cpufreq-nforce2.c 8.96 KB
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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 * (C) 2004-2006  Sebastian Witt <se.witt@gmx.net>
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 *
 *  Based upon reverse engineered information
 *
 *  BIG FAT DISCLAIMER: Work in progress code. Possibly *dangerous*
 */

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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt

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#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/cpufreq.h>
#include <linux/pci.h>
#include <linux/delay.h>

#define NFORCE2_XTAL 25
#define NFORCE2_BOOTFSB 0x48
#define NFORCE2_PLLENABLE 0xa8
#define NFORCE2_PLLREG 0xa4
#define NFORCE2_PLLADR 0xa0
#define NFORCE2_PLL(mul, div) (0x100000 | (mul << 8) | div)

#define NFORCE2_MIN_FSB 50
#define NFORCE2_SAFE_DISTANCE 50

/* Delay in ms between FSB changes */
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/* #define NFORCE2_DELAY 10 */
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/*
 * nforce2_chipset:
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 * FSB is changed using the chipset
 */
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static struct pci_dev *nforce2_dev;
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/* fid:
 * multiplier * 10
 */
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static int fid;
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/* min_fsb, max_fsb:
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 * minimum and maximum FSB (= FSB at boot time)
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 */
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static int min_fsb;
static int max_fsb;
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MODULE_AUTHOR("Sebastian Witt <se.witt@gmx.net>");
MODULE_DESCRIPTION("nForce2 FSB changing cpufreq driver");
MODULE_LICENSE("GPL");

module_param(fid, int, 0444);
module_param(min_fsb, int, 0444);

MODULE_PARM_DESC(fid, "CPU multiplier to use (11.5 = 115)");
MODULE_PARM_DESC(min_fsb,
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		"Minimum FSB to use, if not defined: current FSB - 50");
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/**
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 * nforce2_calc_fsb - calculate FSB
 * @pll: PLL value
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 *
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 *   Calculates FSB from PLL value
 */
static int nforce2_calc_fsb(int pll)
{
	unsigned char mul, div;

	mul = (pll >> 8) & 0xff;
	div = pll & 0xff;

	if (div > 0)
		return NFORCE2_XTAL * mul / div;

	return 0;
}

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/**
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 * nforce2_calc_pll - calculate PLL value
 * @fsb: FSB
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 *
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 *   Calculate PLL value for given FSB
 */
static int nforce2_calc_pll(unsigned int fsb)
{
	unsigned char xmul, xdiv;
	unsigned char mul = 0, div = 0;
	int tried = 0;

	/* Try to calculate multiplier and divider up to 4 times */
	while (((mul == 0) || (div == 0)) && (tried <= 3)) {
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		for (xdiv = 2; xdiv <= 0x80; xdiv++)
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			for (xmul = 1; xmul <= 0xfe; xmul++)
				if (nforce2_calc_fsb(NFORCE2_PLL(xmul, xdiv)) ==
				    fsb + tried) {
					mul = xmul;
					div = xdiv;
				}
		tried++;
	}

	if ((mul == 0) || (div == 0))
		return -1;

	return NFORCE2_PLL(mul, div);
}

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/**
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 * nforce2_write_pll - write PLL value to chipset
 * @pll: PLL value
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 *
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 *   Writes new FSB PLL value to chipset
 */
static void nforce2_write_pll(int pll)
{
	int temp;

	/* Set the pll addr. to 0x00 */
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	pci_write_config_dword(nforce2_dev, NFORCE2_PLLADR, 0);
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	/* Now write the value in all 64 registers */
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	for (temp = 0; temp <= 0x3f; temp++)
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		pci_write_config_dword(nforce2_dev, NFORCE2_PLLREG, pll);
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}

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/**
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 * nforce2_fsb_read - Read FSB
 *
 *   Read FSB from chipset
 *   If bootfsb != 0, return FSB at boot-time
 */
static unsigned int nforce2_fsb_read(int bootfsb)
{
	struct pci_dev *nforce2_sub5;
	u32 fsb, temp = 0;

	/* Get chipset boot FSB from subdevice 5 (FSB at boot-time) */
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	nforce2_sub5 = pci_get_subsys(PCI_VENDOR_ID_NVIDIA, 0x01EF,
				PCI_ANY_ID, PCI_ANY_ID, NULL);
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	if (!nforce2_sub5)
		return 0;

	pci_read_config_dword(nforce2_sub5, NFORCE2_BOOTFSB, &fsb);
	fsb /= 1000000;
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	/* Check if PLL register is already set */
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	pci_read_config_byte(nforce2_dev, NFORCE2_PLLENABLE, (u8 *)&temp);
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	if (bootfsb || !temp)
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		return fsb;
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	/* Use PLL register FSB value */
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	pci_read_config_dword(nforce2_dev, NFORCE2_PLLREG, &temp);
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	fsb = nforce2_calc_fsb(temp);

	return fsb;
}

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/**
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 * nforce2_set_fsb - set new FSB
 * @fsb: New FSB
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 *
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 *   Sets new FSB
 */
static int nforce2_set_fsb(unsigned int fsb)
{
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	u32 temp = 0;
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	unsigned int tfsb;
	int diff;
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	int pll = 0;
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	if ((fsb > max_fsb) || (fsb < NFORCE2_MIN_FSB)) {
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		pr_err("FSB %d is out of range!\n", fsb);
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		return -EINVAL;
	}
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	tfsb = nforce2_fsb_read(0);
	if (!tfsb) {
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		pr_err("Error while reading the FSB\n");
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		return -EINVAL;
	}

	/* First write? Then set actual value */
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	pci_read_config_byte(nforce2_dev, NFORCE2_PLLENABLE, (u8 *)&temp);
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	if (!temp) {
		pll = nforce2_calc_pll(tfsb);

		if (pll < 0)
			return -EINVAL;

		nforce2_write_pll(pll);
	}

	/* Enable write access */
	temp = 0x01;
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	pci_write_config_byte(nforce2_dev, NFORCE2_PLLENABLE, (u8)temp);
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	diff = tfsb - fsb;

	if (!diff)
		return 0;

	while ((tfsb != fsb) && (tfsb <= max_fsb) && (tfsb >= min_fsb)) {
		if (diff < 0)
			tfsb++;
		else
			tfsb--;

		/* Calculate the PLL reg. value */
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		pll = nforce2_calc_pll(tfsb);
		if (pll == -1)
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			return -EINVAL;
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		nforce2_write_pll(pll);
#ifdef NFORCE2_DELAY
		mdelay(NFORCE2_DELAY);
#endif
	}

	temp = 0x40;
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	pci_write_config_byte(nforce2_dev, NFORCE2_PLLADR, (u8)temp);
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	return 0;
}

/**
 * nforce2_get - get the CPU frequency
 * @cpu: CPU number
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 *
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 * Returns the CPU frequency
 */
static unsigned int nforce2_get(unsigned int cpu)
{
	if (cpu)
		return 0;
	return nforce2_fsb_read(0) * fid * 100;
}

/**
 * nforce2_target - set a new CPUFreq policy
 * @policy: new policy
 * @target_freq: the target frequency
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 * @relation: how that frequency relates to achieved frequency
 *  (CPUFREQ_RELATION_L or CPUFREQ_RELATION_H)
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 *
 * Sets a new CPUFreq policy.
 */
static int nforce2_target(struct cpufreq_policy *policy,
			  unsigned int target_freq, unsigned int relation)
{
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/*        unsigned long         flags; */
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	struct cpufreq_freqs freqs;
	unsigned int target_fsb;

	if ((target_freq > policy->max) || (target_freq < policy->min))
		return -EINVAL;

	target_fsb = target_freq / (fid * 100);

	freqs.old = nforce2_get(policy->cpu);
	freqs.new = target_fsb * fid * 100;

	if (freqs.old == freqs.new)
		return 0;

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	pr_debug("Old CPU frequency %d kHz, new %d kHz\n",
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	       freqs.old, freqs.new);

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	cpufreq_freq_transition_begin(policy, &freqs);
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	/* Disable IRQs */
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	/* local_irq_save(flags); */
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	if (nforce2_set_fsb(target_fsb) < 0)
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		pr_err("Changing FSB to %d failed\n", target_fsb);
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	else
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		pr_debug("Changed FSB successfully to %d\n",
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			target_fsb);
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	/* Enable IRQs */
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	/* local_irq_restore(flags); */
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	cpufreq_freq_transition_end(policy, &freqs, 0);
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	return 0;
}

/**
 * nforce2_verify - verifies a new CPUFreq policy
 * @policy: new policy
 */
static int nforce2_verify(struct cpufreq_policy *policy)
{
	unsigned int fsb_pol_max;

	fsb_pol_max = policy->max / (fid * 100);

	if (policy->min < (fsb_pol_max * fid * 100))
		policy->max = (fsb_pol_max + 1) * fid * 100;

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	cpufreq_verify_within_cpu_limits(policy);
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	return 0;
}

static int nforce2_cpu_init(struct cpufreq_policy *policy)
{
	unsigned int fsb;
	unsigned int rfid;

	/* capability check */
	if (policy->cpu != 0)
		return -ENODEV;

	/* Get current FSB */
	fsb = nforce2_fsb_read(0);

	if (!fsb)
		return -EIO;

	/* FIX: Get FID from CPU */
	if (!fid) {
		if (!cpu_khz) {
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			pr_warn("cpu_khz not set, can't calculate multiplier!\n");
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			return -ENODEV;
		}

		fid = cpu_khz / (fsb * 100);
		rfid = fid % 5;

		if (rfid) {
			if (rfid > 2)
				fid += 5 - rfid;
			else
				fid -= rfid;
		}
	}

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	pr_info("FSB currently at %i MHz, FID %d.%d\n",
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		fsb, fid / 10, fid % 10);
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	/* Set maximum FSB to FSB at boot time */
	max_fsb = nforce2_fsb_read(1);
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	if (!max_fsb)
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		return -EIO;

	if (!min_fsb)
		min_fsb = max_fsb - NFORCE2_SAFE_DISTANCE;

	if (min_fsb < NFORCE2_MIN_FSB)
		min_fsb = NFORCE2_MIN_FSB;

	/* cpuinfo and default policy values */
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	policy->min = policy->cpuinfo.min_freq = min_fsb * fid * 100;
	policy->max = policy->cpuinfo.max_freq = max_fsb * fid * 100;
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	return 0;
}

static int nforce2_cpu_exit(struct cpufreq_policy *policy)
{
	return 0;
}

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static struct cpufreq_driver nforce2_driver = {
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	.name = "nforce2",
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	.flags = CPUFREQ_NO_AUTO_DYNAMIC_SWITCHING,
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	.verify = nforce2_verify,
	.target = nforce2_target,
	.get = nforce2_get,
	.init = nforce2_cpu_init,
	.exit = nforce2_cpu_exit,
};

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#ifdef MODULE
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static const struct pci_device_id nforce2_ids[] = {
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	{ PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2 },
	{}
};
MODULE_DEVICE_TABLE(pci, nforce2_ids);
#endif

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/**
 * nforce2_detect_chipset - detect the Southbridge which contains FSB PLL logic
 *
 * Detects nForce2 A2 and C1 stepping
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 *
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 */
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static int nforce2_detect_chipset(void)
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{
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	nforce2_dev = pci_get_subsys(PCI_VENDOR_ID_NVIDIA,
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					PCI_DEVICE_ID_NVIDIA_NFORCE2,
					PCI_ANY_ID, PCI_ANY_ID, NULL);
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	if (nforce2_dev == NULL)
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		return -ENODEV;

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	pr_info("Detected nForce2 chipset revision %X\n",
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		nforce2_dev->revision);
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	pr_info("FSB changing is maybe unstable and can lead to crashes and data loss\n");
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	return 0;
}

/**
 * nforce2_init - initializes the nForce2 CPUFreq driver
 *
 * Initializes the nForce2 FSB support. Returns -ENODEV on unsupported
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 * devices, -EINVAL on problems during initialization, and zero on
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 * success.
 */
static int __init nforce2_init(void)
{
	/* TODO: do we need to detect the processor? */

	/* detect chipset */
	if (nforce2_detect_chipset()) {
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		pr_info("No nForce2 chipset\n");
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		return -ENODEV;
	}

	return cpufreq_register_driver(&nforce2_driver);
}

/**
 * nforce2_exit - unregisters cpufreq module
 *
 *   Unregisters nForce2 FSB change support.
 */
static void __exit nforce2_exit(void)
{
	cpufreq_unregister_driver(&nforce2_driver);
}

module_init(nforce2_init);
module_exit(nforce2_exit);