gpio-pca953x.c 32.3 KB
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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 *  PCA953x 4/8/16/24/40 bit I/O ports
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 *
 *  Copyright (C) 2005 Ben Gardner <bgardner@wabtec.com>
 *  Copyright (C) 2007 Marvell International Ltd.
 *
 *  Derived from drivers/i2c/chips/pca9539.c
 */

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#include <linux/acpi.h>
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#include <linux/gpio/driver.h>
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#include <linux/gpio/consumer.h>
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#include <linux/i2c.h>
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#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of_platform.h>
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#include <linux/platform_data/pca953x.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <linux/slab.h>
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#include <asm/unaligned.h>
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#define PCA953X_INPUT		0x00
#define PCA953X_OUTPUT		0x01
#define PCA953X_INVERT		0x02
#define PCA953X_DIRECTION	0x03
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#define REG_ADDR_MASK		0x3f
#define REG_ADDR_EXT		0x40
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#define REG_ADDR_AI		0x80

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#define PCA957X_IN		0x00
#define PCA957X_INVRT		0x01
#define PCA957X_BKEN		0x02
#define PCA957X_PUPD		0x03
#define PCA957X_CFG		0x04
#define PCA957X_OUT		0x05
#define PCA957X_MSK		0x06
#define PCA957X_INTS		0x07
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#define PCAL953X_OUT_STRENGTH	0x20
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#define PCAL953X_IN_LATCH	0x22
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#define PCAL953X_PULL_EN	0x23
#define PCAL953X_PULL_SEL	0x24
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#define PCAL953X_INT_MASK	0x25
#define PCAL953X_INT_STAT	0x26
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#define PCAL953X_OUT_CONF	0x27
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#define PCAL6524_INT_EDGE	0x28
#define PCAL6524_INT_CLR	0x2a
#define PCAL6524_IN_STATUS	0x2b
#define PCAL6524_OUT_INDCONF	0x2c
#define PCAL6524_DEBOUNCE	0x2d

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#define PCA_GPIO_MASK		0x00FF
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#define PCAL_GPIO_MASK		0x1f
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#define PCAL_PINCTRL_MASK	0x60
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#define PCA_INT			0x0100
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#define PCA_PCAL		0x0200
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#define PCA_LATCH_INT		(PCA_PCAL | PCA_INT)
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#define PCA953X_TYPE		0x1000
#define PCA957X_TYPE		0x2000
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#define PCA_TYPE_MASK		0xF000

#define PCA_CHIP_TYPE(x)	((x) & PCA_TYPE_MASK)
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static const struct i2c_device_id pca953x_id[] = {
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	{ "pca6416", 16 | PCA953X_TYPE | PCA_INT, },
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	{ "pca9505", 40 | PCA953X_TYPE | PCA_INT, },
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	{ "pca9534", 8  | PCA953X_TYPE | PCA_INT, },
	{ "pca9535", 16 | PCA953X_TYPE | PCA_INT, },
	{ "pca9536", 4  | PCA953X_TYPE, },
	{ "pca9537", 4  | PCA953X_TYPE | PCA_INT, },
	{ "pca9538", 8  | PCA953X_TYPE | PCA_INT, },
	{ "pca9539", 16 | PCA953X_TYPE | PCA_INT, },
	{ "pca9554", 8  | PCA953X_TYPE | PCA_INT, },
	{ "pca9555", 16 | PCA953X_TYPE | PCA_INT, },
	{ "pca9556", 8  | PCA953X_TYPE, },
	{ "pca9557", 8  | PCA953X_TYPE, },
	{ "pca9574", 8  | PCA957X_TYPE | PCA_INT, },
	{ "pca9575", 16 | PCA957X_TYPE | PCA_INT, },
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	{ "pca9698", 40 | PCA953X_TYPE, },
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	{ "pcal6416", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
	{ "pcal6524", 24 | PCA953X_TYPE | PCA_LATCH_INT, },
	{ "pcal9555a", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
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	{ "max7310", 8  | PCA953X_TYPE, },
	{ "max7312", 16 | PCA953X_TYPE | PCA_INT, },
	{ "max7313", 16 | PCA953X_TYPE | PCA_INT, },
	{ "max7315", 8  | PCA953X_TYPE | PCA_INT, },
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	{ "max7318", 16 | PCA953X_TYPE | PCA_INT, },
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	{ "pca6107", 8  | PCA953X_TYPE | PCA_INT, },
	{ "tca6408", 8  | PCA953X_TYPE | PCA_INT, },
	{ "tca6416", 16 | PCA953X_TYPE | PCA_INT, },
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	{ "tca6424", 24 | PCA953X_TYPE | PCA_INT, },
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	{ "tca9539", 16 | PCA953X_TYPE | PCA_INT, },
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	{ "tca9554", 8  | PCA953X_TYPE | PCA_INT, },
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	{ "xra1202", 8  | PCA953X_TYPE },
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	{ }
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};
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MODULE_DEVICE_TABLE(i2c, pca953x_id);
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static const struct acpi_device_id pca953x_acpi_ids[] = {
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	{ "INT3491", 16 | PCA953X_TYPE | PCA_LATCH_INT, },
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	{ }
};
MODULE_DEVICE_TABLE(acpi, pca953x_acpi_ids);

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#define MAX_BANK 5
#define BANK_SZ 8

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#define NBANK(chip) DIV_ROUND_UP(chip->gpio_chip.ngpio, BANK_SZ)
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struct pca953x_reg_config {
	int direction;
	int output;
	int input;
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	int invert;
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};

static const struct pca953x_reg_config pca953x_regs = {
	.direction = PCA953X_DIRECTION,
	.output = PCA953X_OUTPUT,
	.input = PCA953X_INPUT,
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	.invert = PCA953X_INVERT,
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};

static const struct pca953x_reg_config pca957x_regs = {
	.direction = PCA957X_CFG,
	.output = PCA957X_OUT,
	.input = PCA957X_IN,
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	.invert = PCA957X_INVRT,
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};

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struct pca953x_chip {
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	unsigned gpio_start;
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	struct mutex i2c_lock;
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	struct regmap *regmap;
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#ifdef CONFIG_GPIO_PCA953X_IRQ
	struct mutex irq_lock;
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	u8 irq_mask[MAX_BANK];
	u8 irq_stat[MAX_BANK];
	u8 irq_trig_raise[MAX_BANK];
	u8 irq_trig_fall[MAX_BANK];
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	struct irq_chip irq_chip;
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#endif
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	atomic_t wakeup_path;
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	struct i2c_client *client;
	struct gpio_chip gpio_chip;
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	const char *const *names;
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	unsigned long driver_data;
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	struct regulator *regulator;
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	const struct pca953x_reg_config *regs;
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};

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static int pca953x_bank_shift(struct pca953x_chip *chip)
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{
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	return fls((chip->gpio_chip.ngpio - 1) / BANK_SZ);
}
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#define PCA953x_BANK_INPUT	BIT(0)
#define PCA953x_BANK_OUTPUT	BIT(1)
#define PCA953x_BANK_POLARITY	BIT(2)
#define PCA953x_BANK_CONFIG	BIT(3)
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#define PCA957x_BANK_INPUT	BIT(0)
#define PCA957x_BANK_POLARITY	BIT(1)
#define PCA957x_BANK_BUSHOLD	BIT(2)
#define PCA957x_BANK_CONFIG	BIT(4)
#define PCA957x_BANK_OUTPUT	BIT(5)

#define PCAL9xxx_BANK_IN_LATCH	BIT(8 + 2)
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#define PCAL9xxx_BANK_PULL_EN	BIT(8 + 3)
#define PCAL9xxx_BANK_PULL_SEL	BIT(8 + 4)
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#define PCAL9xxx_BANK_IRQ_MASK	BIT(8 + 5)
#define PCAL9xxx_BANK_IRQ_STAT	BIT(8 + 6)

/*
 * We care about the following registers:
 * - Standard set, below 0x40, each port can be replicated up to 8 times
 *   - PCA953x standard
 *     Input port			0x00 + 0 * bank_size	R
 *     Output port			0x00 + 1 * bank_size	RW
 *     Polarity Inversion port		0x00 + 2 * bank_size	RW
 *     Configuration port		0x00 + 3 * bank_size	RW
 *   - PCA957x with mixed up registers
 *     Input port			0x00 + 0 * bank_size	R
 *     Polarity Inversion port		0x00 + 1 * bank_size	RW
 *     Bus hold port			0x00 + 2 * bank_size	RW
 *     Configuration port		0x00 + 4 * bank_size	RW
 *     Output port			0x00 + 5 * bank_size	RW
 *
 * - Extended set, above 0x40, often chip specific.
 *   - PCAL6524/PCAL9555A with custom PCAL IRQ handling:
 *     Input latch register		0x40 + 2 * bank_size	RW
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 *     Pull-up/pull-down enable reg	0x40 + 3 * bank_size    RW
 *     Pull-up/pull-down select reg	0x40 + 4 * bank_size    RW
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 *     Interrupt mask register		0x40 + 5 * bank_size	RW
 *     Interrupt status register	0x40 + 6 * bank_size	R
 *
 * - Registers with bit 0x80 set, the AI bit
 *   The bit is cleared and the registers fall into one of the
 *   categories above.
 */

static bool pca953x_check_register(struct pca953x_chip *chip, unsigned int reg,
				   u32 checkbank)
{
	int bank_shift = pca953x_bank_shift(chip);
	int bank = (reg & REG_ADDR_MASK) >> bank_shift;
	int offset = reg & (BIT(bank_shift) - 1);

	/* Special PCAL extended register check. */
	if (reg & REG_ADDR_EXT) {
		if (!(chip->driver_data & PCA_PCAL))
			return false;
		bank += 8;
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	}

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	/* Register is not in the matching bank. */
	if (!(BIT(bank) & checkbank))
		return false;

	/* Register is not within allowed range of bank. */
	if (offset >= NBANK(chip))
		return false;

	return true;
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}

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static bool pca953x_readable_register(struct device *dev, unsigned int reg)
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{
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	struct pca953x_chip *chip = dev_get_drvdata(dev);
	u32 bank;
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	if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) {
		bank = PCA953x_BANK_INPUT | PCA953x_BANK_OUTPUT |
		       PCA953x_BANK_POLARITY | PCA953x_BANK_CONFIG;
	} else {
		bank = PCA957x_BANK_INPUT | PCA957x_BANK_OUTPUT |
		       PCA957x_BANK_POLARITY | PCA957x_BANK_CONFIG |
		       PCA957x_BANK_BUSHOLD;
	}
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	if (chip->driver_data & PCA_PCAL) {
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		bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN |
			PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK |
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			PCAL9xxx_BANK_IRQ_STAT;
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	}

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	return pca953x_check_register(chip, reg, bank);
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}

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static bool pca953x_writeable_register(struct device *dev, unsigned int reg)
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{
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	struct pca953x_chip *chip = dev_get_drvdata(dev);
	u32 bank;
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	if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) {
		bank = PCA953x_BANK_OUTPUT | PCA953x_BANK_POLARITY |
			PCA953x_BANK_CONFIG;
	} else {
		bank = PCA957x_BANK_OUTPUT | PCA957x_BANK_POLARITY |
			PCA957x_BANK_CONFIG | PCA957x_BANK_BUSHOLD;
	}
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	if (chip->driver_data & PCA_PCAL)
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		bank |= PCAL9xxx_BANK_IN_LATCH | PCAL9xxx_BANK_PULL_EN |
			PCAL9xxx_BANK_PULL_SEL | PCAL9xxx_BANK_IRQ_MASK;
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	return pca953x_check_register(chip, reg, bank);
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}

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static bool pca953x_volatile_register(struct device *dev, unsigned int reg)
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{
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	struct pca953x_chip *chip = dev_get_drvdata(dev);
	u32 bank;
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	if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE)
		bank = PCA953x_BANK_INPUT;
	else
		bank = PCA957x_BANK_INPUT;

	if (chip->driver_data & PCA_PCAL)
		bank |= PCAL9xxx_BANK_IRQ_STAT;
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	return pca953x_check_register(chip, reg, bank);
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}
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static const struct regmap_config pca953x_i2c_regmap = {
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	.reg_bits = 8,
	.val_bits = 8,

	.readable_reg = pca953x_readable_register,
	.writeable_reg = pca953x_writeable_register,
	.volatile_reg = pca953x_volatile_register,

	.cache_type = REGCACHE_RBTREE,
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	/* REVISIT: should be 0x7f but some 24 bit chips use REG_ADDR_AI */
	.max_register = 0xff,
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};

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static u8 pca953x_recalc_addr(struct pca953x_chip *chip, int reg, int off,
			      bool write, bool addrinc)
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{
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	int bank_shift = pca953x_bank_shift(chip);
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	int addr = (reg & PCAL_GPIO_MASK) << bank_shift;
	int pinctrl = (reg & PCAL_PINCTRL_MASK) << 1;
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	u8 regaddr = pinctrl | addr | (off / BANK_SZ);

	/* Single byte read doesn't need AI bit set. */
	if (!addrinc)
		return regaddr;

	/* Chips with 24 and more GPIOs always support Auto Increment */
	if (write && NBANK(chip) > 2)
		regaddr |= REG_ADDR_AI;
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	/* PCA9575 needs address-increment on multi-byte writes */
	if (PCA_CHIP_TYPE(chip->driver_data) == PCA957X_TYPE)
		regaddr |= REG_ADDR_AI;

	return regaddr;
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}

static int pca953x_write_regs(struct pca953x_chip *chip, int reg, u8 *val)
{
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	u8 regaddr = pca953x_recalc_addr(chip, reg, 0, true, true);
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	int ret;
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	ret = regmap_bulk_write(chip->regmap, regaddr, val, NBANK(chip));
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	if (ret < 0) {
		dev_err(&chip->client->dev, "failed writing register\n");
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		return ret;
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	}

	return 0;
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}

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static int pca953x_read_regs(struct pca953x_chip *chip, int reg, u8 *val)
{
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	u8 regaddr = pca953x_recalc_addr(chip, reg, 0, false, true);
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	int ret;

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	ret = regmap_bulk_read(chip->regmap, regaddr, val, NBANK(chip));
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	if (ret < 0) {
		dev_err(&chip->client->dev, "failed reading register\n");
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		return ret;
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	}

	return 0;
}

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static int pca953x_gpio_direction_input(struct gpio_chip *gc, unsigned off)
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{
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	struct pca953x_chip *chip = gpiochip_get_data(gc);
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	u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off,
					true, false);
	u8 bit = BIT(off % BANK_SZ);
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	int ret;
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	mutex_lock(&chip->i2c_lock);
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	ret = regmap_write_bits(chip->regmap, dirreg, bit, bit);
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	mutex_unlock(&chip->i2c_lock);
	return ret;
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}

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static int pca953x_gpio_direction_output(struct gpio_chip *gc,
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		unsigned off, int val)
{
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	struct pca953x_chip *chip = gpiochip_get_data(gc);
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	u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off,
					true, false);
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	u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off,
					true, false);
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	u8 bit = BIT(off % BANK_SZ);
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	int ret;
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	mutex_lock(&chip->i2c_lock);
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	/* set output level */
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	ret = regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
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	if (ret)
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		goto exit;
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	/* then direction */
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	ret = regmap_write_bits(chip->regmap, dirreg, bit, 0);
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exit:
	mutex_unlock(&chip->i2c_lock);
	return ret;
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}

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static int pca953x_gpio_get_value(struct gpio_chip *gc, unsigned off)
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{
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	struct pca953x_chip *chip = gpiochip_get_data(gc);
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	u8 inreg = pca953x_recalc_addr(chip, chip->regs->input, off,
				       true, false);
	u8 bit = BIT(off % BANK_SZ);
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	u32 reg_val;
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	int ret;
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	mutex_lock(&chip->i2c_lock);
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	ret = regmap_read(chip->regmap, inreg, &reg_val);
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	mutex_unlock(&chip->i2c_lock);
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	if (ret < 0) {
		/* NOTE:  diagnostic already emitted; that's all we should
		 * do unless gpio_*_value_cansleep() calls become different
		 * from their nonsleeping siblings (and report faults).
		 */
		return 0;
	}

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	return !!(reg_val & bit);
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}

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static void pca953x_gpio_set_value(struct gpio_chip *gc, unsigned off, int val)
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{
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	struct pca953x_chip *chip = gpiochip_get_data(gc);
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	u8 outreg = pca953x_recalc_addr(chip, chip->regs->output, off,
					true, false);
	u8 bit = BIT(off % BANK_SZ);
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	mutex_lock(&chip->i2c_lock);
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	regmap_write_bits(chip->regmap, outreg, bit, val ? bit : 0);
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	mutex_unlock(&chip->i2c_lock);
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}

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static int pca953x_gpio_get_direction(struct gpio_chip *gc, unsigned off)
{
	struct pca953x_chip *chip = gpiochip_get_data(gc);
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	u8 dirreg = pca953x_recalc_addr(chip, chip->regs->direction, off,
					true, false);
	u8 bit = BIT(off % BANK_SZ);
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	u32 reg_val;
	int ret;

	mutex_lock(&chip->i2c_lock);
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	ret = regmap_read(chip->regmap, dirreg, &reg_val);
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	mutex_unlock(&chip->i2c_lock);
	if (ret < 0)
		return ret;

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	return !!(reg_val & bit);
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}

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static void pca953x_gpio_set_multiple(struct gpio_chip *gc,
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				      unsigned long *mask, unsigned long *bits)
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{
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	struct pca953x_chip *chip = gpiochip_get_data(gc);
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	unsigned int bank_mask, bank_val;
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	int bank;
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	u8 reg_val[MAX_BANK];
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	int ret;
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	mutex_lock(&chip->i2c_lock);
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	ret = pca953x_read_regs(chip, chip->regs->output, reg_val);
	if (ret)
		goto exit;

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	for (bank = 0; bank < NBANK(chip); bank++) {
		bank_mask = mask[bank / sizeof(*mask)] >>
			   ((bank % sizeof(*mask)) * 8);
		if (bank_mask) {
			bank_val = bits[bank / sizeof(*bits)] >>
				  ((bank % sizeof(*bits)) * 8);
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			bank_val &= bank_mask;
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			reg_val[bank] = (reg_val[bank] & ~bank_mask) | bank_val;
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		}
	}
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	pca953x_write_regs(chip, chip->regs->output, reg_val);
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exit:
	mutex_unlock(&chip->i2c_lock);
}

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static int pca953x_gpio_set_pull_up_down(struct pca953x_chip *chip,
					 unsigned int offset,
					 unsigned long config)
{
	u8 pull_en_reg = pca953x_recalc_addr(chip, PCAL953X_PULL_EN, offset,
					     true, false);
	u8 pull_sel_reg = pca953x_recalc_addr(chip, PCAL953X_PULL_SEL, offset,
					      true, false);
	u8 bit = BIT(offset % BANK_SZ);
	int ret;

	/*
	 * pull-up/pull-down configuration requires PCAL extended
	 * registers
	 */
	if (!(chip->driver_data & PCA_PCAL))
		return -ENOTSUPP;

	mutex_lock(&chip->i2c_lock);

	/* Disable pull-up/pull-down */
	ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, 0);
	if (ret)
		goto exit;

	/* Configure pull-up/pull-down */
	if (config == PIN_CONFIG_BIAS_PULL_UP)
		ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, bit);
	else if (config == PIN_CONFIG_BIAS_PULL_DOWN)
		ret = regmap_write_bits(chip->regmap, pull_sel_reg, bit, 0);
	if (ret)
		goto exit;

	/* Enable pull-up/pull-down */
	ret = regmap_write_bits(chip->regmap, pull_en_reg, bit, bit);

exit:
	mutex_unlock(&chip->i2c_lock);
	return ret;
}

static int pca953x_gpio_set_config(struct gpio_chip *gc, unsigned int offset,
				   unsigned long config)
{
	struct pca953x_chip *chip = gpiochip_get_data(gc);

	switch (config) {
	case PIN_CONFIG_BIAS_PULL_UP:
	case PIN_CONFIG_BIAS_PULL_DOWN:
		return pca953x_gpio_set_pull_up_down(chip, offset, config);
	default:
		return -ENOTSUPP;
	}
}

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static void pca953x_setup_gpio(struct pca953x_chip *chip, int gpios)
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{
	struct gpio_chip *gc;

	gc = &chip->gpio_chip;

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	gc->direction_input  = pca953x_gpio_direction_input;
	gc->direction_output = pca953x_gpio_direction_output;
	gc->get = pca953x_gpio_get_value;
	gc->set = pca953x_gpio_set_value;
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	gc->get_direction = pca953x_gpio_get_direction;
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	gc->set_multiple = pca953x_gpio_set_multiple;
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	gc->set_config = pca953x_gpio_set_config;
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	gc->can_sleep = true;
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	gc->base = chip->gpio_start;
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	gc->ngpio = gpios;
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	gc->label = dev_name(&chip->client->dev);
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	gc->parent = &chip->client->dev;
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	gc->owner = THIS_MODULE;
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	gc->names = chip->names;
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}

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#ifdef CONFIG_GPIO_PCA953X_IRQ
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static void pca953x_irq_mask(struct irq_data *d)
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{
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	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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	struct pca953x_chip *chip = gpiochip_get_data(gc);
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	chip->irq_mask[d->hwirq / BANK_SZ] &= ~(1 << (d->hwirq % BANK_SZ));
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}

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static void pca953x_irq_unmask(struct irq_data *d)
572
{
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	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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	struct pca953x_chip *chip = gpiochip_get_data(gc);
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576
	chip->irq_mask[d->hwirq / BANK_SZ] |= 1 << (d->hwirq % BANK_SZ);
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}

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static int pca953x_irq_set_wake(struct irq_data *d, unsigned int on)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct pca953x_chip *chip = gpiochip_get_data(gc);

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	if (on)
		atomic_inc(&chip->wakeup_path);
	else
		atomic_dec(&chip->wakeup_path);

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	return irq_set_irq_wake(chip->client->irq, on);
}

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static void pca953x_irq_bus_lock(struct irq_data *d)
593
{
594
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
595
	struct pca953x_chip *chip = gpiochip_get_data(gc);
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	mutex_lock(&chip->irq_lock);
}

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static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
601
{
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	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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	struct pca953x_chip *chip = gpiochip_get_data(gc);
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	u8 new_irqs;
	int level, i;
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	u8 invert_irq_mask[MAX_BANK];
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	u8 reg_direction[MAX_BANK];
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609
	pca953x_read_regs(chip, chip->regs->direction, reg_direction);
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	if (chip->driver_data & PCA_PCAL) {
		/* Enable latch on interrupt-enabled inputs */
		pca953x_write_regs(chip, PCAL953X_IN_LATCH, chip->irq_mask);

		for (i = 0; i < NBANK(chip); i++)
			invert_irq_mask[i] = ~chip->irq_mask[i];

		/* Unmask enabled interrupts */
		pca953x_write_regs(chip, PCAL953X_INT_MASK, invert_irq_mask);
	}
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	/* Look for any newly setup interrupt */
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	for (i = 0; i < NBANK(chip); i++) {
		new_irqs = chip->irq_trig_fall[i] | chip->irq_trig_raise[i];
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		new_irqs &= reg_direction[i];
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		while (new_irqs) {
			level = __ffs(new_irqs);
			pca953x_gpio_direction_input(&chip->gpio_chip,
							level + (BANK_SZ * i));
			new_irqs &= ~(1 << level);
		}
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	}
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	mutex_unlock(&chip->irq_lock);
}

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static int pca953x_irq_set_type(struct irq_data *d, unsigned int type)
639
{
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	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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	struct pca953x_chip *chip = gpiochip_get_data(gc);
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	int bank_nb = d->hwirq / BANK_SZ;
	u8 mask = 1 << (d->hwirq % BANK_SZ);
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	if (!(type & IRQ_TYPE_EDGE_BOTH)) {
		dev_err(&chip->client->dev, "irq %d: unsupported type %d\n",
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			d->irq, type);
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		return -EINVAL;
	}

	if (type & IRQ_TYPE_EDGE_FALLING)
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		chip->irq_trig_fall[bank_nb] |= mask;
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	else
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		chip->irq_trig_fall[bank_nb] &= ~mask;
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	if (type & IRQ_TYPE_EDGE_RISING)
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		chip->irq_trig_raise[bank_nb] |= mask;
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	else
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		chip->irq_trig_raise[bank_nb] &= ~mask;
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	return 0;
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}

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static void pca953x_irq_shutdown(struct irq_data *d)
{
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	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct pca953x_chip *chip = gpiochip_get_data(gc);
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	u8 mask = 1 << (d->hwirq % BANK_SZ);

	chip->irq_trig_raise[d->hwirq / BANK_SZ] &= ~mask;
	chip->irq_trig_fall[d->hwirq / BANK_SZ] &= ~mask;
}

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static bool pca953x_irq_pending(struct pca953x_chip *chip, u8 *pending)
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{
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	u8 cur_stat[MAX_BANK];
	u8 old_stat[MAX_BANK];
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	bool pending_seen = false;
	bool trigger_seen = false;
	u8 trigger[MAX_BANK];
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	u8 reg_direction[MAX_BANK];
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	int ret, i;
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	if (chip->driver_data & PCA_PCAL) {
		/* Read the current interrupt status from the device */
		ret = pca953x_read_regs(chip, PCAL953X_INT_STAT, trigger);
		if (ret)
			return false;

		/* Check latched inputs and clear interrupt status */
		ret = pca953x_read_regs(chip, PCA953X_INPUT, cur_stat);
		if (ret)
			return false;

		for (i = 0; i < NBANK(chip); i++) {
			/* Apply filter for rising/falling edge selection */
			pending[i] = (~cur_stat[i] & chip->irq_trig_fall[i]) |
				(cur_stat[i] & chip->irq_trig_raise[i]);
			pending[i] &= trigger[i];
			if (pending[i])
				pending_seen = true;
		}

		return pending_seen;
	}

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	ret = pca953x_read_regs(chip, chip->regs->input, cur_stat);
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	if (ret)
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		return false;
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	/* Remove output pins from the equation */
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	pca953x_read_regs(chip, chip->regs->direction, reg_direction);
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	for (i = 0; i < NBANK(chip); i++)
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		cur_stat[i] &= reg_direction[i];
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	memcpy(old_stat, chip->irq_stat, NBANK(chip));
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	for (i = 0; i < NBANK(chip); i++) {
		trigger[i] = (cur_stat[i] ^ old_stat[i]) & chip->irq_mask[i];
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		if (trigger[i])
			trigger_seen = true;
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	}

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	if (!trigger_seen)
		return false;
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	memcpy(chip->irq_stat, cur_stat, NBANK(chip));
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	for (i = 0; i < NBANK(chip); i++) {
		pending[i] = (old_stat[i] & chip->irq_trig_fall[i]) |
			(cur_stat[i] & chip->irq_trig_raise[i]);
		pending[i] &= trigger[i];
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		if (pending[i])
			pending_seen = true;
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	}
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	return pending_seen;
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}

static irqreturn_t pca953x_irq_handler(int irq, void *devid)
{
	struct pca953x_chip *chip = devid;
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	u8 pending[MAX_BANK];
	u8 level;
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	unsigned nhandled = 0;
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	int i;
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	if (!pca953x_irq_pending(chip, pending))
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		return IRQ_NONE;
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	for (i = 0; i < NBANK(chip); i++) {
		while (pending[i]) {
			level = __ffs(pending[i]);
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			handle_nested_irq(irq_find_mapping(chip->gpio_chip.irq.domain,
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							level + (BANK_SZ * i)));
			pending[i] &= ~(1 << level);
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			nhandled++;
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		}
	}
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761
	return (nhandled > 0) ? IRQ_HANDLED : IRQ_NONE;
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}

static int pca953x_irq_setup(struct pca953x_chip *chip,
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			     int irq_base)
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{
	struct i2c_client *client = chip->client;
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	struct irq_chip *irq_chip = &chip->irq_chip;
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	u8 reg_direction[MAX_BANK];
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	int ret, i;
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	if (!client->irq)
		return 0;
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	if (irq_base == -1)
		return 0;
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	if (!(chip->driver_data & PCA_INT))
		return 0;
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	ret = pca953x_read_regs(chip, chip->regs->input, chip->irq_stat);
	if (ret)
		return ret;

	/*
	 * There is no way to know which GPIO line generated the
	 * interrupt.  We have to rely on the previous read for
	 * this purpose.
	 */
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	pca953x_read_regs(chip, chip->regs->direction, reg_direction);
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	for (i = 0; i < NBANK(chip); i++)
		chip->irq_stat[i] &= reg_direction[i];
	mutex_init(&chip->irq_lock);

	ret = devm_request_threaded_irq(&client->dev, client->irq,
					NULL, pca953x_irq_handler,
					IRQF_TRIGGER_LOW | IRQF_ONESHOT |
					IRQF_SHARED,
					dev_name(&client->dev), chip);
	if (ret) {
		dev_err(&client->dev, "failed to request irq %d\n",
			client->irq);
		return ret;
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	}

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	irq_chip->name = dev_name(&chip->client->dev);
	irq_chip->irq_mask = pca953x_irq_mask;
	irq_chip->irq_unmask = pca953x_irq_unmask;
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	irq_chip->irq_set_wake = pca953x_irq_set_wake;
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	irq_chip->irq_bus_lock = pca953x_irq_bus_lock;
	irq_chip->irq_bus_sync_unlock = pca953x_irq_bus_sync_unlock;
	irq_chip->irq_set_type = pca953x_irq_set_type;
	irq_chip->irq_shutdown = pca953x_irq_shutdown;

	ret =  gpiochip_irqchip_add_nested(&chip->gpio_chip, irq_chip,
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					   irq_base, handle_simple_irq,
					   IRQ_TYPE_NONE);
	if (ret) {
		dev_err(&client->dev,
			"could not connect irqchip to gpiochip\n");
		return ret;
	}

824
	gpiochip_set_nested_irqchip(&chip->gpio_chip, irq_chip, client->irq);
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	return 0;
}

#else /* CONFIG_GPIO_PCA953X_IRQ */
static int pca953x_irq_setup(struct pca953x_chip *chip,
831
			     int irq_base)
832 833 834
{
	struct i2c_client *client = chip->client;

835
	if (client->irq && irq_base != -1 && (chip->driver_data & PCA_INT))
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		dev_warn(&client->dev, "interrupt support not compiled in\n");

	return 0;
}
#endif

842
static int device_pca95xx_init(struct pca953x_chip *chip, u32 invert)
843 844
{
	int ret;
845
	u8 val[MAX_BANK];
846

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	ret = regcache_sync_region(chip->regmap, chip->regs->output,
				   chip->regs->output + NBANK(chip));
	if (ret != 0)
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		goto out;

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	ret = regcache_sync_region(chip->regmap, chip->regs->direction,
				   chip->regs->direction + NBANK(chip));
	if (ret != 0)
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		goto out;

	/* set platform specific polarity inversion */
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	if (invert)
		memset(val, 0xFF, NBANK(chip));
	else
		memset(val, 0, NBANK(chip));

863
	ret = pca953x_write_regs(chip, chip->regs->invert, val);
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out:
	return ret;
}

868
static int device_pca957x_init(struct pca953x_chip *chip, u32 invert)
869 870
{
	int ret;
871
	u8 val[MAX_BANK];
872

873
	ret = device_pca95xx_init(chip, invert);
874 875
	if (ret)
		goto out;
876

877
	/* To enable register 6, 7 to control pull up and pull down */
878
	memset(val, 0x02, NBANK(chip));
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	ret = pca953x_write_regs(chip, PCA957X_BKEN, val);
	if (ret)
		goto out;
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	return 0;
out:
	return ret;
}

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static const struct of_device_id pca953x_dt_ids[];

890
static int pca953x_probe(struct i2c_client *client,
891
				   const struct i2c_device_id *i2c_id)
892
{
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	struct pca953x_platform_data *pdata;
	struct pca953x_chip *chip;
895
	int irq_base = 0;
896
	int ret;
897
	u32 invert = 0;
898
	struct regulator *reg;
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	chip = devm_kzalloc(&client->dev,
			sizeof(struct pca953x_chip), GFP_KERNEL);
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	if (chip == NULL)
		return -ENOMEM;

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Jingoo Han committed
905
	pdata = dev_get_platdata(&client->dev);
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	if (pdata) {
		irq_base = pdata->irq_base;
		chip->gpio_start = pdata->gpio_base;
		invert = pdata->invert;
		chip->names = pdata->names;
	} else {
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		struct gpio_desc *reset_gpio;

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		chip->gpio_start = -1;
		irq_base = 0;
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		/*
		 * See if we need to de-assert a reset pin.
		 *
		 * There is no known ACPI-enabled platforms that are
		 * using "reset" GPIO. Otherwise any of those platform
		 * must use _DSD method with corresponding property.
		 */
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		reset_gpio = devm_gpiod_get_optional(&client->dev, "reset",
						     GPIOD_OUT_LOW);
		if (IS_ERR(reset_gpio))
			return PTR_ERR(reset_gpio);
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	}
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	chip->client = client;

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	reg = devm_regulator_get(&client->dev, "vcc");
	if (IS_ERR(reg)) {
		ret = PTR_ERR(reg);
		if (ret != -EPROBE_DEFER)
			dev_err(&client->dev, "reg get err: %d\n", ret);
		return ret;
	}
	ret = regulator_enable(reg);
	if (ret) {
		dev_err(&client->dev, "reg en err: %d\n", ret);
		return ret;
	}
	chip->regulator = reg;

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	if (i2c_id) {
		chip->driver_data = i2c_id->driver_data;
948
	} else {
949
		const struct acpi_device_id *acpi_id;
950
		struct device *dev = &client->dev;
951

952 953 954
		chip->driver_data = (uintptr_t)of_device_get_match_data(dev);
		if (!chip->driver_data) {
			acpi_id = acpi_match_device(pca953x_acpi_ids, dev);
955
			if (!acpi_id) {
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				ret = -ENODEV;
				goto err_exit;
			}
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960
			chip->driver_data = acpi_id->driver_data;
961
		}
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	}

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	i2c_set_clientdata(client, chip);

	chip->regmap = devm_regmap_init_i2c(client, &pca953x_i2c_regmap);
	if (IS_ERR(chip->regmap)) {
		ret = PTR_ERR(chip->regmap);
		goto err_exit;
	}

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	regcache_mark_dirty(chip->regmap);

974
	mutex_init(&chip->i2c_lock);
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	/*
	 * In case we have an i2c-mux controlled by a GPIO provided by an
	 * expander using the same driver higher on the device tree, read the
	 * i2c adapter nesting depth and use the retrieved value as lockdep
	 * subclass for chip->i2c_lock.
	 *
	 * REVISIT: This solution is not complete. It protects us from lockdep
	 * false positives when the expander controlling the i2c-mux is on
	 * a different level on the device tree, but not when it's on the same
	 * level on a different branch (in which case the subclass number
	 * would be the same).
	 *
	 * TODO: Once a correct solution is developed, a similar fix should be
	 * applied to all other i2c-controlled GPIO expanders (and potentially
	 * regmap-i2c).
	 */
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	lockdep_set_subclass(&chip->i2c_lock,
			     i2c_adapter_depth(client->adapter));
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	/* initialize cached registers from their original values.
	 * we can't share this chip with another i2c master.
	 */
997
	pca953x_setup_gpio(chip, chip->driver_data & PCA_GPIO_MASK);
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999 1000 1001
	if (PCA_CHIP_TYPE(chip->driver_data) == PCA953X_TYPE) {
		chip->regs = &pca953x_regs;
		ret = device_pca95xx_init(chip, invert);
1002
	} else {
1003
		chip->regs = &pca957x_regs;
1004
		ret = device_pca957x_init(chip, invert);
1005
	}
1006
	if (ret)
1007
		goto err_exit;
1008

1009
	ret = devm_gpiochip_add_data(&client->dev, &chip->gpio_chip, chip);
1010
	if (ret)
1011
		goto err_exit;
1012

1013
	ret = pca953x_irq_setup(chip, irq_base);
1014
	if (ret)