gpio-sch.c 5.05 KB
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// SPDX-License-Identifier: GPL-2.0
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/*
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 * GPIO interface for Intel Poulsbo SCH
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 *
 *  Copyright (c) 2010 CompuLab Ltd
 *  Author: Denis Turischev <denis@compulab.co.il>
 */

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#include <linux/acpi.h>
#include <linux/errno.h>
#include <linux/gpio/driver.h>
#include <linux/io.h>
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#include <linux/kernel.h>
#include <linux/module.h>
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#include <linux/pci_ids.h>
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#include <linux/platform_device.h>
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#define GEN	0x00
#define GIO	0x04
#define GLV	0x08

struct sch_gpio {
	struct gpio_chip chip;
	spinlock_t lock;
	unsigned short iobase;
	unsigned short resume_base;
};
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static unsigned sch_gpio_offset(struct sch_gpio *sch, unsigned gpio,
				unsigned reg)
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{
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	unsigned base = 0;
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	if (gpio >= sch->resume_base) {
		gpio -= sch->resume_base;
		base += 0x20;
	}
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	return base + reg + gpio / 8;
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}

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static unsigned sch_gpio_bit(struct sch_gpio *sch, unsigned gpio)
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{
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	if (gpio >= sch->resume_base)
		gpio -= sch->resume_base;
	return gpio % 8;
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}

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static int sch_gpio_reg_get(struct sch_gpio *sch, unsigned gpio, unsigned reg)
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{
	unsigned short offset, bit;
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	u8 reg_val;
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	offset = sch_gpio_offset(sch, gpio, reg);
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	bit = sch_gpio_bit(sch, gpio);
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	reg_val = !!(inb(sch->iobase + offset) & BIT(bit));
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	return reg_val;
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}

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static void sch_gpio_reg_set(struct sch_gpio *sch, unsigned gpio, unsigned reg,
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			     int val)
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{
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	unsigned short offset, bit;
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	u8 reg_val;
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	offset = sch_gpio_offset(sch, gpio, reg);
	bit = sch_gpio_bit(sch, gpio);
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	reg_val = inb(sch->iobase + offset);
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	if (val)
		outb(reg_val | BIT(bit), sch->iobase + offset);
	else
		outb((reg_val & ~BIT(bit)), sch->iobase + offset);
}
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static int sch_gpio_direction_in(struct gpio_chip *gc, unsigned gpio_num)
{
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	struct sch_gpio *sch = gpiochip_get_data(gc);
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	spin_lock(&sch->lock);
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	sch_gpio_reg_set(sch, gpio_num, GIO, 1);
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	spin_unlock(&sch->lock);
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	return 0;
}

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static int sch_gpio_get(struct gpio_chip *gc, unsigned gpio_num)
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{
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	struct sch_gpio *sch = gpiochip_get_data(gc);
	return sch_gpio_reg_get(sch, gpio_num, GLV);
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}

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static void sch_gpio_set(struct gpio_chip *gc, unsigned gpio_num, int val)
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{
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	struct sch_gpio *sch = gpiochip_get_data(gc);
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	spin_lock(&sch->lock);
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	sch_gpio_reg_set(sch, gpio_num, GLV, val);
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	spin_unlock(&sch->lock);
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}

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static int sch_gpio_direction_out(struct gpio_chip *gc, unsigned gpio_num,
				  int val)
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{
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	struct sch_gpio *sch = gpiochip_get_data(gc);
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	spin_lock(&sch->lock);
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	sch_gpio_reg_set(sch, gpio_num, GIO, 0);
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	spin_unlock(&sch->lock);
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	/*
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	 * according to the datasheet, writing to the level register has no
	 * effect when GPIO is programmed as input.
	 * Actually the the level register is read-only when configured as input.
	 * Thus presetting the output level before switching to output is _NOT_ possible.
	 * Hence we set the level after configuring the GPIO as output.
	 * But we cannot prevent a short low pulse if direction is set to high
	 * and an external pull-up is connected.
	 */
	sch_gpio_set(gc, gpio_num, val);
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	return 0;
}

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static int sch_gpio_get_direction(struct gpio_chip *gc, unsigned gpio_num)
{
	struct sch_gpio *sch = gpiochip_get_data(gc);

	return sch_gpio_reg_get(sch, gpio_num, GIO);
}

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static const struct gpio_chip sch_gpio_chip = {
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	.label			= "sch_gpio",
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	.owner			= THIS_MODULE,
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	.direction_input	= sch_gpio_direction_in,
	.get			= sch_gpio_get,
	.direction_output	= sch_gpio_direction_out,
	.set			= sch_gpio_set,
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	.get_direction		= sch_gpio_get_direction,
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};

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static int sch_gpio_probe(struct platform_device *pdev)
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{
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	struct sch_gpio *sch;
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	struct resource *res;
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	sch = devm_kzalloc(&pdev->dev, sizeof(*sch), GFP_KERNEL);
	if (!sch)
		return -ENOMEM;
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	res = platform_get_resource(pdev, IORESOURCE_IO, 0);
	if (!res)
		return -EBUSY;

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	if (!devm_request_region(&pdev->dev, res->start, resource_size(res),
				 pdev->name))
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		return -EBUSY;

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	spin_lock_init(&sch->lock);
	sch->iobase = res->start;
	sch->chip = sch_gpio_chip;
	sch->chip.label = dev_name(&pdev->dev);
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	sch->chip.parent = &pdev->dev;
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	switch (pdev->id) {
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	case PCI_DEVICE_ID_INTEL_SCH_LPC:
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		sch->resume_base = 10;
		sch->chip.ngpio = 14;

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		/*
		 * GPIO[6:0] enabled by default
		 * GPIO7 is configured by the CMC as SLPIOVR
		 * Enable GPIO[9:8] core powered gpios explicitly
		 */
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		sch_gpio_reg_set(sch, 8, GEN, 1);
		sch_gpio_reg_set(sch, 9, GEN, 1);
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		/*
		 * SUS_GPIO[2:0] enabled by default
		 * Enable SUS_GPIO3 resume powered gpio explicitly
		 */
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		sch_gpio_reg_set(sch, 13, GEN, 1);
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		break;

	case PCI_DEVICE_ID_INTEL_ITC_LPC:
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		sch->resume_base = 5;
		sch->chip.ngpio = 14;
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		break;

	case PCI_DEVICE_ID_INTEL_CENTERTON_ILB:
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		sch->resume_base = 21;
		sch->chip.ngpio = 30;
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		break;

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	case PCI_DEVICE_ID_INTEL_QUARK_X1000_ILB:
		sch->resume_base = 2;
		sch->chip.ngpio = 8;
		break;

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	default:
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		return -ENODEV;
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	}
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	platform_set_drvdata(pdev, sch);
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	return devm_gpiochip_add_data(&pdev->dev, &sch->chip, sch);
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}

static struct platform_driver sch_gpio_driver = {
	.driver = {
		.name = "sch_gpio",
	},
	.probe		= sch_gpio_probe,
};

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module_platform_driver(sch_gpio_driver);
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MODULE_AUTHOR("Denis Turischev <denis@compulab.co.il>");
MODULE_DESCRIPTION("GPIO interface for Intel Poulsbo SCH");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:sch_gpio");