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    spi: rspi: Fix handling of QSPI code when transmit and receive · 7e95b166
    Hoan Nguyen An authored
    
    
    Process handling QSPI when transmit/receive at qspi_trigger_transfer_out_in() as follows:
    Setting the trigger, is the number of bytes in the FIFO buffer to determine
    when there is an interrupt. Then check if the value of triggering number is
    32-bytes or 1-byte, there will be corresponding processing
    Handling (if (n == QSPI_BUFFER_SIZE) esle) this is unnecessary, leads to the
    same processing of data transmission or reception, The difference here are with
    ret = rspi_wait_for_tx_empty(rspi);
    ret = rspi_wait_for_rx_full(rspi);
    
    When the nummber trigger is 32 bytes, we only write into FIFO when the FIFO is completely empty
    (interrupt transmission), and only receive if FIFO is full of 32 bytes of data.
    
    In the case of a nummber trigger that is 1 byte, in principle we still need to process
    rspi_wait_for_tx_empty/full so that FIFO is empty only with the amount of data we need to write to
    or equal to the number of bytes we need to receive, There is currently no processing of this.
    And in the current case with this patch, at this time it only needs at least 1 byte received in
    FIFO that has interrupt received, or FIFO at least 1bytes free can be written into FIFO,
    This patch therefore does not affect this processing.
    So we need to eliminate unnecessary waste processing (if (n == QSPI_BUFFER_SIZE) esle),
    more precisely in waiting for FIFO status.
    The same with handling in qspi_transfer_out()/qspi_transfer_in().
    
    Signed-off-by: default avatarHoan Nguyen An <na-hoan@jinso.co.jp>
    Signed-off-by: default avatarMark Brown <broonie@kernel.org>
    7e95b166