Commit 14d1524d authored by Stephen Rothwell's avatar Stephen Rothwell

Merge remote-tracking branch 'scsi/for-next'

parents d4ab2653 6de89c8b
......@@ -665,7 +665,7 @@ config SCSI_DMX3191D
config SCSI_GDTH
tristate "Intel/ICP (former GDT SCSI Disk Array) RAID Controller support"
depends on (ISA || EISA || PCI) && SCSI && ISA_DMA_API
depends on PCI && SCSI
---help---
Formerly called GDT SCSI Disk Array Controller Support.
......
......@@ -49,7 +49,7 @@ struct device_attribute;
#define ARCMSR_MAX_OUTSTANDING_CMD 1024
#define ARCMSR_DEFAULT_OUTSTANDING_CMD 128
#define ARCMSR_MIN_OUTSTANDING_CMD 32
#define ARCMSR_DRIVER_VERSION "v1.40.00.09-20180709"
#define ARCMSR_DRIVER_VERSION "v1.40.00.10-20181217"
#define ARCMSR_SCSI_INITIATOR_ID 255
#define ARCMSR_MAX_XFER_SECTORS 512
#define ARCMSR_MAX_XFER_SECTORS_B 4096
......@@ -739,7 +739,7 @@ struct AdapterControlBlock
#define ACB_ADAPTER_TYPE_C 0x00000002 /* hbc L IOP */
#define ACB_ADAPTER_TYPE_D 0x00000003 /* hbd M IOP */
#define ACB_ADAPTER_TYPE_E 0x00000004 /* hba L IOP */
u32 roundup_ccbsize;
u32 ioqueue_size;
struct pci_dev * pdev;
struct Scsi_Host * host;
unsigned long vir2phy_offset;
......@@ -747,6 +747,7 @@ struct AdapterControlBlock
uint32_t outbound_int_enable;
uint32_t cdb_phyaddr_hi32;
uint32_t reg_mu_acc_handle0;
uint64_t cdb_phyadd_hipart;
spinlock_t eh_lock;
spinlock_t ccblist_lock;
spinlock_t postq_lock;
......@@ -855,11 +856,11 @@ struct AdapterControlBlock
*******************************************************************************
*/
struct CommandControlBlock{
/*x32:sizeof struct_CCB=(32+60)byte, x64:sizeof struct_CCB=(64+60)byte*/
/*x32:sizeof struct_CCB=(64+60)byte, x64:sizeof struct_CCB=(64+60)byte*/
struct list_head list; /*x32: 8byte, x64: 16byte*/
struct scsi_cmnd *pcmd; /*8 bytes pointer of linux scsi command */
struct AdapterControlBlock *acb; /*x32: 4byte, x64: 8byte*/
uint32_t cdb_phyaddr; /*x32: 4byte, x64: 4byte*/
unsigned long cdb_phyaddr; /*x32: 4byte, x64: 8byte*/
uint32_t arc_cdb_size; /*x32:4byte,x64:4byte*/
uint16_t ccb_flags; /*x32: 2byte, x64: 2byte*/
#define CCB_FLAG_READ 0x0000
......@@ -875,10 +876,10 @@ struct CommandControlBlock{
uint32_t smid;
#if BITS_PER_LONG == 64
/* ======================512+64 bytes======================== */
uint32_t reserved[4]; /*16 byte*/
uint32_t reserved[3]; /*12 byte*/
#else
/* ======================512+32 bytes======================== */
// uint32_t reserved; /*4 byte*/
uint32_t reserved[8]; /*32 byte*/
#endif
/* ======================================================= */
struct ARCMSR_CDB arcmsr_cdb;
......
This diff is collapsed.
......@@ -577,7 +577,7 @@ static void bnx2i_free_mp_bdt(struct bnx2i_hba *hba)
hba->dummy_buffer, hba->dummy_buf_dma);
hba->dummy_buffer = NULL;
}
return;
return;
}
/**
......
This diff is collapsed.
......@@ -38,17 +38,9 @@
#define OEM_ID_INTEL 0x8000
/* controller classes */
#define GDT_ISA 0x01 /* ISA controller */
#define GDT_EISA 0x02 /* EISA controller */
#define GDT_PCI 0x03 /* PCI controller */
#define GDT_PCINEW 0x04 /* new PCI controller */
#define GDT_PCIMPR 0x05 /* PCI MPR controller */
/* GDT_EISA, controller subtypes EISA */
#define GDT3_ID 0x0130941c /* GDT3000/3020 */
#define GDT3A_ID 0x0230941c /* GDT3000A/3020A/3050A */
#define GDT3B_ID 0x0330941c /* GDT3000B/3010A */
/* GDT_ISA */
#define GDT2_ID 0x0120941c /* GDT2000/2020 */
#ifndef PCI_DEVICE_ID_VORTEX_GDT60x0
/* GDT_PCI */
......@@ -281,17 +273,6 @@
#define GDTH_DATA_IN 0x01000000L /* data from target */
#define GDTH_DATA_OUT 0x00000000L /* data to target */
/* BMIC registers (EISA controllers) */
#define ID0REG 0x0c80 /* board ID */
#define EINTENABREG 0x0c89 /* interrupt enable */
#define SEMA0REG 0x0c8a /* command semaphore */
#define SEMA1REG 0x0c8b /* status semaphore */
#define LDOORREG 0x0c8d /* local doorbell */
#define EDENABREG 0x0c8e /* EISA system doorbell enab. */
#define EDOORREG 0x0c8f /* EISA system doorbell */
#define MAILBOXREG 0x0c90 /* mailbox reg. (16 bytes) */
#define EISAREG 0x0cc0 /* EISA configuration */
/* other defines */
#define LINUX_OS 8 /* used for cache optim. */
#define SECS32 0x1f /* round capacity */
......@@ -706,21 +687,11 @@ typedef struct {
u8 fw_magic; /* contr. ID from firmware */
} __attribute__((packed)) gdt_pci_sram;
/* SRAM structure EISA controllers (but NOT GDT3000/3020) */
typedef struct {
u8 os_used[16]; /* OS code per service */
u16 need_deinit; /* switch betw. BIOS/driver */
u8 switch_support; /* see need_deinit */
u8 padding;
} __attribute__((packed)) gdt_eisa_sram;
/* DPRAM ISA controllers */
typedef struct {
union {
struct {
u8 bios_used[0x3c00-32]; /* 15KB - 32Bytes BIOS */
u32 magic; /* controller (EISA) ID */
u16 need_deinit; /* switch betw. BIOS/driver */
u8 switch_support; /* see need_deinit */
u8 padding[9];
......@@ -843,7 +814,6 @@ typedef struct {
u16 cache_feat; /* feat. cache serv. (s/g,..)*/
u16 raw_feat; /* feat. raw service (s/g,..)*/
u16 screen_feat; /* feat. raw service (s/g,..)*/
u16 bmic; /* BMIC address (EISA) */
void __iomem *brd; /* DPRAM address */
u32 brd_phys; /* slot number/BIOS address */
gdt6c_plx_regs *plx; /* PLX regs (new PCI contr.) */
......
......@@ -27,11 +27,7 @@
#define GDTH_MAXSG 32 /* max. s/g elements */
#define MAX_LDRIVES 255 /* max. log. drive count */
#ifdef GDTH_IOCTL_PROC
#define MAX_HDRIVES 100 /* max. host drive count */
#else
#define MAX_HDRIVES MAX_LDRIVES /* max. host drive count */
#endif
/* scatter/gather element */
typedef struct {
......@@ -178,91 +174,6 @@ typedef struct {
gdth_evt_data event_data;
} __attribute__((packed)) gdth_evt_str;
#ifdef GDTH_IOCTL_PROC
/* IOCTL structure (write) */
typedef struct {
u32 magic; /* IOCTL magic */
u16 ioctl; /* IOCTL */
u16 ionode; /* controller number */
u16 service; /* controller service */
u16 timeout; /* timeout */
union {
struct {
u8 command[512]; /* controller command */
u8 data[1]; /* add. data */
} general;
struct {
u8 lock; /* lock/unlock */
u8 drive_cnt; /* drive count */
u16 drives[MAX_HDRIVES];/* drives */
} lockdrv;
struct {
u8 lock; /* lock/unlock */
u8 channel; /* channel */
} lockchn;
struct {
int erase; /* erase event ? */
int handle;
u8 evt[EVENT_SIZE]; /* event structure */
} event;
struct {
u8 bus; /* SCSI bus */
u8 target; /* target ID */
u8 lun; /* LUN */
u8 cmd_len; /* command length */
u8 cmd[12]; /* SCSI command */
} scsi;
struct {
u16 hdr_no; /* host drive number */
u8 flag; /* old meth./add/remove */
} rescan;
} iu;
} gdth_iowr_str;
/* IOCTL structure (read) */
typedef struct {
u32 size; /* buffer size */
u32 status; /* IOCTL error code */
union {
struct {
u8 data[1]; /* data */
} general;
struct {
u16 version; /* driver version */
} drvers;
struct {
u8 type; /* controller type */
u16 info; /* slot etc. */
u16 oem_id; /* OEM ID */
u16 bios_ver; /* not used */
u16 access; /* not used */
u16 ext_type; /* extended type */
u16 device_id; /* device ID */
u16 sub_device_id; /* sub device ID */
} ctrtype;
struct {
u8 version; /* OS version */
u8 subversion; /* OS subversion */
u16 revision; /* revision */
} osvers;
struct {
u16 count; /* controller count */
} ctrcnt;
struct {
int handle;
u8 evt[EVENT_SIZE]; /* event structure */
} event;
struct {
u8 bus; /* SCSI bus, 0xff: invalid */
u8 target; /* target ID */
u8 lun; /* LUN */
u8 cluster_type; /* cluster properties */
} hdr_list[MAX_HDRIVES]; /* index is host drive number */
} iu;
} gdth_iord_str;
#endif
/* GDTIOCTL_GENERAL */
typedef struct {
u16 ionode; /* controller number */
......
......@@ -31,7 +31,6 @@ static int gdth_set_asc_info(struct Scsi_Host *host, char *buffer,
int i, found;
gdth_cmd_str gdtcmd;
gdth_cpar_str *pcpar;
u64 paddr;
char cmnd[MAX_COMMAND_SIZE];
memset(cmnd, 0xff, 12);
......@@ -113,13 +112,23 @@ static int gdth_set_asc_info(struct Scsi_Host *host, char *buffer,
}
if (wb_mode) {
if (!gdth_ioctl_alloc(ha, sizeof(gdth_cpar_str), TRUE, &paddr))
return(-EBUSY);
unsigned long flags;
BUILD_BUG_ON(sizeof(gdth_cpar_str) > GDTH_SCRATCH);
spin_lock_irqsave(&ha->smp_lock, flags);
if (ha->scratch_busy) {
spin_unlock_irqrestore(&ha->smp_lock, flags);
return -EBUSY;
}
ha->scratch_busy = TRUE;
spin_unlock_irqrestore(&ha->smp_lock, flags);
pcpar = (gdth_cpar_str *)ha->pscratch;
memcpy( pcpar, &ha->cpar, sizeof(gdth_cpar_str) );
gdtcmd.Service = CACHESERVICE;
gdtcmd.OpCode = GDT_IOCTL;
gdtcmd.u.ioctl.p_param = paddr;
gdtcmd.u.ioctl.p_param = ha->scratch_phys;
gdtcmd.u.ioctl.param_size = sizeof(gdth_cpar_str);
gdtcmd.u.ioctl.subfunc = CACHE_CONFIG;
gdtcmd.u.ioctl.channel = INVALID_CHANNEL;
......@@ -127,7 +136,10 @@ static int gdth_set_asc_info(struct Scsi_Host *host, char *buffer,
gdth_execute(host, &gdtcmd, cmnd, 30, NULL);
gdth_ioctl_free(ha, GDTH_SCRATCH, ha->pscratch, paddr);
spin_lock_irqsave(&ha->smp_lock, flags);
ha->scratch_busy = FALSE;
spin_unlock_irqrestore(&ha->smp_lock, flags);
printk("Done.\n");
return(orig_length);
}
......@@ -143,7 +155,7 @@ int gdth_show_info(struct seq_file *m, struct Scsi_Host *host)
int id, i, j, k, sec, flag;
int no_mdrv = 0, drv_no, is_mirr;
u32 cnt;
u64 paddr;
dma_addr_t paddr;
int rc = -ENOMEM;
gdth_cmd_str *gdtcmd;
......@@ -217,20 +229,14 @@ int gdth_show_info(struct seq_file *m, struct Scsi_Host *host)
" Serial No.: \t0x%8X\tCache RAM size:\t%d KB\n",
ha->binfo.ser_no, ha->binfo.memsize / 1024);
#ifdef GDTH_DMA_STATISTICS
/* controller statistics */
seq_puts(m, "\nController Statistics:\n");
seq_printf(m,
" 32-bit DMA buffer:\t%lu\t64-bit DMA buffer:\t%lu\n",
ha->dma32_cnt, ha->dma64_cnt);
#endif
if (ha->more_proc) {
size_t size = max_t(size_t, GDTH_SCRATCH, sizeof(gdth_hget_str));
/* more information: 2. about physical devices */
seq_puts(m, "\nPhysical Devices:");
flag = FALSE;
buf = gdth_ioctl_alloc(ha, GDTH_SCRATCH, FALSE, &paddr);
buf = dma_alloc_coherent(&ha->pdev->dev, size, &paddr, GFP_KERNEL);
if (!buf)
goto stop_output;
for (i = 0; i < ha->bus_cnt; ++i) {
......@@ -323,7 +329,6 @@ int gdth_show_info(struct seq_file *m, struct Scsi_Host *host)
}
}
}
gdth_ioctl_free(ha, GDTH_SCRATCH, buf, paddr);
if (!flag)
seq_puts(m, "\n --\n");
......@@ -332,9 +337,6 @@ int gdth_show_info(struct seq_file *m, struct Scsi_Host *host)
seq_puts(m, "\nLogical Drives:");
flag = FALSE;
buf = gdth_ioctl_alloc(ha, GDTH_SCRATCH, FALSE, &paddr);
if (!buf)
goto stop_output;
for (i = 0; i < MAX_LDRIVES; ++i) {
if (!ha->hdr[i].is_logdrv)
continue;
......@@ -408,8 +410,7 @@ int gdth_show_info(struct seq_file *m, struct Scsi_Host *host)
seq_printf(m,
" To Array Drv.:\t%s\n", hrec);
}
gdth_ioctl_free(ha, GDTH_SCRATCH, buf, paddr);
if (!flag)
seq_puts(m, "\n --\n");
......@@ -417,9 +418,6 @@ int gdth_show_info(struct seq_file *m, struct Scsi_Host *host)
seq_puts(m, "\nArray Drives:");
flag = FALSE;
buf = gdth_ioctl_alloc(ha, GDTH_SCRATCH, FALSE, &paddr);
if (!buf)
goto stop_output;
for (i = 0; i < MAX_LDRIVES; ++i) {
if (!(ha->hdr[i].is_arraydrv && ha->hdr[i].is_master))
continue;
......@@ -468,8 +466,7 @@ int gdth_show_info(struct seq_file *m, struct Scsi_Host *host)
hrec);
}
}
gdth_ioctl_free(ha, GDTH_SCRATCH, buf, paddr);
if (!flag)
seq_puts(m, "\n --\n");
......@@ -477,9 +474,6 @@ int gdth_show_info(struct seq_file *m, struct Scsi_Host *host)
seq_puts(m, "\nHost Drives:");
flag = FALSE;
buf = gdth_ioctl_alloc(ha, sizeof(gdth_hget_str), FALSE, &paddr);
if (!buf)
goto stop_output;
for (i = 0; i < MAX_LDRIVES; ++i) {
if (!ha->hdr[i].is_logdrv ||
(ha->hdr[i].is_arraydrv && !ha->hdr[i].is_master))
......@@ -510,7 +504,7 @@ int gdth_show_info(struct seq_file *m, struct Scsi_Host *host)
}
}
}
gdth_ioctl_free(ha, sizeof(gdth_hget_str), buf, paddr);
dma_free_coherent(&ha->pdev->dev, size, buf, paddr);
for (i = 0; i < MAX_HDRIVES; ++i) {
if (!(ha->hdr[i].present))
......@@ -563,65 +557,6 @@ int gdth_show_info(struct seq_file *m, struct Scsi_Host *host)
return rc;
}
static char *gdth_ioctl_alloc(gdth_ha_str *ha, int size, int scratch,
u64 *paddr)
{
unsigned long flags;
char *ret_val;
if (size == 0)
return NULL;
spin_lock_irqsave(&ha->smp_lock, flags);
if (!ha->scratch_busy && size <= GDTH_SCRATCH) {
ha->scratch_busy = TRUE;
ret_val = ha->pscratch;
*paddr = ha->scratch_phys;
} else if (scratch) {
ret_val = NULL;
} else {
dma_addr_t dma_addr;
ret_val = pci_alloc_consistent(ha->pdev, size, &dma_addr);
*paddr = dma_addr;
}
spin_unlock_irqrestore(&ha->smp_lock, flags);
return ret_val;
}
static void gdth_ioctl_free(gdth_ha_str *ha, int size, char *buf, u64 paddr)
{
unsigned long flags;
if (buf == ha->pscratch) {
spin_lock_irqsave(&ha->smp_lock, flags);
ha->scratch_busy = FALSE;
spin_unlock_irqrestore(&ha->smp_lock, flags);
} else {
pci_free_consistent(ha->pdev, size, buf, paddr);
}
}
#ifdef GDTH_IOCTL_PROC
static int gdth_ioctl_check_bin(gdth_ha_str *ha, u16 size)
{
unsigned long flags;
int ret_val;
spin_lock_irqsave(&ha->smp_lock, flags);
ret_val = FALSE;
if (ha->scratch_busy) {
if (((gdth_iord_str *)ha->pscratch)->size == (u32)size)
ret_val = TRUE;
}
spin_unlock_irqrestore(&ha->smp_lock, flags);
return ret_val;
}
#endif
static void gdth_wait_completion(gdth_ha_str *ha, int busnum, int id)
{
unsigned long flags;
......
......@@ -12,9 +12,6 @@ int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
static int gdth_set_asc_info(struct Scsi_Host *host, char *buffer,
int length, gdth_ha_str *ha);
static char *gdth_ioctl_alloc(gdth_ha_str *ha, int size, int scratch,
u64 *paddr);
static void gdth_ioctl_free(gdth_ha_str *ha, int size, char *buf, u64 paddr);
static void gdth_wait_completion(gdth_ha_str *ha, int busnum, int id);
#endif
......
......@@ -14,6 +14,7 @@
#include <linux/acpi.h>
#include <linux/clk.h>
#include <linux/debugfs.h>
#include <linux/dmapool.h>
#include <linux/iopoll.h>
#include <linux/lcm.h>
......@@ -220,6 +221,24 @@ struct hisi_sas_slot {
u16 idx;
};
#define HISI_SAS_DEBUGFS_REG(x) {#x, x}
struct hisi_sas_debugfs_reg_lu {
char *name;
int off;
};
struct hisi_sas_debugfs_reg {
const struct hisi_sas_debugfs_reg_lu *lu;
int count;
int base_off;
union {
u32 (*read_global_reg)(struct hisi_hba *hisi_hba, u32 off);
u32 (*read_port_reg)(struct hisi_hba *hisi_hba, int port,
u32 off);
};
};
struct hisi_sas_hw {
int (*hw_init)(struct hisi_hba *hisi_hba);
void (*setup_itct)(struct hisi_hba *hisi_hba,
......@@ -259,11 +278,16 @@ struct hisi_sas_hw {
u32 (*get_phys_state)(struct hisi_hba *hisi_hba);
int (*write_gpio)(struct hisi_hba *hisi_hba, u8 reg_type,
u8 reg_index, u8 reg_count, u8 *write_data);
void (*wait_cmds_complete_timeout)(struct hisi_hba *hisi_hba,
int delay_ms, int timeout_ms);
int (*wait_cmds_complete_timeout)(struct hisi_hba *hisi_hba,
int delay_ms, int timeout_ms);
void (*snapshot_prepare)(struct hisi_hba *hisi_hba);
void (*snapshot_restore)(struct hisi_hba *hisi_hba);
int max_command_entries;
int complete_hdr_size;
struct scsi_host_template *sht;
const struct hisi_sas_debugfs_reg *debugfs_reg_global;
const struct hisi_sas_debugfs_reg *debugfs_reg_port;
};
struct hisi_hba {
......@@ -329,9 +353,21 @@ struct hisi_hba {
const struct hisi_sas_hw *hw; /* Low level hw interface */
unsigned long sata_dev_bitmap[BITS_TO_LONGS(HISI_SAS_MAX_DEVICES)];
struct work_struct rst_work;
struct work_struct debugfs_work;
u32 phy_state;
u32 intr_coal_ticks; /* Time of interrupt coalesce in us */
u32 intr_coal_count; /* Interrupt count to coalesce */
/* debugfs memories */
void *debugfs_global_reg;
void *debugfs_port_reg[HISI_SAS_MAX_PHYS];
void *debugfs_complete_hdr[HISI_SAS_MAX_QUEUES];
struct hisi_sas_cmd_hdr *debugfs_cmd_hdr[HISI_SAS_MAX_QUEUES];
struct hisi_sas_iost *debugfs_iost;
struct hisi_sas_itct *debugfs_itct;
struct dentry *debugfs_dir;
struct dentry *debugfs_dump_dentry;
};
/* Generic HW DMA host memory structures */
......@@ -461,6 +497,10 @@ struct hisi_sas_slot_buf_table {
};
extern struct scsi_transport_template *hisi_sas_stt;
extern bool hisi_sas_debugfs_enable;
extern struct dentry *hisi_sas_debugfs_dir;
extern void hisi_sas_stop_phys(struct hisi_hba *hisi_hba);
extern int hisi_sas_alloc(struct hisi_hba *hisi_hba, struct Scsi_Host *shost);
extern void hisi_sas_free(struct hisi_hba *hisi_hba);
......@@ -493,4 +533,7 @@ extern void hisi_sas_release_tasks(struct hisi_hba *hisi_hba);
extern u8 hisi_sas_get_prog_phy_linkrate_mask(enum sas_linkrate max);
extern void hisi_sas_controller_reset_prepare(struct hisi_hba *hisi_hba);
extern void hisi_sas_controller_reset_done(struct hisi_hba *hisi_hba);
extern void hisi_sas_debugfs_init(struct hisi_hba *hisi_hba);
extern void hisi_sas_debugfs_exit(struct hisi_hba *hisi_hba);
extern void hisi_sas_debugfs_work_handler(struct work_struct *work);
#endif
This diff is collapsed.
......@@ -3542,8 +3542,8 @@ static int write_gpio_v2_hw(struct hisi_hba *hisi_hba, u8 reg_type,
return 0;
}
static void wait_cmds_complete_timeout_v2_hw(struct hisi_hba *hisi_hba,
int delay_ms, int timeout_ms)
static int wait_cmds_complete_timeout_v2_hw(struct hisi_hba *hisi_hba,
int delay_ms, int timeout_ms)
{
struct device *dev = hisi_hba->dev;
int entries, entries_old = 0, time;
......@@ -3557,7 +3557,12 @@ static void wait_cmds_complete_timeout_v2_hw(struct hisi_hba *hisi_hba,
msleep(delay_ms);
}
if (time >= timeout_ms)
return -ETIMEDOUT;
dev_dbg(dev, "wait commands complete %dms\n", time);
return 0;
}
static struct device_attribute *host_attrs_v2_hw[] = {
......
......@@ -186,6 +186,7 @@
#define CHL_INT0_MSK (PORT_BASE + 0x1c0)
#define CHL_INT1_MSK (PORT_BASE + 0x1c4)
#define CHL_INT2_MSK (PORT_BASE + 0x1c8)
#define SAS_EC_INT_COAL_TIME (PORT_BASE + 0x1cc)
#define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
#define SAS_RX_TRAIN_TIMER (PORT_BASE + 0x2a4)
#define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
......@@ -205,6 +206,7 @@
#define ERR_CNT_DWS_LOST (PORT_BASE + 0x380)
#define ERR_CNT_RESET_PROB (PORT_BASE + 0x384)
#define ERR_CNT_INVLD_DW (PORT_BASE + 0x390)
#define ERR_CNT_CODE_ERR (PORT_BASE + 0x394)
#define ERR_CNT_DISP_ERR (PORT_BASE + 0x398)
#define DEFAULT_ITCT_HW 2048 /* reset value, not reprogrammed */
......@@ -2201,8 +2203,8 @@ static int write_gpio_v3_hw(struct hisi_hba *hisi_hba, u8 reg_type,
return 0;
}
static void wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba,
int delay_ms, int timeout_ms)
static int wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba,
int delay_ms, int timeout_ms)
{
struct device *dev = hisi_hba->dev;
int entries, entries_old = 0, time;
......@@ -2216,7 +2218,12 @@ static void wait_cmds_complete_timeout_v3_hw(struct hisi_hba *hisi_hba,
msleep(delay_ms);
}
if (time >= timeout_ms)
return -ETIMEDOUT;
dev_dbg(dev, "wait commands complete %dms\n", time);
return 0;
}
static ssize_t intr_conv_v3_hw_show(struct device *dev,
......@@ -2332,6 +2339,159 @@ static struct device_attribute *host_attrs_v3_hw[] = {
NULL
};
static const struct hisi_sas_debugfs_reg_lu debugfs_port_reg_lu[] = {
HISI_SAS_DEBUGFS_REG(PHY_CFG),
HISI_SAS_DEBUGFS_REG(HARD_PHY_LINKRATE),
HISI_SAS_DEBUGFS_REG(PROG_PHY_LINK_RATE),
HISI_SAS_DEBUGFS_REG(PHY_CTRL),
HISI_SAS_DEBUGFS_REG(SL_CFG),
HISI_SAS_DEBUGFS_REG(AIP_LIMIT),
HISI_SAS_DEBUGFS_REG(SL_CONTROL),
HISI_SAS_DEBUGFS_REG(RX_PRIMS_STATUS),
HISI_SAS_DEBUGFS_REG(TX_ID_DWORD0),
HISI_SAS_DEBUGFS_REG(TX_ID_DWORD1),
HISI_SAS_DEBUGFS_REG(TX_ID_DWORD2),
HISI_SAS_DEBUGFS_REG(TX_ID_DWORD3),
HISI_SAS_DEBUGFS_REG(TX_ID_DWORD4),
HISI_SAS_DEBUGFS_REG(TX_ID_DWORD5),
HISI_SAS_DEBUGFS_REG(TX_ID_DWORD6),
HISI_SAS_DEBUGFS_REG(TXID_AUTO),
HISI_SAS_DEBUGFS_REG(RX_IDAF_DWORD0),
HISI_SAS_DEBUGFS_REG(RXOP_CHECK_CFG_H),
HISI_SAS_DEBUGFS_REG(STP_LINK_TIMER),
HISI_SAS_DEBUGFS_REG(STP_LINK_TIMEOUT_STATE),
HISI_SAS_DEBUGFS_REG(CON_CFG_DRIVER),
HISI_SAS_DEBUGFS_REG(SAS_SSP_CON_TIMER_CFG),
HISI_SAS_DEBUGFS_REG(SAS_SMP_CON_TIMER_CFG),
HISI_SAS_DEBUGFS_REG(SAS_STP_CON_TIMER_CFG),
HISI_SAS_DEBUGFS_REG(CHL_INT0),
HISI_SAS_DEBUGFS_REG(CHL_INT1),
HISI_SAS_DEBUGFS_REG(CHL_INT2),
HISI_SAS_DEBUGFS_REG(CHL_INT0_MSK),
HISI_SAS_DEBUGFS_REG(CHL_INT1_MSK),
HISI_SAS_DEBUGFS_REG(CHL_INT2_MSK),
HISI_SAS_DEBUGFS_REG(SAS_EC_INT_COAL_TIME),
HISI_SAS_DEBUGFS_REG(CHL_INT_COAL_EN),
HISI_SAS_DEBUGFS_REG(SAS_RX_TRAIN_TIMER),
HISI_SAS_DEBUGFS_REG(PHY_CTRL_RDY_MSK),
HISI_SAS_DEBUGFS_REG(PHYCTRL_NOT_RDY_MSK),
HISI_SAS_DEBUGFS_REG(PHYCTRL_DWS_RESET_MSK),
HISI_SAS_DEBUGFS_REG(PHYCTRL_PHY_ENA_MSK),
HISI_SAS_DEBUGFS_REG(SL_RX_BCAST_CHK_MSK),
HISI_SAS_DEBUGFS_REG(PHYCTRL_OOB_RESTART_MSK),
HISI_SAS_DEBUGFS_REG(DMA_TX_STATUS),
HISI_SAS_DEBUGFS_REG(DMA_RX_STATUS),
HISI_SAS_DEBUGFS_REG(COARSETUNE_TIME),
HISI_SAS_DEBUGFS_REG(ERR_CNT_DWS_LOST),
HISI_SAS_DEBUGFS_REG(ERR_CNT_RESET_PROB),
HISI_SAS_DEBUGFS_REG(ERR_CNT_INVLD_DW),
HISI_SAS_DEBUGFS_REG(ERR_CNT_CODE_ERR),
HISI_SAS_DEBUGFS_REG(ERR_CNT_DISP_ERR),
{}
};
static const struct hisi_sas_debugfs_reg debugfs_port_reg = {
.lu = debugfs_port_reg_lu,
.count = 0x100,
.base_off = PORT_BASE,
.read_port_reg = hisi_sas_phy_read32,
};
static const struct hisi_sas_debugfs_reg_lu debugfs_global_reg_lu[] = {
HISI_SAS_DEBUGFS_REG(DLVRY_QUEUE_ENABLE),
HISI_SAS_DEBUGFS_REG(PHY_CONTEXT),
HISI_SAS_DEBUGFS_REG(PHY_STATE),
HISI_SAS_DEBUGFS_REG(PHY_PORT_NUM_MA),
HISI_SAS_DEBUGFS_REG(PHY_CONN_RATE),
HISI_SAS_DEBUGFS_REG(ITCT_CLR),
HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_LO),
HISI_SAS_DEBUGFS_REG(IO_SATA_BROKEN_MSG_ADDR_HI),
HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_LO),
HISI_SAS_DEBUGFS_REG(SATA_INITI_D2H_STORE_ADDR_HI),
HISI_SAS_DEBUGFS_REG(CFG_MAX_TAG),
HISI_SAS_DEBUGFS_REG(HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL),
HISI_SAS_DEBUGFS_REG(HGC_SAS_TXFAIL_RETRY_CTRL),
HISI_SAS_DEBUGFS_REG(HGC_GET_ITV_TIME),
HISI_SAS_DEBUGFS_REG(DEVICE_MSG_WORK_MODE),
HISI_SAS_DEBUGFS_REG(OPENA_WT_CONTI_TIME),
HISI_SAS_DEBUGFS_REG(I_T_NEXUS_LOSS_TIME),
HISI_SAS_DEBUGFS_REG(MAX_CON_TIME_LIMIT_TIME),
HISI_SAS_DEBUGFS_REG(BUS_INACTIVE_LIMIT_TIME),
HISI_SAS_DEBUGFS_REG(REJECT_TO_OPEN_LIMIT_TIME),
HISI_SAS_DEBUGFS_REG(CQ_INT_CONVERGE_EN),
HISI_SAS_DEBUGFS_REG(CFG_AGING_TIME),
HISI_SAS_DEBUGFS_REG(HGC_DFX_CFG2),
HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_QUERY_IPTT),
HISI_SAS_DEBUGFS_REG(CFG_ABT_SET_IPTT_DONE),
HISI_SAS_DEBUGFS_REG(HGC_IOMB_PROC1_STATUS),
HISI_SAS_DEBUGFS_REG(CHNL_INT_STATUS),
HISI_SAS_DEBUGFS_REG(HGC_AXI_FIFO_ERR_INFO),
HISI_SAS_DEBUGFS_REG(INT_COAL_EN),
HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_TIME),
HISI_SAS_DEBUGFS_REG(OQ_INT_COAL_CNT),
HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_TIME),
HISI_SAS_DEBUGFS_REG(ENT_INT_COAL_CNT),
HISI_SAS_DEBUGFS_REG(OQ_INT_SRC),
HISI_SAS_DEBUGFS_REG(OQ_INT_SRC_MSK),
HISI_SAS_DEBUGFS_REG(ENT_INT_SRC1),
HISI_SAS_DEBUGFS_REG(ENT_INT_SRC2),
HISI_SAS_DEBUGFS_REG(ENT_INT_SRC3),
HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK1),
HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK2),
HISI_SAS_DEBUGFS_REG(ENT_INT_SRC_MSK3),
HISI_SAS_DEBUGFS_REG(CHNL_PHYUPDOWN_INT_MSK),
HISI_SAS_DEBUGFS_REG(CHNL_ENT_INT_MSK),
HISI_SAS_DEBUGFS_REG(HGC_COM_INT_MSK),
HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR),
HISI_SAS_DEBUGFS_REG(SAS_ECC_INTR_MSK),
HISI_SAS_DEBUGFS_REG(HGC_ERR_STAT_EN),
HISI_SAS_DEBUGFS_REG(CQE_SEND_CNT),
HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_DEPTH),
HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_WR_PTR),
HISI_SAS_DEBUGFS_REG(DLVRY_Q_0_RD_PTR),
HISI_SAS_DEBUGFS_REG(HYPER_STREAM_ID_EN_CFG),
HISI_SAS_DEBUGFS_REG(OQ0_INT_SRC_MSK),