Add the RS9116 driver parts

parent 69f00cd0
Pipeline #5245 passed with stage
in 16 minutes and 15 seconds
......@@ -53,4 +53,12 @@ config RSI_COEX
Select M (recommended), if you have want to use this feature
and you have RS9113 module.
config RSI_PURISM
bool "Redpine Signals PURISM FW support"
depends on RSI_91X && RSI_COEX
default n
---help---
This option enables the PURISM FW support.
Say Y if you want to use this feature.
endif # WLAN_VENDOR_RSI
This diff is collapsed.
......@@ -465,6 +465,8 @@ static int rsi_mac80211_add_interface(struct ieee80211_hw *hw,
enum vap_status vap_status;
int vap_idx = -1, i;
rsi_dbg(INFO_ZONE, "Add Interface Called\n");
vif->driver_flags |= IEEE80211_VIF_SUPPORTS_UAPSD;
mutex_lock(&common->mutex);
......@@ -506,6 +508,10 @@ static int rsi_mac80211_add_interface(struct ieee80211_hw *hw,
return -EINVAL;
}
memset(vif_info->rx_bcmc_pn, 0, IEEE80211_CCMP_PN_LEN);
vif_info->rx_pn_valid = false;
vif_info->key = NULL;
if ((vif->type == NL80211_IFTYPE_AP) ||
(vif->type == NL80211_IFTYPE_P2P_GO)) {
rsi_send_rx_filter_frame(common, DISALLOW_BEACONS);
......
......@@ -24,14 +24,14 @@
#include "rsi_coex.h"
#include "rsi_hal.h"
u32 rsi_zone_enabled = /* INFO_ZONE |
u32 rsi_zone_enabled = INFO_ZONE |
INIT_ZONE |
MGMT_TX_ZONE |
MGMT_RX_ZONE |
DATA_TX_ZONE |
DATA_RX_ZONE |
//MGMT_TX_ZONE |
//MGMT_RX_ZONE |
//DATA_TX_ZONE |
//DATA_RX_ZONE |
FSM_ZONE |
ISR_ZONE | */
//ISR_ZONE |
ERR_ZONE |
0;
EXPORT_SYMBOL_GPL(rsi_zone_enabled);
......@@ -67,6 +67,31 @@ void rsi_dbg(u32 zone, const char *fmt, ...)
}
EXPORT_SYMBOL_GPL(rsi_dbg);
/**
* rsi_hex_dump() - This function prints the packet (/msg) in hex bytes.
* @zone: Zone of interest for output message.
* @msg_str: Message to be printed with packet
* @msg: Packet to be printed
* @len: Length of the packet
*
* Return: none
*/
void rsi_hex_dump(u32 zone, char *msg_str, const u8 *msg, u32 len)
{
int ii;
if (!(zone & rsi_zone_enabled))
return;
printk("%s: (length = %d)\n", msg_str, len);
for (ii = 0; ii < len; ii++) {
if (ii && !(ii % 16))
printk(KERN_CONT "\n");
printk(KERN_CONT "%02x ", msg[ii]);
}
printk(KERN_CONT "\n");
}
EXPORT_SYMBOL_GPL(rsi_hex_dump);
static char *opmode_str(int oper_mode)
{
switch (oper_mode) {
......@@ -353,6 +378,9 @@ struct rsi_hw *rsi_91x_init(u16 oper_mode)
rsi_dbg(INFO_ZONE, "%s: oper_mode = %d, coex_mode = %d\n",
__func__, common->oper_mode, common->coex_mode);
common->obm_ant_sel_val = ANTENNA_SEL_UFL;
common->antenna_diversity = 1;
adapter->device_model = RSI_DEV_9113;
#ifdef CONFIG_RSI_COEX
if (common->coex_mode > 1) {
......@@ -439,7 +467,7 @@ static void rsi_91x_hal_module_exit(void)
module_init(rsi_91x_hal_module_init);
module_exit(rsi_91x_hal_module_exit);
MODULE_AUTHOR("Redpine Signals Inc");
MODULE_DESCRIPTION("Station driver for RSI 91x devices");
MODULE_DESCRIPTION("Station driver for RSI 91x devices + Purism FW");
MODULE_SUPPORTED_DEVICE("RSI-91x");
MODULE_VERSION("0.1");
MODULE_LICENSE("Dual BSD/GPL");
This diff is collapsed.
......@@ -949,7 +949,7 @@ static int rsi_probe(struct sdio_func *pfunction,
{
struct rsi_hw *adapter;
struct rsi_91x_sdiodev *sdev;
int status;
int status = 0;
rsi_dbg(INIT_ZONE, "%s: Init function called\n", __func__);
......@@ -968,6 +968,22 @@ static int rsi_probe(struct sdio_func *pfunction,
status = -EIO;
goto fail_free_adapter;
}
rsi_dbg(INFO_ZONE, "Vendor Id:%x, Device Id:%x\n",
pfunction->vendor, pfunction->device);
if ((pfunction->device == 0X9330)) {
rsi_dbg(ERR_ZONE, "%s: ***** 9113 Module *****\n", __func__);
adapter->device_model = RSI_DEV_9113;
} else if ((pfunction->device == 0X9116)) {
rsi_dbg(ERR_ZONE, "%s: ***** 9116 Module *****\n", __func__);
adapter->device_model = RSI_DEV_9116;
} else {
rsi_dbg(ERR_ZONE,
"##### Invalid RSI device id 0x%x\n",
pfunction->device);
goto fail_free_adapter;
}
sdev = (struct rsi_91x_sdiodev *)adapter->rsi_dev;
rsi_init_event(&sdev->rx_thread.event);
status = rsi_create_kthread(adapter->priv, &sdev->rx_thread,
......@@ -1088,16 +1104,36 @@ static void rsi_reset_chip(struct rsi_hw *adapter)
* and any pending dma transfers to rf spi in device to finish.
*/
msleep(100);
ulp_read_write(adapter, RSI_ULP_RESET_REG, RSI_ULP_WRITE_0, 32);
ulp_read_write(adapter, RSI_WATCH_DOG_TIMER_1, RSI_ULP_WRITE_2, 32);
ulp_read_write(adapter, RSI_WATCH_DOG_TIMER_2, RSI_ULP_WRITE_0, 32);
ulp_read_write(adapter, RSI_WATCH_DOG_DELAY_TIMER_1, RSI_ULP_WRITE_50,
32);
ulp_read_write(adapter, RSI_WATCH_DOG_DELAY_TIMER_2, RSI_ULP_WRITE_0,
32);
ulp_read_write(adapter, RSI_WATCH_DOG_TIMER_ENABLE,
RSI_ULP_TIMER_ENABLE, 32);
if (adapter->device_model == RSI_DEV_9116) {
if ((rsi_sdio_master_reg_write(adapter,
NWP_WWD_INTERRUPT_TIMER,
5, 4)) < 0) {
rsi_dbg(ERR_ZONE, "Failed to write to intr timer\n");
}
if ((rsi_sdio_master_reg_write(adapter,
NWP_WWD_SYSTEM_RESET_TIMER,
4, 4)) < 0) {
rsi_dbg(ERR_ZONE,
"Failed to write to system reset timer\n");
}
if ((rsi_sdio_master_reg_write(adapter,
NWP_WWD_MODE_AND_RSTART,
0xAA0001, 4)) < 0) {
rsi_dbg(ERR_ZONE,
"Failed to write to mode and restart\n");
}
rsi_dbg(ERR_ZONE, "***** Watch Dog Reset Successful *****\n");
} else {
ulp_read_write(adapter, RSI_ULP_RESET_REG, RSI_ULP_WRITE_0, 32);
ulp_read_write(adapter, RSI_WATCH_DOG_TIMER_1, RSI_ULP_WRITE_2, 32);
ulp_read_write(adapter, RSI_WATCH_DOG_TIMER_2, RSI_ULP_WRITE_0, 32);
ulp_read_write(adapter, RSI_WATCH_DOG_DELAY_TIMER_1, RSI_ULP_WRITE_50,
32);
ulp_read_write(adapter, RSI_WATCH_DOG_DELAY_TIMER_2, RSI_ULP_WRITE_0,
32);
ulp_read_write(adapter, RSI_WATCH_DOG_TIMER_ENABLE,
RSI_ULP_TIMER_ENABLE, 32);
}
/* This msleep will be sufficient for the ulp
* read write operations to complete for chip reset.
*/
......@@ -1415,7 +1451,8 @@ static const struct dev_pm_ops rsi_pm_ops = {
#endif
static const struct sdio_device_id rsi_dev_table[] = {
{ SDIO_DEVICE(RSI_SDIO_VID_9113, RSI_SDIO_PID_9113) },
{ SDIO_DEVICE(RSI_SDIO_VID, RSI_SDIO_PID_9113) },
{ SDIO_DEVICE(RSI_SDIO_VID, RSI_SDIO_PID_9116) },
{ /* Blank */},
};
......
......@@ -51,9 +51,15 @@ static int rsi_usb_card_write(struct rsi_hw *adapter,
int transfer;
int ep = dev->bulkout_endpoint_addr[endpoint - 1];
memset(seg, 0, len + RSI_USB_TX_HEAD_ROOM);
memcpy(seg + RSI_USB_TX_HEAD_ROOM, buf, len);
len += RSI_USB_TX_HEAD_ROOM;
if (adapter->priv->zb_fsm_state == ZB_DEVICE_READY &&
(adapter->device_model == RSI_DEV_9116 ?
endpoint == ZIGB_EP : endpoint == BT_EP)) {
memcpy(seg, buf, len);
} else {
memset(seg, 0, len + RSI_USB_TX_HEAD_ROOM);
memcpy(seg + RSI_USB_TX_HEAD_ROOM, buf, len);
len += RSI_USB_TX_HEAD_ROOM;
}
transfer = len;
status = usb_bulk_msg(dev->usbdev,
usb_sndbulkpipe(dev->usbdev, ep),
......@@ -439,8 +445,14 @@ static int rsi_usb_host_intf_write_pkt(struct rsi_hw *adapter,
u32 queueno = ((pkt[1] >> 4) & 0x7);
u8 endpoint;
endpoint = ((queueno == RSI_WIFI_MGMT_Q || queueno == RSI_WIFI_DATA_Q ||
queueno == RSI_COEX_Q) ? WLAN_EP : BT_EP);
if (adapter->device_model == RSI_DEV_9116 && queueno == RSI_ZIGB_Q) {
endpoint = ZIGB_EP;
} else {
endpoint = ((queueno == RSI_WIFI_MGMT_Q ||
queueno == RSI_COEX_Q ||
queueno == RSI_WIFI_DATA_Q) ?
WLAN_EP : BT_EP);
}
return rsi_write_multiple(adapter,
endpoint,
......@@ -690,35 +702,52 @@ static int rsi_reset_card(struct rsi_hw *adapter)
*/
msleep(100);
ret = rsi_usb_master_reg_write(adapter, SWBL_REGOUT,
RSI_FW_WDT_DISABLE_REQ,
RSI_COMMON_REG_SIZE);
if (ret < 0) {
rsi_dbg(ERR_ZONE, "Disabling firmware watchdog timer failed\n");
goto fail;
}
ret = usb_ulp_read_write(adapter, RSI_WATCH_DOG_TIMER_1,
RSI_ULP_WRITE_2, 32);
if (ret < 0)
goto fail;
ret = usb_ulp_read_write(adapter, RSI_WATCH_DOG_TIMER_2,
RSI_ULP_WRITE_0, 32);
if (ret < 0)
goto fail;
ret = usb_ulp_read_write(adapter, RSI_WATCH_DOG_DELAY_TIMER_1,
RSI_ULP_WRITE_50, 32);
if (ret < 0)
goto fail;
ret = usb_ulp_read_write(adapter, RSI_WATCH_DOG_DELAY_TIMER_2,
RSI_ULP_WRITE_0, 32);
if (ret < 0)
goto fail;
ret = usb_ulp_read_write(adapter, RSI_WATCH_DOG_TIMER_ENABLE,
RSI_ULP_TIMER_ENABLE, 32);
if (ret < 0)
goto fail;
if (adapter->device_model != RSI_DEV_9116) {
ret = rsi_usb_master_reg_write(adapter, SWBL_REGOUT,
RSI_FW_WDT_DISABLE_REQ,
RSI_COMMON_REG_SIZE);
if (ret < 0) {
rsi_dbg(ERR_ZONE, "Disabling firmware watchdog timer failed\n");
goto fail;
}
ret = usb_ulp_read_write(adapter, RSI_WATCH_DOG_TIMER_1,
RSI_ULP_WRITE_2, 32);
if (ret < 0)
goto fail;
ret = usb_ulp_read_write(adapter, RSI_WATCH_DOG_TIMER_2,
RSI_ULP_WRITE_0, 32);
if (ret < 0)
goto fail;
ret = usb_ulp_read_write(adapter, RSI_WATCH_DOG_DELAY_TIMER_1,
RSI_ULP_WRITE_50, 32);
if (ret < 0)
goto fail;
ret = usb_ulp_read_write(adapter, RSI_WATCH_DOG_DELAY_TIMER_2,
RSI_ULP_WRITE_0, 32);
if (ret < 0)
goto fail;
ret = usb_ulp_read_write(adapter, RSI_WATCH_DOG_TIMER_ENABLE,
RSI_ULP_TIMER_ENABLE, 32);
if (ret < 0)
goto fail;
} else {
if ((rsi_usb_master_reg_write(adapter,
NWP_WWD_INTERRUPT_TIMER,
5, 4)) < 0) {
goto fail;
}
if ((rsi_usb_master_reg_write(adapter,
NWP_WWD_SYSTEM_RESET_TIMER,
4, 4)) < 0) {
goto fail;
}
if ((rsi_usb_master_reg_write(adapter,
NWP_WWD_MODE_AND_RSTART,
0xAA0001, 4)) < 0) {
goto fail;
}
}
rsi_dbg(INFO_ZONE, "Reset card done\n");
return ret;
......@@ -763,6 +792,21 @@ static int rsi_probe(struct usb_interface *pfunction,
rsi_dbg(ERR_ZONE, "%s: Initialized os intf ops\n", __func__);
if (id && (id->idProduct == 0x9113)) {
rsi_dbg(INIT_ZONE, "%s: 9113 MODULE IS CONNECTED\n",
__func__);
adapter->device_model = RSI_DEV_9113;
} else if (id && (id->idProduct == 0x9116)) {
adapter->device_model = RSI_DEV_9116;
rsi_dbg(INIT_ZONE, "%s: 9116 MODULE IS CONNECTED\n",
__func__);
} else {
rsi_dbg(ERR_ZONE,
"##### Invalid RSI device id 0x%x\n",
id->idProduct);
goto err1;
}
dev = (struct rsi_91x_usbdev *)adapter->rsi_dev;
status = rsi_usb_reg_read(dev->usbdev, FW_STATUS_REG, &fw_status, 2);
......@@ -845,7 +889,8 @@ static int rsi_resume(struct usb_interface *intf)
#endif
static const struct usb_device_id rsi_dev_table[] = {
{ USB_DEVICE(RSI_USB_VID_9113, RSI_USB_PID_9113) },
{ USB_DEVICE(RSI_USB_VID, RSI_USB_PID_9113) },
{ USB_DEVICE(RSI_USB_VID, RSI_USB_PID_9116) },
{ /* Blank */},
};
......
......@@ -17,12 +17,38 @@
#ifndef __RSI_BOOTPARAMS_HEADER_H__
#define __RSI_BOOTPARAMS_HEADER_H__
#define LOADED_TOKEN 0x5AA5 /* Bootup params are installed by host
* or OTP/FLASH (Bootloader)
*/
#define ROM_TOKEN 0x55AA /* Bootup params are taken from ROM
* itself in MCU mode.
*/
#define CRYSTAL_GOOD_TIME BIT(0)
#define BOOTUP_MODE_INFO BIT(1)
#define WIFI_TAPLL_CONFIGS BIT(5)
#define WIFI_PLL960_CONFIGS BIT(6)
#define WIFI_AFEPLL_CONFIGS BIT(7)
#define WIFI_SWITCH_CLK_CONFIGS BIT(8)
#define BT_TAPLL_CONFIGS BIT(9)
#define BT_PLL960_CONFIGS BIT(10)
#define BT_AFEPLL_CONFIGS BIT(11)
#define BT_SWITCH_CLK_CONFIGS BIT(12)
#define ZB_TAPLL_CONFIGS BIT(13)
#define ZB_PLL960_CONFIGS BIT(14)
#define ZB_AFEPLL_CONFIGS BIT(15)
#define ZB_SWITCH_CLK_CONFIGS BIT(16)
#define BUCKBOOST_WAIT_INFO BIT(17)
#define PMU_WAKEUP_SHUTDOWN_W BIT(18)
#define WDT_PROG_VALUES BIT(19)
#define WDT_RESET_DELAY_VALUE BIT(20)
#define DCDC_OPERATION_MODE_VALID BIT(21)
#define PMU_SLP_CLKOUT_SEL BIT(22)
#define SOC_RESET_WAIT_CNT BIT(23)
#define BT_COEXIST BIT(0)
#define BOOTUP_MODE (BIT(2) | BIT(1))
#define CUR_DEV_MODE_9116 (bootup_params_9116.bootup_mode_info >> 1)
#define TA_PLL_M_VAL_20 9
#define TA_PLL_N_VAL_20 0
......@@ -55,6 +81,14 @@
(WIFI_PLL960_CONFIGS | WIFI_AFEPLL_CONFIGS | WIFI_SWITCH_CLK_CONFIGS | \
WIFI_TAPLL_CONFIGS | CRYSTAL_GOOD_TIME | BOOTUP_MODE_INFO)
#define RSI_SWITCH_TASS_CLK BIT(0)
#define RSI_SWITCH_QSPI_CLK BIT(1)
#define RSI_SWITCH_SLP_CLK_2_32 BIT(2)
#define RSI_SWITCH_WLAN_BBP_LMAC_CLK_REG BIT(3)
#define RSI_SWITCH_ZBBT_BBP_LMAC_CLK_REG BIT(4)
#define RSI_SWITCH_BBP_LMAC_CLK_REG BIT(5)
#define RSI_MODEM_CLK_160MHZ BIT(6)
/* structure to store configs related to TAPLL programming */
struct tapll_info {
__le16 pll_reg_1;
......@@ -80,6 +114,16 @@ struct pll_config {
struct afepll_info afepll_info_g;
} __packed;
/* PLL configurations for RS9116 */
struct pll_config_9116 {
__le16 pll_ctrl_set_reg;
__le16 pll_ctrl_clr_reg;
__le16 pll_modem_conig_reg;
__le16 soc_clk_config_reg;
__le16 adc_dac_strm1_config_reg;
__le16 adc_dac_strm2_config_reg;
} __packed;
/* structure to store configs related to UMAC clk programming */
struct switch_clk {
__le16 switch_clk_info;
......@@ -93,11 +137,26 @@ struct switch_clk {
__le16 qspi_uart_clock_reg_config;
} __packed;
/* UMAC clk programming configurations for RS9116 */
struct switch_clk_9116 {
__le32 switch_clk_info;
__le32 tass_clock_reg;
__le32 wlan_bbp_lmac_clk_reg_val;
__le32 zbbt_bbp_lmac_clk_reg_val;
__le32 bbp_lmac_clk_en_val;
} __packed;
struct device_clk_info {
struct pll_config pll_config_g;
struct switch_clk switch_clk_g;
} __packed;
/* device clock info configurations for RS9116 */
struct device_clk_info_9116 {
struct pll_config_9116 pll_config_9116_g;
struct switch_clk_9116 switch_clk_9116_g;
} __packed;
struct bootup_params {
__le16 magic_number;
__le16 crystal_good_time;
......@@ -127,4 +186,34 @@ struct bootup_params {
__le32 max_threshold_to_avoid_sleep;
u8 beacon_resedue_alg_en;
} __packed;
/* bootup params for RS9116 */
struct bootup_params_9116 {
__le16 magic_number;
__le16 crystal_good_time;
__le32 valid;
__le32 reserved_for_valids;
__le16 bootup_mode_info;
__le16 digital_loop_back_params;
__le16 rtls_timestamp_en;
__le16 host_spi_intr_cfg;
struct device_clk_info_9116 device_clk_info_9116[1];
/* ulp buckboost wait time */
__le32 buckboost_wakeup_cnt;
/* pmu wakeup wait time & WDT EN info */
__le16 pmu_wakeup_wait;
u8 shutdown_wait_time;
/* Sleep clock source selection */
u8 pmu_slp_clkout_sel;
/* WDT programming values */
__le32 wdt_prog_value;
/* WDT soc reset delay */
__le32 wdt_soc_rst_delay;
/* dcdc modes configs */
__le32 dcdc_operation_mode;
__le32 soc_reset_wait_cnt;
__le32 waiting_time_at_fresh_sleep;
__le32 max_threshold_to_avoid_sleep;
u8 beacon_resedue_alg_en;
} __packed;
#endif
......@@ -39,6 +39,11 @@
#define PING_WRITE 0x1
#define PONG_WRITE 0x2
#ifdef CONFIG_RSI_PURISM
#define RSI_FLASH_READ_COEX_IMAGE (0x04000000 + 0x80000 + 0x40)
#define RSI_FLASH_READ_WLAN_IMAGE (0x04000000 + 0x20000 + 0x40)
#endif
#define BL_CMD_TIMEOUT 2000
#define BL_BURN_TIMEOUT (50 * 1000)
......@@ -63,6 +68,12 @@
#define FW_LOADING_SUCCESSFUL 'S'
#define LOADING_INITIATED '1'
/* Total RAM access commands from TA */
#define MEM_ACCESS_CTRL_FROM_HOST 0x41300000
#define RAM_384K_ACCESS_FROM_TA (BIT(2) | BIT(3) | BIT(4) | BIT(5) \
| BIT(20) | BIT(21) | BIT(22) | BIT(23) \
| BIT(24) | BIT(25))
#define RSI_ULP_RESET_REG 0x161
#define RSI_WATCH_DOG_TIMER_1 0x16c
#define RSI_WATCH_DOG_TIMER_2 0x16d
......@@ -114,9 +125,19 @@
#define FW_FLASH_OFFSET 0x820
#define LMAC_VER_OFFSET (FW_FLASH_OFFSET + 0x200)
#define LMAC_VER_OFFSET_RS9116 0x22c2
#define MAX_DWORD_ALIGN_BYTES 64
#define RSI_COMMON_REG_SIZE 2
#define NWP_AHB_BASE_ADDR 0x41300000
#define NWP_WWD_INTERRUPT_TIMER (NWP_AHB_BASE_ADDR + 0x300)
#define NWP_WWD_SYSTEM_RESET_TIMER (NWP_AHB_BASE_ADDR + 0x304)
#define NWP_WWD_WINDOW_TIMER (NWP_AHB_BASE_ADDR + 0x308)
#define NWP_WWD_TIMER_SETTINGS (NWP_AHB_BASE_ADDR + 0x30C)
#define NWP_WWD_MODE_AND_RSTART (NWP_AHB_BASE_ADDR + 0x310)
#define NWP_WWD_RESET_BYPASS (NWP_AHB_BASE_ADDR + 0x314)
#define NWP_FSM_INTR_MASK_REG (NWP_AHB_BASE_ADDR + 0x104)
struct bl_header {
__le32 flags;
__le32 image_no;
......@@ -167,6 +188,25 @@ struct rsi_bt_desc {
__le16 bt_pkt_type;
} __packed;
#define RSI_BL_CTRL_LEN_MASK 0xFFFFFF
#define RSI_BL_CTRL_SPI_32BIT_MODE BIT(27)
#define RSI_BL_CTRL_REL_TA_SOFTRESET BIT(28)
#define RSI_BL_CTRL_START_FROM_ROM_PC BIT(29)
#define RSI_BL_CTRL_SPI_8BIT_MODE BIT(30)
#define RSI_BL_CTRL_LAST_ENTRY BIT(31)
struct bootload_entry {
__le32 control;
__le32 dst_addr; /* Destination address */
} __packed;
struct bootload_ds {
__le16 fixed_pattern;
__le16 offset;
__le32 reserved;
struct bootload_entry bl_entry[7];
} __packed;
int rsi_hal_device_init(struct rsi_hw *adapter);
int rsi_prepare_mgmt_desc(struct rsi_common *common, struct sk_buff *skb);
int rsi_prepare_data_desc(struct rsi_common *common, struct sk_buff *skb);
......
......@@ -33,6 +33,8 @@ struct rsi_hw;
#include "rsi_ps.h"
#define DRV_VER "RS9116.NB0.NL.PURISM.LNX.1.3"
#define ERR_ZONE BIT(0) /* For Error Msgs */
#define INFO_ZONE BIT(1) /* For General Status Msgs */
#define INIT_ZONE BIT(2) /* For Driver Init Seq Msgs */
......@@ -60,6 +62,7 @@ enum RSI_FSM_STATES {
extern u32 rsi_zone_enabled;
extern __printf(2, 3) void rsi_dbg(u32 zone, const char *fmt, ...);
void rsi_hex_dump(u32 zone, char *msg_str, const u8 *msg, u32 len);
#define RSI_MAX_VIFS 3
#define NUM_EDCA_QUEUES 4
......@@ -82,6 +85,14 @@ extern __printf(2, 3) void rsi_dbg(u32 zone, const char *fmt, ...);
#define MAX_CONTINUOUS_VI_PKTS 4
/* Hardware queue info */
#define RSI_COEX_Q 0x0
#define RSI_ZIGB_Q 0x1
#define RSI_BT_Q 0x2
#define RSI_WLAN_Q 0x3
#define RSI_WIFI_MGMT_Q 0x4
#define RSI_WIFI_DATA_Q 0x5
#define RSI_BT_MGMT_Q 0x6
#define RSI_BT_DATA_Q 0x7
#define BROADCAST_HW_Q 9
#define MGMT_HW_Q 10
#define BEACON_HW_Q 11
......@@ -112,6 +123,7 @@ extern __printf(2, 3) void rsi_dbg(u32 zone, const char *fmt, ...);
#define RSI_WOW_NO_CONNECTION BIT(1)
#define RSI_DEV_9113 1
#define RSI_DEV_9116 2
#define RSI_MAX_RX_PKTS 64
struct version_info {
......@@ -182,6 +194,17 @@ struct rsi_bgscan_params {
u16 passive_scan_duration;
};
struct rsi_9116_features {
u8 pll_mode;
u8 rf_type;
u8 wireless_mode;
u8 afe_type;
u8 enable_ppe;
u8 dpd;
u32 sifs_tx_enable;
u32 ps_options;
};
struct vif_priv {
bool is_ht;
bool sgi;
......@@ -194,6 +217,11 @@ struct rsi_event {
wait_queue_head_t event_queue;
};
enum {
ZB_DEVICE_NOT_READY = 0,
ZB_DEVICE_READY
};
struct rsi_thread {
void (*thread_function)(void *);
struct completion completion;
......@@ -221,6 +249,7 @@ struct rsi_common {
void *coex_cb;
bool mgmt_q_block;
char driver_ver[32];
struct version_info lmac_ver;
struct rsi_thread tx_thread;
......@@ -252,6 +281,7 @@ struct rsi_common {
/* state related */
u32 fsm_state;
u8 zb_fsm_state;
bool init_done;
u8 bb_rf_prog_count;
bool iface_down;
......@@ -312,6 +342,28 @@ struct rsi_common {
struct rsi_bgscan_params bgscan;
u8 bgscan_en;
u8 mac_ops_resumed;
/* RS9116 */
struct rsi_9116_features w9116_features;
bool antenna_diversity;
u16 peer_dist;
u16 bt_feature_bitmap;
u16 uart_debug;
u16 ext_opt;
u8 host_intf_on_demand;
u8 crystal_as_sleep_clk;
u16 feature_bitmap_9116;
u16 ble_roles;
bool three_wire_coex;
u16 bt_bdr_mode;
u16 anchor_point_gap;
u8 bt_rf_type;
u8 ble_tx_pwr_inx;
u8 ble_pwr_save_options;
u8 bt_rf_tx_power_mode;
u8 bt_rf_rx_power_mode;
u8 load_image_no;
u8 rsi_scan_count;
};
struct eepromrw_info {
......@@ -352,6 +404,7 @@ struct rsi_hw {
struct timer_list bl_cmd_timer;
bool blcmd_timer_expired;
u32 flash_capacity;
u32 common_hal_fsm;
struct eepromrw_info eeprom;
u32 interrupt_status;
u8 dfs_region;
......@@ -380,6 +433,9 @@ struct rsi_host_intf_ops {
int (*load_data_master_write)(struct rsi_hw *adapter, u32 addr,
u32 instructions_size, u16 block_size,
u8 *fw);
int (*ta_reset_ops)(struct rsi_hw *adapter);
int (*rsi_check_bus_status)(struct rsi_hw *adapter);
int (*check_hw_queue_status)(struct rsi_hw *adapter, u8 q_num);
int (*reinit_device)(struct rsi_hw *adapter);
};
......
......@@ -38,6 +38,8 @@
#define RSI_PAIRWISE_KEY 1
#define RSI_GROUP_KEY 2
#define RSI_MAC_SUB_LEN 3
/* EPPROM_READ_ADDRESS */
#define WLAN_MAC_EEPROM_ADDR 40
#define WLAN_MAC_MAGIC_WORD_LEN 0x01
......@@ -54,6 +56,8 @@
#define RSI_HW_BMISS_PKT BIT(4)
#define RSI_INSERT_SEQ_IN_FW BIT(2)
#define RSI_BAND_CHECK 0x03
#define WOW_MAX_FILTERS_PER_LIST 16
#define WOW_PATTERN_SIZE 256
......@@ -294,6 +298,7 @@ enum cmd_frame_type {
COMMON_DEV_CONFIG = 0x28,
RADIO_PARAMS_UPDATE = 0x29,
WOWLAN_CONFIG_PARAMS = 0x2B,
FEATURES_ENABLE = 0x33,
WOWLAN_WAKEUP_REASON = 0xc5
};
......@@ -346,6 +351,11 @@ struct rsi_cmd_desc {
struct rsi_cmd_desc_dword3 desc_dword3;
};
struct rsi_boot_params_9116 {
__le16 desc_word[8];
struct bootup_params_9116 bootup_params;
} __packed;
struct rsi_boot_params {
__le16 desc_word[8];
struct bootup_params bootup_params;
......@@ -588,7 +598,14 @@ struct rsi_config_vals {
u8 driver_mode;
u8 region_code;
u8 antenna_sel_val;
u8 reserved2[16];
u16 dev_peer_dist;
u16 dev_bt_feature_bitmap;
u16 uart_dbg;
u16 features_9116;
u16 dev_ble_roles;
u16 bt_bdr;
u16 dev_anchor_point_gap;
u8 reserved2[2];
} __packed;
/* Packet info flags */
......@@ -654,6 +671,22 @@ struct rsi_bgscan_probe {
__le16 probe_req_length;
} __packed;
#define RSI_DUTY_CYCLING BIT(0)