Commit b23b0ea3 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull more ARM SoC updates from Olof Johansson:
 "A few updates that we merged late but are low risk for regressions for
  other platforms (and a few other straggling patches):

   - I mis-tagged the 'drivers' branch, and missed 3 patches. Merged in
     here. They're for a driver for the PL353 SRAM controller and a
     build fix for the qualcomm scm driver.

   - A new platform, RDA Micro RDA8810PL (Cortex-A5 w/ integrated
     Vivante GPU, 256MB RAM, Wifi). This includes some acked
     platform-specific drivers (serial, etc). This also include DTs for
     two boards with this SoC, OrangePi 2G and OrangePi i86.

   - i.MX8 is another new platform (NXP, 4x Cortex-A53 + Cortex-M4, 4K
     video playback offload). This is the first i.MX 64-bit SoC.

   - Some minor updates to Samsung boards (adding a few peripherals in
     DTs).

   - Small rework for SMP bootup on STi platforms.

   - A couple of TEE driver fixes.

   - A couple of new config options (bcm2835 thermal, Uniphier MDMAC)
     enabled in defconfigs"

* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (27 commits)
  ARM: multi_v7_defconfig: enable CONFIG_UNIPHIER_MDMAC
  arm64: defconfig: Re-enable bcm2835-thermal driver
  MAINTAINERS: Add entry for RDA Micro SoC architecture
  tty: serial: Add RDA8810PL UART driver
  ARM: dts: rda8810pl: Add interrupt support for UART
  dt-bindings: serial: Document RDA Micro UART
  ARM: dts: rda8810pl: Add timer support
  ARM: dts: Add devicetree for OrangePi i96 board
  ARM: dts: Add devicetree for OrangePi 2G IoT board
  ARM: dts: Add devicetree for RDA8810PL SoC
  ARM: Prepare RDA8810PL SoC
  dt-bindings: arm: Document RDA8810PL and reference boards
  dt-bindings: Add RDA Micro vendor prefix
  ARM: sti: remove pen_release and boot_lock
  arm64: dts: exynos: Add Bluetooth chip to TM2(e) boards
  arm64: dts: imx8mq-evk: enable watchdog
  arm64: dts: imx8mq: add watchdog devices
  MAINTAINERS: add i.MX8 DT path to i.MX architecture
  arm64: add support for i.MX8M EVK board
  arm64: add basic DTS for i.MX8MQ
  ...
parents 078a5a4f 00f8ccd0
......@@ -1028,6 +1028,12 @@
specified address. The serial port must already be
setup and configured. Options are not yet supported.
rda,<addr>
Start an early, polled-mode console on a serial port
of an RDA Micro SoC, such as RDA8810PL, at the
specified address. The serial port must already be
setup and configured. Options are not yet supported.
smh Use ARM semihosting calls for early console.
s3c2410,<addr>
......
RDA Micro platforms device tree bindings
----------------------------------------
RDA8810PL SoC
=============
Required root node properties:
- compatible : must contain "rda,8810pl"
Boards:
Root node property compatible must contain, depending on board:
- Orange Pi 2G-IoT: "xunlong,orangepi-2g-iot"
- Orange Pi i96: "xunlong,orangepi-i96"
Device tree bindings for ARM PL353 static memory controller
PL353 static memory controller supports two kinds of memory
interfaces.i.e NAND and SRAM/NOR interfaces.
The actual devices are instantiated from the child nodes of pl353 smc node.
Required properties:
- compatible : Should be "arm,pl353-smc-r2p1", "arm,primecell".
- reg : Controller registers map and length.
- clock-names : List of input clock names - "memclk", "apb_pclk"
(See clock bindings for details).
- clocks : Clock phandles (see clock bindings for details).
- address-cells : Must be 2.
- size-cells : Must be 1.
Child nodes:
For NAND the "arm,pl353-nand-r2p1" and for NOR the "cfi-flash" drivers are
supported as child nodes.
for NAND partition information please refer the below file
Documentation/devicetree/bindings/mtd/partition.txt
Example:
smcc: memory-controller@e000e000
compatible = "arm,pl353-smc-r2p1", "arm,primecell";
clock-names = "memclk", "apb_pclk";
clocks = <&clkc 11>, <&clkc 44>;
reg = <0xe000e000 0x1000>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0x0 0x0 0xe1000000 0x1000000 //Nand CS Region
0x1 0x0 0xe2000000 0x2000000 //SRAM/NOR CS Region
0x2 0x0 0xe4000000 0x2000000>; //SRAM/NOR CS Region
nand_0: flash@e1000000 {
compatible = "arm,pl353-nand-r2p1"
reg = <0 0 0x1000000>;
(...)
};
nor0: flash@e2000000 {
compatible = "cfi-flash";
reg = <1 0 0x2000000>;
};
nor1: flash@e4000000 {
compatible = "cfi-flash";
reg = <2 0 0x2000000>;
};
};
RDA Micro UART
Required properties:
- compatible : "rda,8810pl-uart" for RDA8810PL SoCs.
- reg : Offset and length of the register set for the device.
- interrupts : Should contain UART interrupt.
- clocks : Phandle to the input clock.
Example:
uart2: serial@20a90000 {
compatible = "rda,8810pl-uart";
reg = <0x20a90000 0x1000>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&uart_clk>;
};
......@@ -325,6 +325,7 @@ ralink Mediatek/Ralink Technology Corp.
ramtron Ramtron International
raspberrypi Raspberry Pi Foundation
raydium Raydium Semiconductor Corp.
rda Unisoc Communications, Inc.
realtek Realtek Semiconductor Corp.
renesas Renesas Electronics Corporation
richtek Richtek Technology Corporation
......
......@@ -1540,6 +1540,7 @@ F: arch/arm/mach-imx/
F: arch/arm/mach-mxs/
F: arch/arm/boot/dts/imx*
F: arch/arm/configs/imx*_defconfig
F: arch/arm64/boot/dts/freescale/imx*
F: drivers/clk/imx/
F: drivers/firmware/imx/
F: drivers/soc/imx/
......@@ -1967,6 +1968,20 @@ M: Lennert Buytenhek <kernel@wantstofly.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
S: Maintained
ARM/RDA MICRO ARCHITECTURE
M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
L: linux-unisoc@lists.infradead.org (moderated for non-subscribers)
S: Maintained
F: arch/arm/boot/dts/rda8810pl-*
F: drivers/clocksource/timer-rda.c
F: drivers/irqchip/irq-rda-intc.c
F: drivers/tty/serial/rda-uart.c
F: Documentation/devicetree/bindings/arm/rda.txt
F: Documentation/devicetree/bindings/interrupt-controller/rda,8810pl-intc.txt
F: Documentation/devicetree/bindings/serial/rda,8810pl-uart.txt
F: Documentation/devicetree/bindings/timer/rda,8810pl-timer.txt
ARM/REALTEK ARCHITECTURE
M: Andreas Färber <afaerber@suse.de>
L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)
......
......@@ -787,6 +787,8 @@ source "arch/arm/plat-pxa/Kconfig"
source "arch/arm/mach-qcom/Kconfig"
source "arch/arm/mach-rda/Kconfig"
source "arch/arm/mach-realview/Kconfig"
source "arch/arm/mach-rockchip/Kconfig"
......
......@@ -202,6 +202,7 @@ machine-$(CONFIG_ARCH_ORION5X) += orion5x
machine-$(CONFIG_ARCH_PICOXCELL) += picoxcell
machine-$(CONFIG_ARCH_PXA) += pxa
machine-$(CONFIG_ARCH_QCOM) += qcom
machine-$(CONFIG_ARCH_RDA) += rda
machine-$(CONFIG_ARCH_REALVIEW) += realview
machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip
machine-$(CONFIG_ARCH_RPC) += rpc
......
......@@ -822,6 +822,9 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-msm8974-sony-xperia-castor.dtb \
qcom-msm8974-sony-xperia-honami.dtb \
qcom-mdm9615-wp8548-mangoh-green.dtb
dtb-$(CONFIG_ARCH_RDA) += \
rda8810pl-orangepi-2g-iot.dtb \
rda8810pl-orangepi-i96.dtb
dtb-$(CONFIG_ARCH_REALVIEW) += \
arm-realview-pb1176.dtb \
arm-realview-pb11mp.dtb \
......
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 Andreas Färber
* Copyright (c) 2018 Manivannan Sadhasivam
*/
/dts-v1/;
#include "rda8810pl.dtsi"
/ {
compatible = "xunlong,orangepi-2g-iot", "rda,8810pl";
model = "Orange Pi 2G-IoT";
aliases {
serial0 = &uart1;
serial1 = &uart2;
serial2 = &uart3;
};
chosen {
stdout-path = "serial2:921600n8";
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
uart_clk: uart-clk {
compatible = "fixed-clock";
clock-frequency = <921600>;
#clock-cells = <0>;
};
};
&uart1 {
status = "okay";
clocks = <&uart_clk>;
};
&uart2 {
status = "okay";
clocks = <&uart_clk>;
};
&uart3 {
status = "okay";
clocks = <&uart_clk>;
};
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2017 Andreas Färber
* Copyright (c) 2018 Manivannan Sadhasivam
*/
/dts-v1/;
#include "rda8810pl.dtsi"
/ {
compatible = "xunlong,orangepi-i96", "rda,8810pl";
model = "Orange Pi i96";
aliases {
serial0 = &uart2;
serial1 = &uart1;
serial2 = &uart3;
};
chosen {
stdout-path = "serial2:921600n8";
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x10000000>;
};
uart_clk: uart-clk {
compatible = "fixed-clock";
clock-frequency = <921600>;
#clock-cells = <0>;
};
};
&uart1 {
status = "okay";
clocks = <&uart_clk>;
};
&uart2 {
status = "okay";
clocks = <&uart_clk>;
};
&uart3 {
status = "okay";
clocks = <&uart_clk>;
};
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* RDA8810PL SoC
*
* Copyright (c) 2017 Andreas Färber
* Copyright (c) 2018 Manivannan Sadhasivam
*/
#include <dt-bindings/interrupt-controller/irq.h>
/ {
compatible = "rda,8810pl";
interrupt-parent = <&intc>;
#address-cells = <1>;
#size-cells = <1>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a5";
reg = <0x0>;
};
};
sram@100000 {
compatible = "mmio-sram";
reg = <0x100000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
};
apb@20800000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x20800000 0x100000>;
intc: interrupt-controller@0 {
compatible = "rda,8810pl-intc";
reg = <0x0 0x1000>;
interrupt-controller;
#interrupt-cells = <2>;
};
};
apb@20900000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x20900000 0x100000>;
timer@10000 {
compatible = "rda,8810pl-timer";
reg = <0x10000 0x1000>;
interrupts = <16 IRQ_TYPE_LEVEL_HIGH>,
<17 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hwtimer", "ostimer";
};
};
apb@20a00000 {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0x20a00000 0x100000>;
uart1: serial@0 {
compatible = "rda,8810pl-uart";
reg = <0x0 0x1000>;
interrupts = <9 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart2: serial@10000 {
compatible = "rda,8810pl-uart";
reg = <0x10000 0x1000>;
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
uart3: serial@90000 {
compatible = "rda,8810pl-uart";
reg = <0x90000 0x1000>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
};
l2: cache-controller@21100000 {
compatible = "arm,pl310-cache";
reg = <0x21100000 0x1000>;
cache-unified;
cache-level = <2>;
};
};
......@@ -867,6 +867,7 @@ CONFIG_STM32_DMA=y
CONFIG_STM32_DMAMUX=y
CONFIG_STM32_MDMA=y
CONFIG_TEGRA20_APB_DMA=y
CONFIG_UNIPHIER_MDMAC=y
CONFIG_XILINX_DMA=y
CONFIG_QCOM_BAM_DMA=y
CONFIG_DW_DMAC=y
......
menuconfig ARCH_RDA
bool "RDA Micro SoCs"
depends on ARCH_MULTI_V7
select RDA_INTC
select RDA_TIMER
help
This enables support for the RDA Micro 8810PL SoC family.
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
obj-$(CONFIG_SMP) += platsmp.o
obj-$(CONFIG_ARCH_STI) += board-dt.o
/*
* arch/arm/mach-sti/headsmp.S
*
* Copyright (C) 2013 STMicroelectronics (R&D) Limited.
* http://www.st.com
*
* Cloned from linux/arch/arm/mach-vexpress/headsmp.S
*
* Copyright (c) 2003 ARM Limited
* All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/linkage.h>
#include <linux/init.h>
/*
* ST specific entry point for secondary CPUs. This provides
* a "holding pen" into which all secondary cores are held until we're
* ready for them to initialise.
*/
ENTRY(sti_secondary_startup)
mrc p15, 0, r0, c0, c0, 5
and r0, r0, #15
adr r4, 1f
ldmia r4, {r5, r6}
sub r4, r4, r5
add r6, r6, r4
pen: ldr r7, [r6]
cmp r7, r0
bne pen
/*
* we've been released from the holding pen: secondary_stack
* should now contain the SVC stack for this core
*/
b secondary_startup
ENDPROC(sti_secondary_startup)
1: .long .
.long pen_release
......@@ -28,82 +28,33 @@
#include "smp.h"
static void write_pen_release(int val)
{
pen_release = val;
smp_wmb();
sync_cache_w(&pen_release);
}
static DEFINE_SPINLOCK(boot_lock);
static void sti_secondary_init(unsigned int cpu)
{
/*
* let the primary processor know we're out of the
* pen, then head off into the C entry point
*/
write_pen_release(-1);
/*
* Synchronise with the boot thread.
*/
spin_lock(&boot_lock);
spin_unlock(&boot_lock);
}
static u32 __iomem *cpu_strt_ptr;
static int sti_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
unsigned long timeout;
/*
* set synchronisation state between this boot processor
* and the secondary one
*/
spin_lock(&boot_lock);
unsigned long entry_pa = __pa_symbol(secondary_startup);
/*
* The secondary processor is waiting to be released from
* the holding pen - release it, then wait for it to flag
* that it has been released by resetting pen_release.
*
* Note that "pen_release" is the hardware CPU ID, whereas
* "cpu" is Linux's internal ID.
* Secondary CPU is initialised and started by a U-BOOTROM firmware.
* Secondary CPU is spinning and waiting for a write at cpu_strt_ptr.
* Writing secondary_startup address at cpu_strt_ptr makes it to
* jump directly to secondary_startup().
*/
write_pen_release(cpu_logical_map(cpu));
__raw_writel(entry_pa, cpu_strt_ptr);
/*
* Send the secondary CPU a soft interrupt, thereby causing
* it to jump to the secondary entrypoint.
*/
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) {
smp_rmb();
if (pen_release == -1)
break;
udelay(10);
}
/*
* now the secondary core is starting up let it run its
* calibrations, then wait for it to finish
*/
spin_unlock(&boot_lock);
/* wmb so that data is actually written before cache flush is done */
smp_wmb();
sync_cache_w(cpu_strt_ptr);
return pen_release != -1 ? -ENOSYS : 0;
return 0;
}
static void __init sti_smp_prepare_cpus(unsigned int max_cpus)
{
struct device_node *np;
void __iomem *scu_base;
u32 __iomem *cpu_strt_ptr;
u32 release_phys;
int cpu;
unsigned long entry_pa = __pa_symbol(sti_secondary_startup);
np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
......@@ -131,8 +82,8 @@ static void __init sti_smp_prepare_cpus(unsigned int max_cpus)
}
/*
* holding pen is usually configured in SBC DMEM but can also be
* in RAM.
* cpu-release-addr is usually configured in SBC DMEM but can
* also be in RAM.
*/
if (!memblock_is_memory(release_phys))
......@@ -142,22 +93,11 @@ static void __init sti_smp_prepare_cpus(unsigned int max_cpus)
cpu_strt_ptr =
(u32 __iomem *)phys_to_virt(release_phys);
__raw_writel(entry_pa, cpu_strt_ptr);
/*
* wmb so that data is actually written
* before cache flush is done
*/
smp_wmb();
sync_cache_w(cpu_strt_ptr);
if (!memblock_is_memory(release_phys))
iounmap(cpu_strt_ptr);
set_cpu_possible(cpu, true);
}
}
const struct smp_operations sti_smp_ops __initconst = {
.smp_prepare_cpus = sti_smp_prepare_cpus,
.smp_secondary_init = sti_secondary_init,
.smp_boot_secondary = sti_boot_secondary,
};
......@@ -142,6 +142,14 @@ config ARCH_MVEBU
- Armada 7K SoC Family
- Armada 8K SoC Family
config ARCH_MXC
bool "ARMv8 based NXP i.MX SoC family"
select ARM64_ERRATUM_843419
select ARM64_ERRATUM_845719
help
This enables support for the ARMv8 based SoCs in the
NXP i.MX family.
config ARCH_QCOM
bool "Qualcomm Platforms"
select GPIOLIB
......
......@@ -1202,6 +1202,20 @@
status = "okay";
};
&serial_3 {
status = "okay";
bluetooth {
compatible = "brcm,bcm43438-bt";
max-speed = <3000000>;
shutdown-gpios = <&gpd4 0 GPIO_ACTIVE_HIGH>;
device-wakeup-gpios = <&gpr3 7 GPIO_ACTIVE_HIGH>;
host-wakeup-gpios = <&gpa2 2 GPIO_ACTIVE_HIGH>;
clocks = <&s2mps13_osc S2MPS11_CLK_BT>;
clock-names = "extclk";
};
};
&spi_1 {
cs-gpios = <&gpd6 3 GPIO_ACTIVE_HIGH>;
status = "okay";
......
......@@ -544,6 +544,21 @@
power-domains = <&pd_cam1>;
};
cmu_imem: clock-controller@11060000 {
compatible = "samsung,exynos5433-cmu-imem";
reg = <0x11060000 0x1000>;
#clock-cells = <1>;
clock-names = "oscclk",
"aclk_imem_sssx_266",
"aclk_imem_266",
"aclk_imem_200";
clocks = <&xxti>,
<&cmu_top CLK_DIV_ACLK_IMEM_SSSX_266>,
<&cmu_top CLK_DIV_ACLK_IMEM_266>,
<&cmu_top CLK_DIV_ACLK_IMEM_200>;
};
pd_gscl: power-domain@105c4000 {
compatible = "samsung,exynos5433-pd";
reg = <0x105c4000 0x20>;
......
......@@ -18,3 +18,5 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* Copyright 2017 NXP
* Copyright (C) 2017-2018 Pengutronix, Lucas Stach <kernel@pengutronix.de>
*/
/dts-v1/;
#include "imx8mq.dtsi"
/ {
model = "NXP i.MX8MQ EVK";
compatible = "fsl,imx8mq-evk", "fsl,imx8mq";
chosen {
stdout-path = &uart1;
};
memory@40000000 {
device_type = "memory";
reg = <0x00000000 0x40000000 0 0xc0000000>;
};
reg_usdhc2_vmmc: regulator-vsd-3v3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_reg_usdhc2>;
compatible = "regulator-fixed";
regulator-name = "VSD_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii-id";
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic@8 {
compatible = "fsl,pfuze100";
reg = <0x8>;
regulators {
sw1a_reg: sw1ab {
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <1100000>;
};
sw1c_reg: sw1c {
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <1100000>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
sw3a_reg: sw3ab {
regulator-min-microvolt = <825000>;
regulator-max-microvolt = <1100000>;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-always-on;
};
vgen1_reg: vgen1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};