Commit cb3ec2f3 authored by Stephen Rothwell's avatar Stephen Rothwell

Merge remote-tracking branch 'phy-next/next'

parents ceaea814 49ee1406
...@@ -23,6 +23,8 @@ Optional properties: ...@@ -23,6 +23,8 @@ Optional properties:
register files". When set driver will request its register files". When set driver will request its
phandle as one companion-grf for some special SoCs phandle as one companion-grf for some special SoCs
(e.g RV1108). (e.g RV1108).
- extcon : phandle to the extcon device providing the cable state for
the otg phy.
Required nodes : a sub-node is required for each port the phy provides. Required nodes : a sub-node is required for each port the phy provides.
The sub-node name is used to identify host or otg port, The sub-node name is used to identify host or otg port,
......
...@@ -9,6 +9,7 @@ Required properties: ...@@ -9,6 +9,7 @@ Required properties:
"qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074 "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
"qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996, "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
"qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996, "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
"qcom,msm8998-qmp-usb3-phy" for USB3 QMP V3 phy on msm8998,
"qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845, "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
"qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845, "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845,
"qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845. "qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845.
...@@ -42,6 +43,8 @@ Required properties: ...@@ -42,6 +43,8 @@ Required properties:
"aux", "cfg_ahb", "ref". "aux", "cfg_ahb", "ref".
For "qcom,msm8996-qmp-usb3-phy" must contain: For "qcom,msm8996-qmp-usb3-phy" must contain:
"aux", "cfg_ahb", "ref". "aux", "cfg_ahb", "ref".
For "qcom,msm8998-qmp-usb3-phy" must contain:
"aux", "cfg_ahb", "ref".
For "qcom,sdm845-qmp-usb3-phy" must contain: For "qcom,sdm845-qmp-usb3-phy" must contain:
"aux", "cfg_ahb", "ref", "com_aux". "aux", "cfg_ahb", "ref", "com_aux".
For "qcom,sdm845-qmp-usb3-uni-phy" must contain: For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
...@@ -61,6 +64,8 @@ Required properties: ...@@ -61,6 +64,8 @@ Required properties:
"phy", "common", "cfg". "phy", "common", "cfg".
For "qcom,msm8996-qmp-usb3-phy" must contain For "qcom,msm8996-qmp-usb3-phy" must contain
"phy", "common". "phy", "common".
For "qcom,msm8998-qmp-usb3-phy" must contain
"phy", "common".
For "qcom,sdm845-qmp-usb3-phy" must contain: For "qcom,sdm845-qmp-usb3-phy" must contain:
"phy", "common". "phy", "common".
For "qcom,sdm845-qmp-usb3-uni-phy" must contain: For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
......
...@@ -6,6 +6,7 @@ QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets. ...@@ -6,6 +6,7 @@ QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
Required properties: Required properties:
- compatible: compatible list, contains - compatible: compatible list, contains
"qcom,msm8996-qusb2-phy" for 14nm PHY on msm8996, "qcom,msm8996-qusb2-phy" for 14nm PHY on msm8996,
"qcom,msm8998-qusb2-phy" for 10nm PHY on msm8998,
"qcom,sdm845-qusb2-phy" for 10nm PHY on sdm845. "qcom,sdm845-qusb2-phy" for 10nm PHY on sdm845.
- reg: offset and length of the PHY register set. - reg: offset and length of the PHY register set.
......
...@@ -5,6 +5,8 @@ This file provides information on what the device node for the R-Car generation ...@@ -5,6 +5,8 @@ This file provides information on what the device node for the R-Car generation
Required properties: Required properties:
- compatible: "renesas,usb2-phy-r8a774a1" if the device is a part of an R8A774A1 - compatible: "renesas,usb2-phy-r8a774a1" if the device is a part of an R8A774A1
SoC.
"renesas,usb2-phy-r8a774c0" if the device is a part of an R8A774C0
SoC. SoC.
"renesas,usb2-phy-r8a7795" if the device is a part of an R8A7795 "renesas,usb2-phy-r8a7795" if the device is a part of an R8A7795
SoC. SoC.
......
...@@ -35,6 +35,7 @@ Required properties: ...@@ -35,6 +35,7 @@ Required properties:
DRA7x DRA7x
Should be "ti,dra7x-usb2-phy2" for the 2nd instance of USB2 PHY Should be "ti,dra7x-usb2-phy2" for the 2nd instance of USB2 PHY
in DRA7x in DRA7x
Should be "ti,am654-usb2" for the USB2 PHYs on AM654.
- reg : Address and length of the register set for the device. - reg : Address and length of the register set for the device.
- #phy-cells: determine the number of cells that should be given in the - #phy-cells: determine the number of cells that should be given in the
phandle while referencing this phy. phandle while referencing this phy.
......
...@@ -2,4 +2,4 @@ config PHY_FSL_IMX8MQ_USB ...@@ -2,4 +2,4 @@ config PHY_FSL_IMX8MQ_USB
tristate "Freescale i.MX8M USB3 PHY" tristate "Freescale i.MX8M USB3 PHY"
depends on OF && HAS_IOMEM depends on OF && HAS_IOMEM
select GENERIC_PHY select GENERIC_PHY
default SOC_IMX8MQ default ARCH_MXC && ARM64
...@@ -687,6 +687,116 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = { ...@@ -687,6 +687,116 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02), QMP_PHY_INIT_CFG(QPHY_V3_PCS_MULTI_LANE_CTRL1, 0x02),
}; };
static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
};
static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
};
static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
};
static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL, 0x15),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
};
/* struct qmp_phy_cfg - per-PHY initialization config */ /* struct qmp_phy_cfg - per-PHY initialization config */
struct qmp_phy_cfg { struct qmp_phy_cfg {
/* phy-type - PCIE/UFS/USB */ /* phy-type - PCIE/UFS/USB */
...@@ -1036,6 +1146,33 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { ...@@ -1036,6 +1146,33 @@ static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
.no_pcs_sw_reset = true, .no_pcs_sw_reset = true,
}; };
static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
.type = PHY_TYPE_USB3,
.nlanes = 1,
.serdes_tbl = msm8998_usb3_serdes_tbl,
.serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
.tx_tbl = msm8998_usb3_tx_tbl,
.tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl),
.rx_tbl = msm8998_usb3_rx_tbl,
.rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl),
.pcs_tbl = msm8998_usb3_pcs_tbl,
.pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
.clk_list = msm8996_phy_clk_l,
.num_clks = ARRAY_SIZE(msm8996_phy_clk_l),
.reset_list = msm8996_usb3phy_reset_l,
.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
.vreg_list = qmp_phy_vreg_l,
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
.regs = qmp_v3_usb3phy_regs_layout,
.start_ctrl = SERDES_START | PCS_START,
.pwrdn_ctrl = SW_PWRDN,
.mask_pcs_ready = PHYSTATUS,
.is_dual_lane_phy = true,
};
static void qcom_qmp_phy_configure(void __iomem *base, static void qcom_qmp_phy_configure(void __iomem *base,
const unsigned int *regs, const unsigned int *regs,
const struct qmp_phy_init_tbl tbl[], const struct qmp_phy_init_tbl tbl[],
...@@ -1747,6 +1884,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = { ...@@ -1747,6 +1884,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
}, { }, {
.compatible = "qcom,sdm845-qmp-ufs-phy", .compatible = "qcom,sdm845-qmp-ufs-phy",
.data = &sdm845_ufsphy_cfg, .data = &sdm845_ufsphy_cfg,
}, {
.compatible = "qcom,msm8998-qmp-usb3-phy",
.data = &msm8998_usb3phy_cfg,
}, },
{ }, { },
}; };
......
...@@ -174,6 +174,7 @@ ...@@ -174,6 +174,7 @@
#define QSERDES_V3_COM_DIV_FRAC_START1_MODE1 0x0c4 #define QSERDES_V3_COM_DIV_FRAC_START1_MODE1 0x0c4
#define QSERDES_V3_COM_DIV_FRAC_START2_MODE1 0x0c8 #define QSERDES_V3_COM_DIV_FRAC_START2_MODE1 0x0c8
#define QSERDES_V3_COM_DIV_FRAC_START3_MODE1 0x0cc #define QSERDES_V3_COM_DIV_FRAC_START3_MODE1 0x0cc
#define QSERDES_V3_COM_INTEGLOOP_INITVAL 0x0d0
#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0 0x0d8 #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0 0x0d8
#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0 0x0dc #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0 0x0dc
#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1 0x0e0 #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1 0x0e0
...@@ -201,6 +202,7 @@ ...@@ -201,6 +202,7 @@
#define QSERDES_V3_COM_DEBUG_BUS2 0x170 #define QSERDES_V3_COM_DEBUG_BUS2 0x170
#define QSERDES_V3_COM_DEBUG_BUS3 0x174 #define QSERDES_V3_COM_DEBUG_BUS3 0x174
#define QSERDES_V3_COM_DEBUG_BUS_SEL 0x178 #define QSERDES_V3_COM_DEBUG_BUS_SEL 0x178
#define QSERDES_V3_COM_CMN_MODE 0x184
/* Only for QMP V3 PHY - TX registers */ /* Only for QMP V3 PHY - TX registers */
#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX 0x044 #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX 0x044
...@@ -211,6 +213,7 @@ ...@@ -211,6 +213,7 @@
#define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4 #define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4
/* Only for QMP V3 PHY - RX registers */ /* Only for QMP V3 PHY - RX registers */
#define QSERDES_V3_RX_UCDR_FO_GAIN 0x008
#define QSERDES_V3_RX_UCDR_SO_GAIN_HALF 0x00c #define QSERDES_V3_RX_UCDR_SO_GAIN_HALF 0x00c
#define QSERDES_V3_RX_UCDR_SO_GAIN 0x014 #define QSERDES_V3_RX_UCDR_SO_GAIN 0x014
#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF 0x024 #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF 0x024
...@@ -219,6 +222,7 @@ ...@@ -219,6 +222,7 @@
#define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x030 #define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x030
#define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 #define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034
#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c #define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c
#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040
#define QSERDES_V3_RX_UCDR_PI_CONTROLS 0x044 #define QSERDES_V3_RX_UCDR_PI_CONTROLS 0x044
#define QSERDES_V3_RX_RX_TERM_BW 0x07c #define QSERDES_V3_RX_RX_TERM_BW 0x07c
#define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc #define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc
......
...@@ -152,6 +152,31 @@ static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = { ...@@ -152,6 +152,31 @@ static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = {
QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00), QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00),
}; };
static const unsigned int msm8998_regs_layout[] = {
[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8,
[QUSB2PHY_PLL_STATUS] = 0x1a0,
[QUSB2PHY_PORT_TUNE1] = 0x23c,
[QUSB2PHY_PORT_TUNE2] = 0x240,
[QUSB2PHY_PORT_TUNE3] = 0x244,
[QUSB2PHY_PORT_TUNE4] = 0x248,
[QUSB2PHY_PORT_TEST1] = 0x24c,
[QUSB2PHY_PORT_TEST2] = 0x250,
[QUSB2PHY_PORT_POWERDOWN] = 0x210,
[QUSB2PHY_INTR_CTRL] = 0x22c,
};
static const struct qusb2_phy_init_tbl msm8998_init_tbl[] = {
QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x13),
QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c),
QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80),
QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a),
QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xa5),
QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x09),
QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19),
};
static const unsigned int sdm845_regs_layout[] = { static const unsigned int sdm845_regs_layout[] = {
[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8, [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8,
[QUSB2PHY_PLL_STATUS] = 0x1a0, [QUSB2PHY_PLL_STATUS] = 0x1a0,
...@@ -221,6 +246,18 @@ static const struct qusb2_phy_cfg msm8996_phy_cfg = { ...@@ -221,6 +246,18 @@ static const struct qusb2_phy_cfg msm8996_phy_cfg = {
.autoresume_en = BIT(3), .autoresume_en = BIT(3),
}; };
static const struct qusb2_phy_cfg msm8998_phy_cfg = {
.tbl = msm8998_init_tbl,
.tbl_num = ARRAY_SIZE(msm8998_init_tbl),
.regs = msm8998_regs_layout,
.disable_ctrl = POWER_DOWN,
.mask_core_ready = CORE_READY_STATUS,
.has_pll_override = true,
.autoresume_en = BIT(0),
.update_tune1_with_efuse = true,
};
static const struct qusb2_phy_cfg sdm845_phy_cfg = { static const struct qusb2_phy_cfg sdm845_phy_cfg = {
.tbl = sdm845_init_tbl, .tbl = sdm845_init_tbl,
.tbl_num = ARRAY_SIZE(sdm845_init_tbl), .tbl_num = ARRAY_SIZE(sdm845_init_tbl),
...@@ -733,6 +770,9 @@ static const struct of_device_id qusb2_phy_of_match_table[] = { ...@@ -733,6 +770,9 @@ static const struct of_device_id qusb2_phy_of_match_table[] = {
{ {
.compatible = "qcom,msm8996-qusb2-phy", .compatible = "qcom,msm8996-qusb2-phy",
.data = &msm8996_phy_cfg, .data = &msm8996_phy_cfg,
}, {
.compatible = "qcom,msm8998-qusb2-phy",
.data = &msm8998_phy_cfg,
}, { }, {
.compatible = "qcom,sdm845-qusb2-phy", .compatible = "qcom,sdm845-qusb2-phy",
.data = &sdm845_phy_cfg, .data = &sdm845_phy_cfg,
......
...@@ -23,24 +23,7 @@ ...@@ -23,24 +23,7 @@
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/delay.h> #include <linux/delay.h>
#include <linux/iopoll.h>
#define readl_poll_timeout(addr, val, cond, sleep_us, timeout_us) \
({ \
ktime_t timeout = ktime_add_us(ktime_get(), timeout_us); \
might_sleep_if(timeout_us); \
for (;;) { \
(val) = readl(addr); \
if (cond) \
break; \
if (timeout_us && ktime_compare(ktime_get(), timeout) > 0) { \
(val) = readl(addr); \
break; \
} \
if (sleep_us) \
usleep_range(DIV_ROUND_UP(sleep_us, 4), sleep_us); \
} \
(cond) ? 0 : -ETIMEDOUT; \
})
#define UFS_QCOM_PHY_CAL_ENTRY(reg, val) \ #define UFS_QCOM_PHY_CAL_ENTRY(reg, val) \
{ \ { \
......
...@@ -55,16 +55,16 @@ enum rockchip_usb2phy_host_state { ...@@ -55,16 +55,16 @@ enum rockchip_usb2phy_host_state {
}; };
/** /**
* Different states involved in USB charger detection. * enum usb_chg_state - Different states involved in USB charger detection.
* USB_CHG_STATE_UNDEFINED USB charger is not connected or detection * @USB_CHG_STATE_UNDEFINED: USB charger is not connected or detection
* process is not yet started. * process is not yet started.
* USB_CHG_STATE_WAIT_FOR_DCD Waiting for Data pins contact. * @USB_CHG_STATE_WAIT_FOR_DCD: Waiting for Data pins contact.
* USB_CHG_STATE_DCD_DONE Data pin contact is detected. * @USB_CHG_STATE_DCD_DONE: Data pin contact is detected.
* USB_CHG_STATE_PRIMARY_DONE Primary detection is completed (Detects * @USB_CHG_STATE_PRIMARY_DONE: Primary detection is completed (Detects
* between SDP and DCP/CDP). * between SDP and DCP/CDP).
* USB_CHG_STATE_SECONDARY_DONE Secondary detection is completed (Detects * @USB_CHG_STATE_SECONDARY_DONE: Secondary detection is completed (Detects
* between DCP and CDP). * between DCP and CDP).
* USB_CHG_STATE_DETECTED USB charger type is determined. * @USB_CHG_STATE_DETECTED: USB charger type is determined.
*/ */
enum usb_chg_state { enum usb_chg_state {
USB_CHG_STATE_UNDEFINED = 0, USB_CHG_STATE_UNDEFINED = 0,
...@@ -94,7 +94,7 @@ struct usb2phy_reg { ...@@ -94,7 +94,7 @@ struct usb2phy_reg {
}; };
/** /**
* struct rockchip_chg_det_reg: usb charger detect registers * struct rockchip_chg_det_reg - usb charger detect registers
* @cp_det: charging port detected successfully. * @cp_det: charging port detected successfully.
* @dcp_det: dedicated charging port detected successfully. * @dcp_det: dedicated charging port detected successfully.
* @dp_det: assert data pin connect successfully. * @dp_det: assert data pin connect successfully.
...@@ -120,7 +120,7 @@ struct rockchip_chg_det_reg { ...@@ -120,7 +120,7 @@ struct rockchip_chg_det_reg {
}; };
/** /**
* struct rockchip_usb2phy_port_cfg: usb-phy port configuration. * struct rockchip_usb2phy_port_cfg - usb-phy port configuration.
* @phy_sus: phy suspend register. * @phy_sus: phy suspend register.
* @bvalid_det_en: vbus valid rise detection enable register. * @bvalid_det_en: vbus valid rise detection enable register.
* @bvalid_det_st: vbus valid rise detection status register. * @bvalid_det_st: vbus valid rise detection status register.
...@@ -148,10 +148,11 @@ struct rockchip_usb2phy_port_cfg { ...@@ -148,10 +148,11 @@ struct rockchip_usb2phy_port_cfg {
}; };
/** /**
* struct rockchip_usb2phy_cfg: usb-phy configuration. * struct rockchip_usb2phy_cfg - usb-phy configuration.
* @reg: the address offset of grf for usb-phy config. * @reg: the address offset of grf for usb-phy config.
* @num_ports: specify how many ports that the phy has. * @num_ports: specify how many ports that the phy has.
* @clkout_ctl: keep on/turn off output clk of phy. * @clkout_ctl: keep on/turn off output clk of phy.
* @port_cfgs: usb-phy port configurations.
* @chg_det: charger detection registers. * @chg_det: charger detection registers.
*/ */
struct rockchip_usb2phy_cfg { struct rockchip_usb2phy_cfg {
...@@ -163,12 +164,10 @@ struct rockchip_usb2phy_cfg { ...@@ -163,12 +164,10 @@ struct rockchip_usb2phy_cfg {
}; };
/** /**
* struct rockchip_usb2phy_port: usb-phy port data. * struct rockchip_usb2phy_port - usb-phy port data.
* @phy: generic phy.
* @port_id: flag for otg port or host port. * @port_id: flag for otg port or host port.
* @suspended: phy suspended flag. * @suspended: phy suspended flag.
* @utmi_avalid: utmi avalid status usage flag.
* true - use avalid to get vbus status
* flase - use bvalid to get vbus status
* @vbus_attached: otg device vbus status. * @vbus_attached: otg device vbus status.
* @bvalid_irq: IRQ number assigned for vbus valid rise detection. * @bvalid_irq: IRQ number assigned for vbus valid rise detection.
* @ls_irq: IRQ number assigned for linestate detection. * @ls_irq: IRQ number assigned for linestate detection.
...@@ -178,7 +177,7 @@ struct rockchip_usb2phy_cfg { ...@@ -178,7 +177,7 @@ struct rockchip_usb2phy_cfg {
* @chg_work: charge detect work. * @chg_work: charge detect work.
* @otg_sm_work: OTG state machine work. * @otg_sm_work: OTG state machine work.
* @sm_work: HOST state machine work. * @sm_work: HOST state machine work.
* @phy_cfg: port register configuration, assigned by driver data. * @port_cfg: port register configuration, assigned by driver data.
* @event_nb: hold event notification callback. * @event_nb: hold event notification callback.
* @state: define OTG enumeration states before device reset. * @state: define OTG enumeration states before device reset.
* @mode: the dr_mode of the controller. * @mode: the dr_mode of the controller.
...@@ -187,7 +186,6 @@ struct rockchip_usb2phy_port { ...@@ -187,7 +186,6 @@ struct rockchip_usb2phy_port {
struct phy *phy; struct phy *phy;
unsigned int port_id; unsigned int port_id;
bool suspended; bool suspended;
bool utmi_avalid;
bool vbus_attached; bool vbus_attached;
int bvalid_irq; int bvalid_irq;
int ls_irq; int ls_irq;
...@@ -203,12 +201,13 @@ struct rockchip_usb2phy_port { ...@@ -203,12 +201,13 @@ struct rockchip_usb2phy_port {
}; };
/** /**
* struct rockchip_usb2phy: usb2.0 phy driver data. * struct rockchip_usb2phy - usb2.0 phy driver data.
* @dev: pointer to device.
* @grf: General Register Files regmap. * @grf: General Register Files regmap.
* @usbgrf: USB General Register Files regmap. * @usbgrf: USB General Register Files regmap.
* @clk: clock struct of phy input clk. * @clk: clock struct of phy input clk.
* @clk480m: clock struct of phy output clk. * @clk480m: clock struct of phy output clk.
* @clk_hw: clock struct of phy output clk management. * @clk480m_hw: clock struct of phy output clk management.
* @chg_state: states involved in USB charger detection. * @chg_state: states involved in USB charger detection.
* @chg_type: USB charger types. * @chg_type: USB charger types.
* @dcd_retries: The retry count used to track Data contact * @dcd_retries: The retry count used to track Data contact
...@@ -542,12 +541,8 @@ static void rockchip_usb2phy_otg_sm_work(struct work_struct *work) ...@@ -542,12 +541,8 @@ static void rockchip_usb2phy_otg_sm_work(struct work_struct *work)
unsigned long delay; unsigned long delay;
bool vbus_attach, sch_work, notify_charger; bool vbus_attach, sch_work, notify_charger;
if (rport->utmi_avalid) vbus_attach = property_enabled(rphy->grf,
vbus_attach = property_enabled(rphy->grf, &rport->port_cfg->utmi_bvalid);
&rport->port_cfg->utmi_avalid);
else
vbus_attach = property_enabled(rphy->grf,
&rport->port_cfg->utmi_bvalid);
sch_work = false; sch_work = false;
notify_charger = false; notify_charger = false;
...@@ -1021,9 +1016,6 @@ static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy, ...@@ -1021,9 +1016,6 @@ static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work); INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work);
INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work); INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
rport->utmi_avalid =
of_property_read_bool(child_np, "rockchip,utmi-avalid");
/* /*
* Some SoCs use one interrupt with otg-id/otg-bvalid/linestate * Some SoCs use one interrupt with otg-id/otg-bvalid/linestate
* interrupts muxed together, so probe the otg-mux interrupt first, * interrupts muxed together, so probe the otg-mux interrupt first,
......
...@@ -33,12 +33,11 @@ config OMAP_CONTROL_PHY ...@@ -33,12 +33,11 @@ config OMAP_CONTROL_PHY
config OMAP_USB2 config OMAP_USB2
tristate "OMAP USB2 PHY Driver" tristate "OMAP USB2 PHY Driver"
depends on ARCH_OMAP2PLUS depends on ARCH_OMAP2PLUS || ARCH_K3
depends on USB_SUPPORT depends on USB_SUPPORT
select GENERIC_PHY select GENERIC_PHY
select USB_PHY select USB_PHY
select OMAP_CONTROL_PHY select OMAP_CONTROL_PHY if ARCH_OMAP2PLUS
depends on OMAP_OCP2SCP
help help
Enable this to support the transceiver that is part of SOC. This Enable this to support the transceiver that is part of SOC. This
driver takes care of all the PHY functionality apart from comparator. driver takes care of all the PHY functionality apart from comparator.
...@@ -50,7 +49,6 @@ config TI_PIPE3 ...@@ -50,7 +49,6 @@ config TI_PIPE3
depends on ARCH_OMAP2PLUS || COMPILE_TEST depends on ARCH_OMAP2PLUS || COMPILE_TEST
select GENERIC_PHY select GENERIC_PHY
select OMAP_CONTROL_PHY select OMAP_CONTROL_PHY
depends on OMAP_OCP2SCP
help help
Enable this to support the PIPE3 PHY that is part of TI SOCs. This Enable this to support the PIPE3 PHY that is part of TI SOCs. This
driver takes care of all the PHY functionality apart from comparator. driver takes care of all the PHY functionality apart from comparator.
......
...@@ -36,6 +36,10 @@ ...@@ -36,6 +36,10 @@
#define USB2PHY_DISCON_BYP_LATCH (1 << 31) #define USB2PHY_DISCON_BYP_LATCH (1 << 31)
#define USB2PHY_ANA_CONFIG1 0x4c #define USB2PHY_ANA_CONFIG1 0x4c
#define AM654_USB2_OTG_PD BIT(8)
#define AM654_USB2_VBUS_DET_EN BIT(5)
#define AM654_USB2_VBUSVALID_DET_EN BIT(4)
/** /**
* omap_usb2_set_comparator - links the comparator present in the sytem with * omap_usb2_set_comparator - links the comparator present in the sytem with
* this phy * this phy
...@@ -135,9 +139,9 @@ static int omap_usb_power_on(struct phy *x) ...@@ -135,9 +139,9 @@ static int omap_usb_power_on(struct phy *x)
static int omap_usb2_disable_clocks(struct omap_usb *phy) static int omap_usb2_disable_clocks(struct omap_usb *phy)
{ {
clk_disable(phy->wkupclk); clk_disable_unprepare(phy->wkupclk);
if (!IS_ERR(phy->optclk)) if (!IS_ERR(phy->optclk))
clk_disable(phy->optclk); clk_disable_unprepare(phy->optclk);
return 0; return 0;
} }
...@@ -146,14 +150,14 @@ static int omap_usb2_enable_clocks(struct omap_usb *phy) ...@@ -146,14 +150,14 @@ static int omap_usb2_enable_clocks(struct omap_usb *phy)
{ {
int ret; int ret;
ret = clk_enable(phy->wkupclk); ret = clk_prepare_enable(phy->wkupclk);
if (ret < 0) { if (ret < 0) {
dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret); dev_err(phy->dev, "Failed to enable wkupclk %d\n", ret);
goto err0; goto err0;
} }
if (!IS_ERR(phy->optclk)) { if (!IS_ERR(phy->optclk)) {
ret = clk_enable(phy->optclk); ret = clk_prepare_enable(phy->optclk);
if (ret < 0) { if (ret < 0) {
dev_err(phy->dev, "Failed to enable optclk %d\n", ret); dev_err(phy->dev, "Failed to enable optclk %d\n", ret);
goto err1; goto err1;
...@@ -245,6 +249,15 @@ static const struct usb_phy_data am437x_usb2_data = { ...@@ -245,6 +249,15 @@ static const struct usb_phy_data am437x_usb2_data = {
.power_off = AM437X_USB2_PHY_PD | AM437X_USB2_OTG_PD, .power_off = AM437X_USB2_PHY_PD | AM437X_USB2_OTG_PD,
}; };
static const struct usb_phy_data am654_usb2_data = {
.label = "am654_usb2",
.flags = OMAP_USB2_CALIBRATE_FALSE_DISCONNECT,
.mask = AM654_USB2_OTG_PD | AM654_USB2_VBUS_DET_EN |
AM654_USB2_VBUSVALID_DET_EN,
.power_on = AM654_USB2_VBUS_DET_EN | AM654_USB2_VBUSVALID_DET_EN,
.power_off = AM654_USB2_OTG_PD,
};
static const struct of_device_id omap_usb2_id_table[] = { static const struct of_device_id omap_usb2_id_table[] = {
{ {
.compatible = "ti,omap-usb2", .compatible = "ti,omap-usb2",
...@@ -266,6 +279,10 @@ static const struct of_device_id omap_usb2_id_table[] = { ...@@ -266,6 +279,10 @@ static const struct of_device_id omap_usb2_id_table[] = {
.compatible = "ti,am437x-usb2", .compatible = "ti,am437x-usb2",
.data = &am437x_usb2_data, .data = &am437x_usb2_data,
}, },
{
.compatible = "ti,am654-usb2",
.data = &am654_usb2_data,
},
{}, {},