Commit f86330d2 authored by Stephen Rothwell's avatar Stephen Rothwell

Merge remote-tracking branch 'pinctrl/for-next'

parents a7956ce7 489d4832
......@@ -58,11 +58,11 @@ group pwm3
- functions pwm, gpio
group pmic1
- pin 17
- pin 7
- functions pmic, gpio
group pmic0
- pin 16
- pin 6
- functions pmic, gpio
group i2c2
......@@ -112,19 +112,31 @@ group usb2_drvvbus1
- functions drvbus, gpio
group sdio_sb
- pins 60-64
- pins 60-65
- functions sdio, gpio
group rgmii
- pins 42-55
- pins 42-53
- functions mii, gpio
group pcie1
- pins 39-40
- pins 39
- functions pcie, gpio
group pcie1_clkreq
- pins 40
- functions pcie, gpio
group pcie1_wakeup
- pins 41
- functions pcie, gpio
group smi
- pins 54-55
- functions smi, gpio
group ptp
- pins 56-58
- pins 56
- functions ptp, gpio
group ptp_clk
......
......@@ -129,6 +129,13 @@ config PINCTRL_IMX8MQ
help
Say Y here to enable the imx8mq pinctrl driver
config PINCTRL_IMX8QM
bool "IMX8QM pinctrl driver"
depends on ARCH_MXC && ARM64
select PINCTRL_IMX_SCU
help
Say Y here to enable the imx8qm pinctrl driver
config PINCTRL_IMX8QXP
bool "IMX8QXP pinctrl driver"
depends on ARCH_MXC && ARM64
......
......@@ -19,6 +19,7 @@ obj-$(CONFIG_PINCTRL_IMX6UL) += pinctrl-imx6ul.o
obj-$(CONFIG_PINCTRL_IMX7D) += pinctrl-imx7d.o
obj-$(CONFIG_PINCTRL_IMX7ULP) += pinctrl-imx7ulp.o
obj-$(CONFIG_PINCTRL_IMX8MQ) += pinctrl-imx8mq.o
obj-$(CONFIG_PINCTRL_IMX8QM) += pinctrl-imx8qm.o
obj-$(CONFIG_PINCTRL_IMX8QXP) += pinctrl-imx8qxp.o
obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
......
This diff is collapsed.
......@@ -45,12 +45,14 @@ config PINCTRL_MT2701
config PINCTRL_MT7623
bool "Mediatek MT7623 pin control with generic binding"
depends on MACH_MT7623 || COMPILE_TEST
depends on OF
default MACH_MT7623
select PINCTRL_MTK_MOORE
config PINCTRL_MT7629
bool "Mediatek MT7629 pin control"
depends on MACH_MT7629 || COMPILE_TEST
depends on OF
default MACH_MT7629
select PINCTRL_MTK_MOORE
......@@ -92,6 +94,7 @@ config PINCTRL_MT6797
config PINCTRL_MT7622
bool "MediaTek MT7622 pin control"
depends on OF
depends on ARM64 || COMPILE_TEST
default ARM64 && ARCH_MEDIATEK
select PINCTRL_MTK_MOORE
......
......@@ -290,7 +290,13 @@ static int mtk_xt_set_gpio_as_eint(void *data, unsigned long eint_n)
return err;
err = mtk_hw_set_value(hw, desc, PINCTRL_PIN_REG_SMT, MTK_ENABLE);
if (err)
/* SMT is supposed to be supported by every real GPIO and doesn't
* support virtual GPIOs, so the extra condition err != -ENOTSUPP
* is just for adding EINT support to these virtual GPIOs. It should
* add an extra flag in the pin descriptor when more pins with
* distinctive characteristic come out.
*/
if (err && err != -ENOTSUPP)
return err;
return 0;
......
......@@ -170,8 +170,8 @@ static struct armada_37xx_pin_group armada_37xx_nb_groups[] = {
PIN_GRP_GPIO("pwm1", 12, 1, BIT(4), "pwm"),
PIN_GRP_GPIO("pwm2", 13, 1, BIT(5), "pwm"),
PIN_GRP_GPIO("pwm3", 14, 1, BIT(6), "pwm"),
PIN_GRP_GPIO("pmic1", 17, 1, BIT(7), "pmic"),
PIN_GRP_GPIO("pmic0", 16, 1, BIT(8), "pmic"),
PIN_GRP_GPIO("pmic1", 7, 1, BIT(7), "pmic"),
PIN_GRP_GPIO("pmic0", 6, 1, BIT(8), "pmic"),
PIN_GRP_GPIO("i2c2", 2, 2, BIT(9), "i2c"),
PIN_GRP_GPIO("i2c1", 0, 2, BIT(10), "i2c"),
PIN_GRP_GPIO("spi_cs1", 17, 1, BIT(12), "spi"),
......@@ -195,8 +195,11 @@ static struct armada_37xx_pin_group armada_37xx_sb_groups[] = {
PIN_GRP_GPIO("usb2_drvvbus1", 1, 1, BIT(1), "drvbus"),
PIN_GRP_GPIO("sdio_sb", 24, 6, BIT(2), "sdio"),
PIN_GRP_GPIO("rgmii", 6, 12, BIT(3), "mii"),
PIN_GRP_GPIO("pcie1", 3, 2, BIT(4), "pcie"),
PIN_GRP_GPIO("ptp", 20, 3, BIT(5), "ptp"),
PIN_GRP_GPIO("smi", 18, 2, BIT(4), "smi"),
PIN_GRP_GPIO("pcie1", 3, 1, BIT(5), "pcie"),
PIN_GRP_GPIO("pcie1_clkreq", 4, 1, BIT(9), "pcie"),
PIN_GRP_GPIO("pcie1_wakeup", 5, 1, BIT(10), "pcie"),
PIN_GRP_GPIO("ptp", 20, 3, BIT(11) | BIT(12) | BIT(13), "ptp"),
PIN_GRP("ptp_clk", 21, 1, BIT(6), "ptp", "mii"),
PIN_GRP("ptp_trig", 22, 1, BIT(7), "ptp", "mii"),
PIN_GRP_GPIO_3("mii_col", 23, 1, BIT(8) | BIT(14), 0, BIT(8), BIT(14),
......
......@@ -489,7 +489,7 @@ static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
/*
* If WAKE_INT_MASTER_REG.MaskStsEn is set, a software write to the
* debounce registers of any GPIO will block wake/interrupt status
* generation for *all* GPIOs for a lenght of time that depends on
* generation for *all* GPIOs for a length of time that depends on
* WAKE_INT_MASTER_REG.MaskStsLength[11:0]. During this period the
* INTERRUPT_ENABLE bit will read as 0.
*
......
......@@ -1139,8 +1139,7 @@ static int mcp23s08_probe(struct spi_device *spi)
return -ENODEV;
data = devm_kzalloc(&spi->dev,
sizeof(*data) + chips * sizeof(struct mcp23s08),
GFP_KERNEL);
struct_size(data, chip, chips), GFP_KERNEL);
if (!data)
return -ENOMEM;
......
......@@ -6007,8 +6007,8 @@ static int atlas7_gpio_probe(struct platform_device *pdev)
}
/* retrieve gpio descriptor data */
a7gc = devm_kzalloc(&pdev->dev, sizeof(*a7gc) +
sizeof(struct atlas7_gpio_bank) * nbank, GFP_KERNEL);
a7gc = devm_kzalloc(&pdev->dev, struct_size(a7gc, banks, nbank),
GFP_KERNEL);
if (!a7gc)
return -ENOMEM;
......
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