arm-cci.c 63.1 KB
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/*
 * CCI cache coherent interconnect driver
 *
 * Copyright (C) 2013 ARM Ltd.
 * Author: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/arm-cci.h>
#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
#include <linux/of_address.h>
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#include <linux/of_irq.h>
#include <linux/of_platform.h>
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#include <linux/perf_event.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <asm/cacheflush.h>
#include <asm/smp_plat.h>

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static void __iomem *cci_ctrl_base;
static unsigned long cci_ctrl_phys;
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#ifdef CONFIG_ARM_CCI400_PORT_CTRL
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struct cci_nb_ports {
	unsigned int nb_ace;
	unsigned int nb_ace_lite;
};

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static const struct cci_nb_ports cci400_ports = {
	.nb_ace = 2,
	.nb_ace_lite = 3
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};

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#define CCI400_PORTS_DATA	(&cci400_ports)
#else
#define CCI400_PORTS_DATA	(NULL)
#endif

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static const struct of_device_id arm_cci_matches[] = {
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#ifdef CONFIG_ARM_CCI400_COMMON
	{.compatible = "arm,cci-400", .data = CCI400_PORTS_DATA },
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#endif
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#ifdef CONFIG_ARM_CCI5xx_PMU
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	{ .compatible = "arm,cci-500", },
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	{ .compatible = "arm,cci-550", },
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#endif
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	{},
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};

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#ifdef CONFIG_ARM_CCI_PMU
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#define DRIVER_NAME		"ARM-CCI"
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#define DRIVER_NAME_PMU		DRIVER_NAME " PMU"

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#define CCI_PMCR		0x0100
#define CCI_PID2		0x0fe8

#define CCI_PMCR_CEN		0x00000001
#define CCI_PMCR_NCNT_MASK	0x0000f800
#define CCI_PMCR_NCNT_SHIFT	11

#define CCI_PID2_REV_MASK	0xf0
#define CCI_PID2_REV_SHIFT	4

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#define CCI_PMU_EVT_SEL		0x000
#define CCI_PMU_CNTR		0x004
#define CCI_PMU_CNTR_CTRL	0x008
#define CCI_PMU_OVRFLW		0x00c

#define CCI_PMU_OVRFLW_FLAG	1

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#define CCI_PMU_CNTR_SIZE(model)	((model)->cntr_size)
#define CCI_PMU_CNTR_BASE(model, idx)	((idx) * CCI_PMU_CNTR_SIZE(model))
#define CCI_PMU_CNTR_MASK		((1ULL << 32) -1)
#define CCI_PMU_CNTR_LAST(cci_pmu)	(cci_pmu->num_cntrs - 1)
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#define CCI_PMU_MAX_HW_CNTRS(model) \
	((model)->num_hw_cntrs + (model)->fixed_hw_cntrs)
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/* Types of interfaces that can generate events */
enum {
	CCI_IF_SLAVE,
	CCI_IF_MASTER,
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#ifdef CONFIG_ARM_CCI5xx_PMU
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	CCI_IF_GLOBAL,
#endif
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	CCI_IF_MAX,
};

struct event_range {
	u32 min;
	u32 max;
};

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struct cci_pmu_hw_events {
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	struct perf_event **events;
	unsigned long *used_mask;
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	raw_spinlock_t pmu_lock;
};

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struct cci_pmu;
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/*
 * struct cci_pmu_model:
 * @fixed_hw_cntrs - Number of fixed event counters
 * @num_hw_cntrs - Maximum number of programmable event counters
 * @cntr_size - Size of an event counter mapping
 */
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struct cci_pmu_model {
	char *name;
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	u32 fixed_hw_cntrs;
	u32 num_hw_cntrs;
	u32 cntr_size;
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	struct attribute **format_attrs;
	struct attribute **event_attrs;
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	struct event_range event_ranges[CCI_IF_MAX];
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	int (*validate_hw_event)(struct cci_pmu *, unsigned long);
	int (*get_event_idx)(struct cci_pmu *, struct cci_pmu_hw_events *, unsigned long);
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	void (*write_counters)(struct cci_pmu *, unsigned long *);
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};

static struct cci_pmu_model cci_pmu_models[];

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struct cci_pmu {
	void __iomem *base;
	struct pmu pmu;
	int nr_irqs;
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	int *irqs;
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	unsigned long active_irqs;
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	const struct cci_pmu_model *model;
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	struct cci_pmu_hw_events hw_events;
	struct platform_device *plat_device;
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	int num_cntrs;
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	atomic_t active_events;
	struct mutex reserve_mutex;
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	struct hlist_node node;
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	cpumask_t cpus;
};

#define to_cci_pmu(c)	(container_of(c, struct cci_pmu, pmu))

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enum cci_models {
#ifdef CONFIG_ARM_CCI400_PMU
	CCI400_R0,
	CCI400_R1,
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#endif
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#ifdef CONFIG_ARM_CCI5xx_PMU
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	CCI500_R0,
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	CCI550_R0,
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#endif
	CCI_MODEL_MAX
};

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static void pmu_write_counters(struct cci_pmu *cci_pmu,
				 unsigned long *mask);
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static ssize_t cci_pmu_format_show(struct device *dev,
			struct device_attribute *attr, char *buf);
static ssize_t cci_pmu_event_show(struct device *dev,
			struct device_attribute *attr, char *buf);

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#define CCI_EXT_ATTR_ENTRY(_name, _func, _config) 				\
	&((struct dev_ext_attribute[]) {					\
		{ __ATTR(_name, S_IRUGO, _func, NULL), (void *)_config }	\
	})[0].attr.attr
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#define CCI_FORMAT_EXT_ATTR_ENTRY(_name, _config) \
	CCI_EXT_ATTR_ENTRY(_name, cci_pmu_format_show, (char *)_config)
#define CCI_EVENT_EXT_ATTR_ENTRY(_name, _config) \
	CCI_EXT_ATTR_ENTRY(_name, cci_pmu_event_show, (unsigned long)_config)

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/* CCI400 PMU Specific definitions */

#ifdef CONFIG_ARM_CCI400_PMU

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/* Port ids */
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#define CCI400_PORT_S0		0
#define CCI400_PORT_S1		1
#define CCI400_PORT_S2		2
#define CCI400_PORT_S3		3
#define CCI400_PORT_S4		4
#define CCI400_PORT_M0		5
#define CCI400_PORT_M1		6
#define CCI400_PORT_M2		7

#define CCI400_R1_PX		5
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/*
 * Instead of an event id to monitor CCI cycles, a dedicated counter is
 * provided. Use 0xff to represent CCI cycles and hope that no future revisions
 * make use of this event in hardware.
 */
enum cci400_perf_events {
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	CCI400_PMU_CYCLES = 0xff
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};

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#define CCI400_PMU_CYCLE_CNTR_IDX	0
#define CCI400_PMU_CNTR0_IDX		1
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/*
 * CCI PMU event id is an 8-bit value made of two parts - bits 7:5 for one of 8
 * ports and bits 4:0 are event codes. There are different event codes
 * associated with each port type.
 *
 * Additionally, the range of events associated with the port types changed
 * between Rev0 and Rev1.
 *
 * The constants below define the range of valid codes for each port type for
 * the different revisions and are used to validate the event to be monitored.
 */

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#define CCI400_PMU_EVENT_MASK		0xffUL
#define CCI400_PMU_EVENT_SOURCE_SHIFT	5
#define CCI400_PMU_EVENT_SOURCE_MASK	0x7
#define CCI400_PMU_EVENT_CODE_SHIFT	0
#define CCI400_PMU_EVENT_CODE_MASK	0x1f
#define CCI400_PMU_EVENT_SOURCE(event) \
	((event >> CCI400_PMU_EVENT_SOURCE_SHIFT) & \
			CCI400_PMU_EVENT_SOURCE_MASK)
#define CCI400_PMU_EVENT_CODE(event) \
	((event >> CCI400_PMU_EVENT_CODE_SHIFT) & CCI400_PMU_EVENT_CODE_MASK)

#define CCI400_R0_SLAVE_PORT_MIN_EV	0x00
#define CCI400_R0_SLAVE_PORT_MAX_EV	0x13
#define CCI400_R0_MASTER_PORT_MIN_EV	0x14
#define CCI400_R0_MASTER_PORT_MAX_EV	0x1a

#define CCI400_R1_SLAVE_PORT_MIN_EV	0x00
#define CCI400_R1_SLAVE_PORT_MAX_EV	0x14
#define CCI400_R1_MASTER_PORT_MIN_EV	0x00
#define CCI400_R1_MASTER_PORT_MAX_EV	0x11
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#define CCI400_CYCLE_EVENT_EXT_ATTR_ENTRY(_name, _config) \
	CCI_EXT_ATTR_ENTRY(_name, cci400_pmu_cycle_event_show, \
					(unsigned long)_config)

static ssize_t cci400_pmu_cycle_event_show(struct device *dev,
			struct device_attribute *attr, char *buf);

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static struct attribute *cci400_pmu_format_attrs[] = {
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	CCI_FORMAT_EXT_ATTR_ENTRY(event, "config:0-4"),
	CCI_FORMAT_EXT_ATTR_ENTRY(source, "config:5-7"),
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	NULL
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};

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static struct attribute *cci400_r0_pmu_event_attrs[] = {
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	/* Slave events */
	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_any, 0x0),
	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_device, 0x01),
	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_normal_or_nonshareable, 0x2),
	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_inner_or_outershareable, 0x3),
	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_cache_maintenance, 0x4),
	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_mem_barrier, 0x5),
	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_sync_barrier, 0x6),
	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_dvm_msg, 0x7),
	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_dvm_msg_sync, 0x8),
	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_stall_tt_full, 0x9),
	CCI_EVENT_EXT_ATTR_ENTRY(si_r_data_last_hs_snoop, 0xA),
	CCI_EVENT_EXT_ATTR_ENTRY(si_r_data_stall_rvalids_h_rready_l, 0xB),
	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_any, 0xC),
	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_device, 0xD),
	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_normal_or_nonshareable, 0xE),
	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_inner_or_outershare_wback_wclean, 0xF),
	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_write_unique, 0x10),
	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_write_line_unique, 0x11),
	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_evict, 0x12),
	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_stall_tt_full, 0x13),
	/* Master events */
	CCI_EVENT_EXT_ATTR_ENTRY(mi_retry_speculative_fetch, 0x14),
	CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_addr_hazard, 0x15),
	CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_id_hazard, 0x16),
	CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_tt_full, 0x17),
	CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_barrier_hazard, 0x18),
	CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall_barrier_hazard, 0x19),
	CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall_tt_full, 0x1A),
	/* Special event for cycles counter */
	CCI400_CYCLE_EVENT_EXT_ATTR_ENTRY(cycles, 0xff),
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	NULL
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};

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static struct attribute *cci400_r1_pmu_event_attrs[] = {
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	/* Slave events */
	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_any, 0x0),
	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_device, 0x01),
	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_normal_or_nonshareable, 0x2),
	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_inner_or_outershareable, 0x3),
	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_cache_maintenance, 0x4),
	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_mem_barrier, 0x5),
	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_sync_barrier, 0x6),
	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_dvm_msg, 0x7),
	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_dvm_msg_sync, 0x8),
	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_stall_tt_full, 0x9),
	CCI_EVENT_EXT_ATTR_ENTRY(si_r_data_last_hs_snoop, 0xA),
	CCI_EVENT_EXT_ATTR_ENTRY(si_r_data_stall_rvalids_h_rready_l, 0xB),
	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_any, 0xC),
	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_device, 0xD),
	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_normal_or_nonshareable, 0xE),
	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_inner_or_outershare_wback_wclean, 0xF),
	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_write_unique, 0x10),
	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_write_line_unique, 0x11),
	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_evict, 0x12),
	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_stall_tt_full, 0x13),
	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_stall_slave_id_hazard, 0x14),
	/* Master events */
	CCI_EVENT_EXT_ATTR_ENTRY(mi_retry_speculative_fetch, 0x0),
	CCI_EVENT_EXT_ATTR_ENTRY(mi_stall_cycle_addr_hazard, 0x1),
	CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_master_id_hazard, 0x2),
	CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_hi_prio_rtq_full, 0x3),
	CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_barrier_hazard, 0x4),
	CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall_barrier_hazard, 0x5),
	CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall_wtq_full, 0x6),
	CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_low_prio_rtq_full, 0x7),
	CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_mid_prio_rtq_full, 0x8),
	CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_qvn_vn0, 0x9),
	CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_qvn_vn1, 0xA),
	CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_qvn_vn2, 0xB),
	CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall_qvn_vn3, 0xC),
	CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall_qvn_vn0, 0xD),
	CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall_qvn_vn1, 0xE),
	CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall_qvn_vn2, 0xF),
	CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall_qvn_vn3, 0x10),
	CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_unique_or_line_unique_addr_hazard, 0x11),
	/* Special event for cycles counter */
	CCI400_CYCLE_EVENT_EXT_ATTR_ENTRY(cycles, 0xff),
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	NULL
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};

static ssize_t cci400_pmu_cycle_event_show(struct device *dev,
			struct device_attribute *attr, char *buf)
{
	struct dev_ext_attribute *eattr = container_of(attr,
				struct dev_ext_attribute, attr);
	return snprintf(buf, PAGE_SIZE, "config=0x%lx\n", (unsigned long)eattr->var);
}

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static int cci400_get_event_idx(struct cci_pmu *cci_pmu,
				struct cci_pmu_hw_events *hw,
				unsigned long cci_event)
{
	int idx;

	/* cycles event idx is fixed */
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	if (cci_event == CCI400_PMU_CYCLES) {
		if (test_and_set_bit(CCI400_PMU_CYCLE_CNTR_IDX, hw->used_mask))
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			return -EAGAIN;

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		return CCI400_PMU_CYCLE_CNTR_IDX;
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	}

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	for (idx = CCI400_PMU_CNTR0_IDX; idx <= CCI_PMU_CNTR_LAST(cci_pmu); ++idx)
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		if (!test_and_set_bit(idx, hw->used_mask))
			return idx;

	/* No counters available */
	return -EAGAIN;
}

static int cci400_validate_hw_event(struct cci_pmu *cci_pmu, unsigned long hw_event)
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{
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	u8 ev_source = CCI400_PMU_EVENT_SOURCE(hw_event);
	u8 ev_code = CCI400_PMU_EVENT_CODE(hw_event);
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	int if_type;
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	if (hw_event & ~CCI400_PMU_EVENT_MASK)
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		return -ENOENT;

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	if (hw_event == CCI400_PMU_CYCLES)
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		return hw_event;

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	switch (ev_source) {
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	case CCI400_PORT_S0:
	case CCI400_PORT_S1:
	case CCI400_PORT_S2:
	case CCI400_PORT_S3:
	case CCI400_PORT_S4:
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		/* Slave Interface */
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		if_type = CCI_IF_SLAVE;
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		break;
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	case CCI400_PORT_M0:
	case CCI400_PORT_M1:
	case CCI400_PORT_M2:
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		/* Master Interface */
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		if_type = CCI_IF_MASTER;
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		break;
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	default:
		return -ENOENT;
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	}

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	if (ev_code >= cci_pmu->model->event_ranges[if_type].min &&
		ev_code <= cci_pmu->model->event_ranges[if_type].max)
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		return hw_event;

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	return -ENOENT;
}

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static int probe_cci400_revision(void)
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{
	int rev;
	rev = readl_relaxed(cci_ctrl_base + CCI_PID2) & CCI_PID2_REV_MASK;
	rev >>= CCI_PID2_REV_SHIFT;

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	if (rev < CCI400_R1_PX)
		return CCI400_R0;
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	else
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		return CCI400_R1;
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}

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static const struct cci_pmu_model *probe_cci_model(struct platform_device *pdev)
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{
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	if (platform_has_secure_cci_access())
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		return &cci_pmu_models[probe_cci400_revision()];
	return NULL;
}
#else	/* !CONFIG_ARM_CCI400_PMU */
static inline struct cci_pmu_model *probe_cci_model(struct platform_device *pdev)
{
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	return NULL;
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}
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#endif	/* CONFIG_ARM_CCI400_PMU */
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#ifdef CONFIG_ARM_CCI5xx_PMU
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/*
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 * CCI5xx PMU event id is an 9-bit value made of two parts.
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 *	 bits [8:5] - Source for the event
 *	 bits [4:0] - Event code (specific to type of interface)
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 *
 *
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 */

/* Port ids */
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#define CCI5xx_PORT_S0			0x0
#define CCI5xx_PORT_S1			0x1
#define CCI5xx_PORT_S2			0x2
#define CCI5xx_PORT_S3			0x3
#define CCI5xx_PORT_S4			0x4
#define CCI5xx_PORT_S5			0x5
#define CCI5xx_PORT_S6			0x6

#define CCI5xx_PORT_M0			0x8
#define CCI5xx_PORT_M1			0x9
#define CCI5xx_PORT_M2			0xa
#define CCI5xx_PORT_M3			0xb
#define CCI5xx_PORT_M4			0xc
#define CCI5xx_PORT_M5			0xd
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#define CCI5xx_PORT_M6			0xe
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#define CCI5xx_PORT_GLOBAL		0xf

#define CCI5xx_PMU_EVENT_MASK		0x1ffUL
#define CCI5xx_PMU_EVENT_SOURCE_SHIFT	0x5
#define CCI5xx_PMU_EVENT_SOURCE_MASK	0xf
#define CCI5xx_PMU_EVENT_CODE_SHIFT	0x0
#define CCI5xx_PMU_EVENT_CODE_MASK	0x1f

#define CCI5xx_PMU_EVENT_SOURCE(event)	\
	((event >> CCI5xx_PMU_EVENT_SOURCE_SHIFT) & CCI5xx_PMU_EVENT_SOURCE_MASK)
#define CCI5xx_PMU_EVENT_CODE(event)	\
	((event >> CCI5xx_PMU_EVENT_CODE_SHIFT) & CCI5xx_PMU_EVENT_CODE_MASK)

#define CCI5xx_SLAVE_PORT_MIN_EV	0x00
#define CCI5xx_SLAVE_PORT_MAX_EV	0x1f
#define CCI5xx_MASTER_PORT_MIN_EV	0x00
#define CCI5xx_MASTER_PORT_MAX_EV	0x06
#define CCI5xx_GLOBAL_PORT_MIN_EV	0x00
#define CCI5xx_GLOBAL_PORT_MAX_EV	0x0f


#define CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(_name, _config) \
	CCI_EXT_ATTR_ENTRY(_name, cci5xx_pmu_global_event_show, \
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					(unsigned long) _config)

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static ssize_t cci5xx_pmu_global_event_show(struct device *dev,
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				struct device_attribute *attr, char *buf);

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static struct attribute *cci5xx_pmu_format_attrs[] = {
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	CCI_FORMAT_EXT_ATTR_ENTRY(event, "config:0-4"),
	CCI_FORMAT_EXT_ATTR_ENTRY(source, "config:5-8"),
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	NULL,
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};

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static struct attribute *cci5xx_pmu_event_attrs[] = {
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	/* Slave events */
	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_arvalid, 0x0),
	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_dev, 0x1),
	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_nonshareable, 0x2),
	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_shareable_non_alloc, 0x3),
	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_shareable_alloc, 0x4),
	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_invalidate, 0x5),
	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_cache_maint, 0x6),
	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_dvm_msg, 0x7),
	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_rval, 0x8),
	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_hs_rlast_snoop, 0x9),
	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_hs_awalid, 0xA),
	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_dev, 0xB),
	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_non_shareable, 0xC),
	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_share_wb, 0xD),
	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_share_wlu, 0xE),
	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_share_wunique, 0xF),
	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_evict, 0x10),
	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_wrevict, 0x11),
	CCI_EVENT_EXT_ATTR_ENTRY(si_w_data_beat, 0x12),
	CCI_EVENT_EXT_ATTR_ENTRY(si_srq_acvalid, 0x13),
	CCI_EVENT_EXT_ATTR_ENTRY(si_srq_read, 0x14),
	CCI_EVENT_EXT_ATTR_ENTRY(si_srq_clean, 0x15),
	CCI_EVENT_EXT_ATTR_ENTRY(si_srq_data_transfer_low, 0x16),
	CCI_EVENT_EXT_ATTR_ENTRY(si_rrq_stall_arvalid, 0x17),
	CCI_EVENT_EXT_ATTR_ENTRY(si_r_data_stall, 0x18),
	CCI_EVENT_EXT_ATTR_ENTRY(si_wrq_stall, 0x19),
	CCI_EVENT_EXT_ATTR_ENTRY(si_w_data_stall, 0x1A),
	CCI_EVENT_EXT_ATTR_ENTRY(si_w_resp_stall, 0x1B),
	CCI_EVENT_EXT_ATTR_ENTRY(si_srq_stall, 0x1C),
	CCI_EVENT_EXT_ATTR_ENTRY(si_s_data_stall, 0x1D),
	CCI_EVENT_EXT_ATTR_ENTRY(si_rq_stall_ot_limit, 0x1E),
	CCI_EVENT_EXT_ATTR_ENTRY(si_r_stall_arbit, 0x1F),

	/* Master events */
	CCI_EVENT_EXT_ATTR_ENTRY(mi_r_data_beat_any, 0x0),
	CCI_EVENT_EXT_ATTR_ENTRY(mi_w_data_beat_any, 0x1),
	CCI_EVENT_EXT_ATTR_ENTRY(mi_rrq_stall, 0x2),
	CCI_EVENT_EXT_ATTR_ENTRY(mi_r_data_stall, 0x3),
	CCI_EVENT_EXT_ATTR_ENTRY(mi_wrq_stall, 0x4),
	CCI_EVENT_EXT_ATTR_ENTRY(mi_w_data_stall, 0x5),
	CCI_EVENT_EXT_ATTR_ENTRY(mi_w_resp_stall, 0x6),

	/* Global events */
537 538 539 540 541 542 543 544 545 546 547 548 549 550
	CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_filter_bank_0_1, 0x0),
	CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_filter_bank_2_3, 0x1),
	CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_filter_bank_4_5, 0x2),
	CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_filter_bank_6_7, 0x3),
	CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_miss_filter_bank_0_1, 0x4),
	CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_miss_filter_bank_2_3, 0x5),
	CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_miss_filter_bank_4_5, 0x6),
	CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_access_miss_filter_bank_6_7, 0x7),
	CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_back_invalidation, 0x8),
	CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_stall_alloc_busy, 0x9),
	CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_stall_tt_full, 0xA),
	CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_wrq, 0xB),
	CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_cd_hs, 0xC),
	CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_rq_stall_addr_hazard, 0xD),
551
	CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_rq_stall_tt_full, 0xE),
552
	CCI5xx_GLOBAL_EVENT_EXT_ATTR_ENTRY(cci_snoop_rq_tzmp1_prot, 0xF),
553
	NULL
554 555
};

556
static ssize_t cci5xx_pmu_global_event_show(struct device *dev,
557 558 559 560 561 562
				struct device_attribute *attr, char *buf)
{
	struct dev_ext_attribute *eattr = container_of(attr,
					struct dev_ext_attribute, attr);
	/* Global events have single fixed source code */
	return snprintf(buf, PAGE_SIZE, "event=0x%lx,source=0x%x\n",
563
				(unsigned long)eattr->var, CCI5xx_PORT_GLOBAL);
564 565
}

566 567 568 569 570 571 572 573 574
/*
 * CCI500 provides 8 independent event counters that can count
 * any of the events available.
 * CCI500 PMU event source ids
 *	0x0-0x6 - Slave interfaces
 *	0x8-0xD - Master interfaces
 *	0xf     - Global Events
 *	0x7,0xe - Reserved
 */
575 576 577
static int cci500_validate_hw_event(struct cci_pmu *cci_pmu,
					unsigned long hw_event)
{
578 579
	u32 ev_source = CCI5xx_PMU_EVENT_SOURCE(hw_event);
	u32 ev_code = CCI5xx_PMU_EVENT_CODE(hw_event);
580 581
	int if_type;

582
	if (hw_event & ~CCI5xx_PMU_EVENT_MASK)
583 584 585
		return -ENOENT;

	switch (ev_source) {
586 587 588 589 590 591 592
	case CCI5xx_PORT_S0:
	case CCI5xx_PORT_S1:
	case CCI5xx_PORT_S2:
	case CCI5xx_PORT_S3:
	case CCI5xx_PORT_S4:
	case CCI5xx_PORT_S5:
	case CCI5xx_PORT_S6:
593 594
		if_type = CCI_IF_SLAVE;
		break;
595 596 597 598 599 600
	case CCI5xx_PORT_M0:
	case CCI5xx_PORT_M1:
	case CCI5xx_PORT_M2:
	case CCI5xx_PORT_M3:
	case CCI5xx_PORT_M4:
	case CCI5xx_PORT_M5:
601 602
		if_type = CCI_IF_MASTER;
		break;
603
	case CCI5xx_PORT_GLOBAL:
604 605 606 607 608 609 610 611 612 613 614 615
		if_type = CCI_IF_GLOBAL;
		break;
	default:
		return -ENOENT;
	}

	if (ev_code >= cci_pmu->model->event_ranges[if_type].min &&
		ev_code <= cci_pmu->model->event_ranges[if_type].max)
		return hw_event;

	return -ENOENT;
}
616

617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668
/*
 * CCI550 provides 8 independent event counters that can count
 * any of the events available.
 * CCI550 PMU event source ids
 *	0x0-0x6 - Slave interfaces
 *	0x8-0xe - Master interfaces
 *	0xf     - Global Events
 *	0x7	- Reserved
 */
static int cci550_validate_hw_event(struct cci_pmu *cci_pmu,
					unsigned long hw_event)
{
	u32 ev_source = CCI5xx_PMU_EVENT_SOURCE(hw_event);
	u32 ev_code = CCI5xx_PMU_EVENT_CODE(hw_event);
	int if_type;

	if (hw_event & ~CCI5xx_PMU_EVENT_MASK)
		return -ENOENT;

	switch (ev_source) {
	case CCI5xx_PORT_S0:
	case CCI5xx_PORT_S1:
	case CCI5xx_PORT_S2:
	case CCI5xx_PORT_S3:
	case CCI5xx_PORT_S4:
	case CCI5xx_PORT_S5:
	case CCI5xx_PORT_S6:
		if_type = CCI_IF_SLAVE;
		break;
	case CCI5xx_PORT_M0:
	case CCI5xx_PORT_M1:
	case CCI5xx_PORT_M2:
	case CCI5xx_PORT_M3:
	case CCI5xx_PORT_M4:
	case CCI5xx_PORT_M5:
	case CCI5xx_PORT_M6:
		if_type = CCI_IF_MASTER;
		break;
	case CCI5xx_PORT_GLOBAL:
		if_type = CCI_IF_GLOBAL;
		break;
	default:
		return -ENOENT;
	}

	if (ev_code >= cci_pmu->model->event_ranges[if_type].min &&
		ev_code <= cci_pmu->model->event_ranges[if_type].max)
		return hw_event;

	return -ENOENT;
}

669
#endif	/* CONFIG_ARM_CCI5xx_PMU */
670

671 672 673 674 675
/*
 * Program the CCI PMU counters which have PERF_HES_ARCH set
 * with the event period and mark them ready before we enable
 * PMU.
 */
676
static void cci_pmu_sync_counters(struct cci_pmu *cci_pmu)
677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701
{
	int i;
	struct cci_pmu_hw_events *cci_hw = &cci_pmu->hw_events;

	DECLARE_BITMAP(mask, cci_pmu->num_cntrs);

	bitmap_zero(mask, cci_pmu->num_cntrs);
	for_each_set_bit(i, cci_pmu->hw_events.used_mask, cci_pmu->num_cntrs) {
		struct perf_event *event = cci_hw->events[i];

		if (WARN_ON(!event))
			continue;

		/* Leave the events which are not counting */
		if (event->hw.state & PERF_HES_STOPPED)
			continue;
		if (event->hw.state & PERF_HES_ARCH) {
			set_bit(i, mask);
			event->hw.state &= ~PERF_HES_ARCH;
		}
	}

	pmu_write_counters(cci_pmu, mask);
}

702
/* Should be called with cci_pmu->hw_events->pmu_lock held */
703
static void __cci_pmu_enable_nosync(struct cci_pmu *cci_pmu)
704 705 706 707 708 709 710 711
{
	u32 val;

	/* Enable all the PMU counters. */
	val = readl_relaxed(cci_ctrl_base + CCI_PMCR) | CCI_PMCR_CEN;
	writel(val, cci_ctrl_base + CCI_PMCR);
}

712 713 714 715 716 717 718
/* Should be called with cci_pmu->hw_events->pmu_lock held */
static void __cci_pmu_enable_sync(struct cci_pmu *cci_pmu)
{
	cci_pmu_sync_counters(cci_pmu);
	__cci_pmu_enable_nosync(cci_pmu);
}

719 720 721 722 723 724 725 726 727 728
/* Should be called with cci_pmu->hw_events->pmu_lock held */
static void __cci_pmu_disable(void)
{
	u32 val;

	/* Disable all the PMU counters. */
	val = readl_relaxed(cci_ctrl_base + CCI_PMCR) & ~CCI_PMCR_CEN;
	writel(val, cci_ctrl_base + CCI_PMCR);
}

729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746
static ssize_t cci_pmu_format_show(struct device *dev,
			struct device_attribute *attr, char *buf)
{
	struct dev_ext_attribute *eattr = container_of(attr,
				struct dev_ext_attribute, attr);
	return snprintf(buf, PAGE_SIZE, "%s\n", (char *)eattr->var);
}

static ssize_t cci_pmu_event_show(struct device *dev,
			struct device_attribute *attr, char *buf)
{
	struct dev_ext_attribute *eattr = container_of(attr,
				struct dev_ext_attribute, attr);
	/* source parameter is mandatory for normal PMU events */
	return snprintf(buf, PAGE_SIZE, "source=?,event=0x%lx\n",
					 (unsigned long)eattr->var);
}

747
static int pmu_is_valid_counter(struct cci_pmu *cci_pmu, int idx)
748
{
749
	return 0 <= idx && idx <= CCI_PMU_CNTR_LAST(cci_pmu);
750 751
}

752
static u32 pmu_read_register(struct cci_pmu *cci_pmu, int idx, unsigned int offset)
753
{
754 755
	return readl_relaxed(cci_pmu->base +
			     CCI_PMU_CNTR_BASE(cci_pmu->model, idx) + offset);
756 757
}

758 759
static void pmu_write_register(struct cci_pmu *cci_pmu, u32 value,
			       int idx, unsigned int offset)
760
{
761 762
	writel_relaxed(value, cci_pmu->base +
		       CCI_PMU_CNTR_BASE(cci_pmu->model, idx) + offset);
763 764
}

765
static void pmu_disable_counter(struct cci_pmu *cci_pmu, int idx)
766
{
767
	pmu_write_register(cci_pmu, 0, idx, CCI_PMU_CNTR_CTRL);
768 769
}

770
static void pmu_enable_counter(struct cci_pmu *cci_pmu, int idx)
771
{
772
	pmu_write_register(cci_pmu, 1, idx, CCI_PMU_CNTR_CTRL);
773 774
}

775 776 777 778 779 780
static bool __maybe_unused
pmu_counter_is_enabled(struct cci_pmu *cci_pmu, int idx)
{
	return (pmu_read_register(cci_pmu, idx, CCI_PMU_CNTR_CTRL) & 0x1) != 0;
}

781
static void pmu_set_event(struct cci_pmu *cci_pmu, int idx, unsigned long event)
782
{
783
	pmu_write_register(cci_pmu, event, idx, CCI_PMU_EVT_SEL);
784 785
}

786 787 788 789 790 791 792 793 794 795 796 797 798 799 800 801 802 803 804 805 806 807 808 809 810 811 812 813 814 815 816 817 818 819 820 821 822 823
/*
 * For all counters on the CCI-PMU, disable any 'enabled' counters,
 * saving the changed counters in the mask, so that we can restore
 * it later using pmu_restore_counters. The mask is private to the
 * caller. We cannot rely on the used_mask maintained by the CCI_PMU
 * as it only tells us if the counter is assigned to perf_event or not.
 * The state of the perf_event cannot be locked by the PMU layer, hence
 * we check the individual counter status (which can be locked by
 * cci_pm->hw_events->pmu_lock).
 *
 * @mask should be initialised to empty by the caller.
 */
static void __maybe_unused
pmu_save_counters(struct cci_pmu *cci_pmu, unsigned long *mask)
{
	int i;

	for (i = 0; i < cci_pmu->num_cntrs; i++) {
		if (pmu_counter_is_enabled(cci_pmu, i)) {
			set_bit(i, mask);
			pmu_disable_counter(cci_pmu, i);
		}
	}
}

/*
 * Restore the status of the counters. Reversal of the pmu_save_counters().
 * For each counter set in the mask, enable the counter back.
 */
static void __maybe_unused
pmu_restore_counters(struct cci_pmu *cci_pmu, unsigned long *mask)
{
	int i;

	for_each_set_bit(i, mask, cci_pmu->num_cntrs)
		pmu_enable_counter(cci_pmu, i);
}

824 825 826 827
/*
 * Returns the number of programmable counters actually implemented
 * by the cci
 */
828 829
static u32 pmu_get_max_counters(void)
{
830 831
	return (readl_relaxed(cci_ctrl_base + CCI_PMCR) &
		CCI_PMCR_NCNT_MASK) >> CCI_PMCR_NCNT_SHIFT;
832 833
}

834
static int pmu_get_event_idx(struct cci_pmu_hw_events *hw, struct perf_event *event)
835
{
836
	struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu);
837
	unsigned long cci_event = event->hw.config_base;
838 839
	int idx;

840 841
	if (cci_pmu->model->get_event_idx)
		return cci_pmu->model->get_event_idx(cci_pmu, hw, cci_event);
842

843 844
	/* Generic code to find an unused idx from the mask */
	for(idx = 0; idx <= CCI_PMU_CNTR_LAST(cci_pmu); idx++)
845 846 847 848 849 850 851 852 853
		if (!test_and_set_bit(idx, hw->used_mask))
			return idx;

	/* No counters available */
	return -EAGAIN;
}

static int pmu_map_event(struct perf_event *event)
{
854
	struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu);
855

856 857
	if (event->attr.type < PERF_TYPE_MAX ||
			!cci_pmu->model->validate_hw_event)
858 859
		return -ENOENT;

860
	return	cci_pmu->model->validate_hw_event(cci_pmu, event->attr.config);
861 862
}

863
static int pmu_request_irq(struct cci_pmu *cci_pmu, irq_handler_t handler)
864 865 866 867 868 869 870
{
	int i;
	struct platform_device *pmu_device = cci_pmu->plat_device;

	if (unlikely(!pmu_device))
		return -ENODEV;

871
	if (cci_pmu->nr_irqs < 1) {
872 873 874 875 876 877 878 879 880 881 882
		dev_err(&pmu_device->dev, "no irqs for CCI PMUs defined\n");
		return -ENODEV;
	}

	/*
	 * Register all available CCI PMU interrupts. In the interrupt handler
	 * we iterate over the counters checking for interrupt source (the
	 * overflowing counter) and clear it.
	 *
	 * This should allow handling of non-unique interrupt for the counters.
	 */
883 884
	for (i = 0; i < cci_pmu->nr_irqs; i++) {
		int err = request_irq(cci_pmu->irqs[i], handler, IRQF_SHARED,
885 886 887
				"arm-cci-pmu", cci_pmu);
		if (err) {
			dev_err(&pmu_device->dev, "unable to request IRQ%d for ARM CCI PMU counters\n",
888
				cci_pmu->irqs[i]);
889 890 891
			return err;
		}

892
		set_bit(i, &cci_pmu->active_irqs);
893 894 895 896 897
	}

	return 0;
}

898 899 900 901
static void pmu_free_irq(struct cci_pmu *cci_pmu)
{
	int i;

902 903
	for (i = 0; i < cci_pmu->nr_irqs; i++) {
		if (!test_and_clear_bit(i, &cci_pmu->active_irqs))
904 905
			continue;

906
		free_irq(cci_pmu->irqs[i], cci_pmu);
907 908 909 910 911 912 913 914 915 916 917 918 919 920
	}
}

static u32 pmu_read_counter(struct perf_event *event)
{
	struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu);
	struct hw_perf_event *hw_counter = &event->hw;
	int idx = hw_counter->idx;
	u32 value;

	if (unlikely(!pmu_is_valid_counter(cci_pmu, idx))) {
		dev_err(&cci_pmu->plat_device->dev, "Invalid CCI PMU counter %d\n", idx);
		return 0;
	}
921
	value = pmu_read_register(cci_pmu, idx, CCI_PMU_CNTR);
922 923 924 925

	return value;
}

926
static void pmu_write_counter(struct cci_pmu *cci_pmu, u32 value, int idx)
927
{
928
	pmu_write_register(cci_pmu, value, idx, CCI_PMU_CNTR);
929 930
}

931
static void __pmu_write_counters(struct cci_pmu *cci_pmu, unsigned long *mask)
932 933 934 935 936 937 938 939 940
{
	int i;
	struct cci_pmu_hw_events *cci_hw = &cci_pmu->hw_events;

	for_each_set_bit(i, mask, cci_pmu->num_cntrs) {
		struct perf_event *event = cci_hw->events[i];

		if (WARN_ON(!event))
			continue;
941
		pmu_write_counter(cci_pmu, local64_read(&event->hw.prev_count), i);
942 943 944
	}
}

945 946 947 948 949 950 951 952
static void pmu_write_counters(struct cci_pmu *cci_pmu, unsigned long *mask)
{
	if (cci_pmu->model->write_counters)
		cci_pmu->model->write_counters(cci_pmu, mask);
	else
		__pmu_write_counters(cci_pmu, mask);
}

953
#ifdef CONFIG_ARM_CCI5xx_PMU
954 955

/*
956
 * CCI-500/CCI-550 has advanced power saving policies, which could gate the
957 958 959 960 961 962 963 964 965 966 967 968 969 970 971 972 973 974 975 976 977 978
 * clocks to the PMU counters, which makes the writes to them ineffective.
 * The only way to write to those counters is when the global counters
 * are enabled and the particular counter is enabled.
 *
 * So we do the following :
 *
 * 1) Disable all the PMU counters, saving their current state
 * 2) Enable the global PMU profiling, now that all counters are
 *    disabled.
 *
 * For each counter to be programmed, repeat steps 3-7:
 *
 * 3) Write an invalid event code to the event control register for the
      counter, so that the counters are not modified.
 * 4) Enable the counter control for the counter.
 * 5) Set the counter value
 * 6) Disable the counter
 * 7) Restore the event in the target counter
 *
 * 8) Disable the global PMU.
 * 9) Restore the status of the rest of the counters.
 *
979
 * We choose an event which for CCI-5xx is guaranteed not to count.
980 981
 * We use the highest possible event code (0x1f) for the master interface 0.
 */
982 983 984
#define CCI5xx_INVALID_EVENT	((CCI5xx_PORT_M0 << CCI5xx_PMU_EVENT_SOURCE_SHIFT) | \
				 (CCI5xx_PMU_EVENT_CODE_MASK << CCI5xx_PMU_EVENT_CODE_SHIFT))
static void cci5xx_pmu_write_counters(struct cci_pmu *cci_pmu, unsigned long *mask)
985 986 987 988 989 990 991 992 993 994 995 996 997 998 999 1000 1001 1002 1003
{
	int i;
	DECLARE_BITMAP(saved_mask, cci_pmu->num_cntrs);

	bitmap_zero(saved_mask, cci_pmu->num_cntrs);
	pmu_save_counters(cci_pmu, saved_mask);

	/*
	 * Now that all the counters are disabled, we can safely turn the PMU on,
	 * without syncing the status of the counters
	 */
	__cci_pmu_enable_nosync(cci_pmu);

	for_each_set_bit(i, mask, cci_pmu->num_cntrs) {
		struct perf_event *event = cci_pmu->hw_events.events[i];

		if (WARN_ON(!event))
			continue;

1004
		pmu_set_event(cci_pmu, i, CCI5xx_INVALID_EVENT);
1005 1006 1007 1008 1009 1010 1011 1012 1013 1014 1015
		pmu_enable_counter(cci_pmu, i);
		pmu_write_counter(cci_pmu, local64_read(&event->hw.prev_count), i);
		pmu_disable_counter(cci_pmu, i);
		pmu_set_event(cci_pmu, i, event->hw.config_base);
	}

	__cci_pmu_disable();

	pmu_restore_counters(cci_pmu, saved_mask);
}

1016
#endif	/* CONFIG_ARM_CCI5xx_PMU */
1017

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static u64 pmu_event_update(struct perf_event *event)
{
	struct hw_perf_event *hwc = &event->hw;
	u64 delta, prev_raw_count, new_raw_count;

	do {
		prev_raw_count = local64_read(&hwc->prev_count);
		new_raw_count = pmu_read_counter(event);
	} while (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
		 new_raw_count) != prev_raw_count);

	delta = (new_raw_count - prev_raw_count) & CCI_PMU_CNTR_MASK;

	local64_add(delta, &event->count);

	return new_raw_count;
}

static void pmu_read(struct perf_event *event)
{
	pmu_event_update(event);
}

1041
static void pmu_event_set_period(struct perf_event *event)
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{
	struct hw_perf_event *hwc = &event->hw;
	/*
	 * The CCI PMU counters have a period of 2^32. To account for the
	 * possiblity of extreme interrupt latency we program for a period of
	 * half that. Hopefully we can handle the interrupt before another 2^31
	 * events occur and the counter overtakes its previous value.
	 */
	u64 val = 1ULL << 31;
	local64_set(&hwc->prev_count, val);
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	/*
	 * CCI PMU uses PERF_HES_ARCH to keep track of the counters, whose
	 * values needs to be sync-ed with the s/w state before the PMU is
	 * enabled.
	 * Mark this counter for sync.
	 */
	hwc->state |= PERF_HES_ARCH;
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}

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static irqreturn_t pmu_handle_irq(int irq_num, void *dev)
{
	unsigned long flags;
1065
	struct cci_pmu *cci_pmu = dev;
1066
	struct cci_pmu_hw_events *events = &cci_pmu->hw_events;
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	int idx, handled = IRQ_NONE;

	raw_spin_lock_irqsave(&events->pmu_lock, flags);
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	/* Disable the PMU while we walk through the counters */
	__cci_pmu_disable();
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	/*
	 * Iterate over counters and update the corresponding perf events.
	 * This should work regardless of whether we have per-counter overflow
	 * interrupt or a combined overflow interrupt.
	 */
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	for (idx = 0; idx <= CCI_PMU_CNTR_LAST(cci_pmu); idx++) {
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		struct perf_event *event = events->events[idx];

		if (!event)
			continue;

		/* Did this counter overflow? */
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		if (!(pmu_read_register(cci_pmu, idx, CCI_PMU_OVRFLW) &
1086
		      CCI_PMU_OVRFLW_FLAG))
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			continue;

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		pmu_write_register(cci_pmu, CCI_PMU_OVRFLW_FLAG, idx,
							CCI_PMU_OVRFLW);
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		pmu_event_update(event);
		pmu_event_set_period(event);
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		handled = IRQ_HANDLED;
	}
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	/* Enable the PMU and sync possibly overflowed counters */
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	__cci_pmu_enable_sync(cci_pmu);
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	raw_spin_unlock_irqrestore(&events->pmu_lock, flags);

	return IRQ_RETVAL(handled);
}

1104
static int cci_pmu_get_hw(struct cci_pmu *cci_pmu)
1105
{
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	int ret = pmu_request_irq(cci_pmu, pmu_handle_irq);
	if (ret) {
		pmu_free_irq(cci_pmu);
		return ret;
	}
	return 0;
}
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static void cci_pmu_put_hw(struct cci_pmu *cci_pmu)
{
	pmu_free_irq(cci_pmu);
}
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static void hw_perf_event_destroy(struct perf_event *event)
{
	struct cci_pmu *cci_pmu = to_cci_pmu(event->pmu);
	atomic_t *active_events = &cci_pmu->active_events;
	struct mutex *reserve_mutex = &cci_pmu->reserve_mutex;

	if (atomic_dec_and_mutex_lock(active_events, reserve_mutex)) {
		cci_pmu_put_hw(cci_pmu);
		mutex_unlock(reserve_mutex);
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	}
}

1131
static void cci_pmu_enable(struct pmu *pmu)
1132
{
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	struct cci_pmu *cci_pmu = to_cci_pmu(pmu);
	struct cci_pmu_hw_events *hw_events = &cci_pmu->hw_events;
1135
	int enabled = bitmap_weight(hw_events->used_mask, cci_pmu->num_cntrs);
1136
	unsigned long flags;
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	if (!enabled)
		return;

	raw_spin_lock_irqsave(&hw_events->pmu_lock, flags);
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	__cci_pmu_enable_sync(cci_pmu);
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	raw_spin_unlock_irqrestore(