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    x86/boot/compressed/64: Prepare new top-level page table for trampoline · e9d0e633
    Kirill A. Shutemov authored
    
    
    If trampoline code would need to switch between 4- and 5-level paging
    modes, we have to use a page table in trampoline memory.
    
    Having it in trampoline memory guarantees that it's below 4G and we can
    point CR3 to it from 32-bit trampoline code.
    
    We only use the page table if the desired paging mode doesn't match the
    mode we are in. Otherwise the page table is unused and trampoline code
    wouldn't touch CR3.
    
    For 4- to 5-level paging transition, we set up current (4-level paging)
    CR3 as the first and the only entry in a new top-level page table.
    
    For 5- to 4-level paging transition, copy page table pointed by first
    entry in the current top-level page table as our new top-level page
    table.
    
    If the page table is used by trampoline we would need to copy it to new
    page table outside trampoline and update CR3 before restoring trampoline
    memory.
    
    Tested-by: default avatarBorislav Petkov <bp@suse.de>
    Signed-off-by: default avatarKirill A. Shutemov <kirill.shutemov@linux.intel.com>
    Cc: Andy Lutomirski <luto@amacapital.net>
    Cc: Andy Shevchenko <andy.shevchenko@gmail.com>
    Cc: Cyrill Gorcunov <gorcunov@openvz.org>
    Cc: Eric Biederman <ebiederm@xmission.com>
    Cc: H. Peter Anvin <hpa@zytor.com>
    Cc: Juergen Gross <jgross@suse.com>
    Cc: Kees Cook <keescook@chromium.org>
    Cc: Linus Torvalds <torvalds@linux-foundation.org>
    Cc: Matthew Wilcox <willy@infradead.org>
    Cc: Peter Zijlstra <peterz@infradead.org>
    Cc: Thomas Gleixner <tglx@linutronix.de>
    Cc: linux-mm@kvack.org
    Link: http://lkml.kernel.org/r/20180226180451.86788-6-kirill.shutemov@linux.intel.com
    
    
    Signed-off-by: default avatarIngo Molnar <mingo@kernel.org>
    e9d0e633