1. 24 Nov, 2015 2 commits
  2. 22 Oct, 2015 1 commit
    • Mark Rutland's avatar
      arm64: kvm: restore EL1N SP for panic · db85c55f
      Mark Rutland authored
      If we panic in hyp mode, we inject a call to panic() into the EL1N host
      kernel. If a guest context is active, we first attempt to restore the
      minimal amount of state necessary to execute the host kernel with
      However, the SP is restored as part of restore_common_regs, and so we
      may return to the host's panic() function with the SP of the guest. Any
      calculations based on the SP will be bogus, and any attempt to access
      the stack will result in recursive data aborts.
      When running Linux as a guest, the guest's EL1N SP is like to be some
      valid kernel address. In this case, the host kernel may use that region
      as a stack for panic(), corrupting it in the process.
      Avoid the problem by restoring the host SP prior to returning to the
      host. To prevent misleading backtraces in the host, the FP is zeroed at
      the same time. We don't need any of the other "common" registers in
      order to panic successfully.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Acked-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Cc: Christoffer Dall <christoffer.dall@linaro.org>
      Cc: <kvmarm@lists.cs.columbia.edu>
      Signed-off-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
  3. 17 Sep, 2015 2 commits
  4. 14 Sep, 2015 1 commit
    • Will Deacon's avatar
      KVM: arm64: add workaround for Cortex-A57 erratum #852523 · 43297dda
      Will Deacon authored
      When restoring the system register state for an AArch32 guest at EL2,
      writes to DACR32_EL2 may not be correctly synchronised by Cortex-A57,
      which can lead to the guest effectively running with junk in the DACR
      and running into unexpected domain faults.
      This patch works around the issue by re-ordering our restoration of the
      AArch32 register aliases so that they happen before the AArch64 system
      registers. Ensuring that the registers are restored in this order
      guarantees that they will be correctly synchronised by the core.
      Cc: <stable@vger.kernel.org>
      Reviewed-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
  5. 19 Aug, 2015 1 commit
  6. 27 Jul, 2015 1 commit
  7. 21 Jul, 2015 3 commits
    • Alex Bennée's avatar
      KVM: arm64: introduce vcpu->arch.debug_ptr · 84e690bf
      Alex Bennée authored
      This introduces a level of indirection for the debug registers. Instead
      of using the sys_regs[] directly we store registers in a structure in
      the vcpu. The new kvm_arm_reset_debug_ptr() sets the debug ptr to the
      guest context.
      Because we no longer give the sys_regs offset for the sys_reg_desc->reg
      field, but instead the index into a debug-specific struct we need to
      add a number of additional trap functions for each register. Also as the
      generic generic user-space access code no longer works we have
      introduced a new pair of function pointers to the sys_reg_desc structure
      to override the generic code when needed.
      Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      Signed-off-by: default avatarAlex Bennée <alex.bennee@linaro.org>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
    • Alex Bennée's avatar
      KVM: arm64: re-factor hyp.S debug register code · e0a1b9a9
      Alex Bennée authored
      This is a pre-cursor to sharing the code with the guest debug support.
      This replaces the big macro that fishes data out of a fixed location
      with a more general helper macro to restore a set of debug registers. It
      uses macro substitution so it can be re-used for debug control and value
      registers. It does however rely on the debug registers being 64 bit
      aligned (as they happen to be in the hyp ABI).
      Signed-off-by: default avatarAlex Bennée <alex.bennee@linaro.org>
      Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
    • Alex Bennée's avatar
      KVM: arm: introduce kvm_arm_init/setup/clear_debug · 56c7f5e7
      Alex Bennée authored
      This is a precursor for later patches which will need to do more to
      setup debug state before entering the hyp.S switch code. The existing
      functionality for setting mdcr_el2 has been moved out of hyp.S and now
      uses the value kept in vcpu->arch.mdcr_el2.
      As the assembler used to previously mask and preserve MDCR_EL2.HPMN I've
      had to add a mechanism to save the value of mdcr_el2 as a per-cpu
      variable during the initialisation code. The kernel never sets this
      number so we are assuming the bootcode has set up the correct value
      This also moves the conditional setting of the TDA bit from the hyp code
      into the C code which is currently used for the lazy debug register
      context switch code.
      Signed-off-by: default avatarAlex Bennée <alex.bennee@linaro.org>
      Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
  8. 17 Jun, 2015 1 commit
  9. 12 Jun, 2015 1 commit
  10. 16 Jan, 2015 1 commit
  11. 15 Jan, 2015 1 commit
    • Mark Rutland's avatar
      arm64: kvm: move to ESR_ELx macros · c6d01a94
      Mark Rutland authored
      Now that we have common ESR_ELx macros, make use of them in the arm64
      KVM code. The addition of <asm/esr.h> to the include path highlighted
      badly ordered (i.e. not alphabetical) include lists; these are changed
      to alphabetical order.
      There should be no functional change as a result of this patch.
      Signed-off-by: default avatarMark Rutland <mark.rutland@arm.com>
      Reviewed-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      Cc: Catalin Marinas <catalin.marinas@arm.com>
      Cc: Marc Zyngier <marc.zyngier@arm.com>
      Cc: Peter Maydell <peter.maydell@linaro.org>
      Cc: Will Deacon <will.deacon@arm.com>
  12. 12 Jan, 2015 1 commit
  13. 07 Nov, 2014 1 commit
  14. 11 Jul, 2014 7 commits
  15. 09 May, 2014 1 commit
  16. 27 Feb, 2014 1 commit
    • Marc Zyngier's avatar
      arm/arm64: KVM: detect CPU reset on CPU_PM_EXIT · b20c9f29
      Marc Zyngier authored
      Commit 1fcf7ce0
       (arm: kvm: implement CPU PM notifier) added
      support for CPU power-management, using a cpu_notifier to re-init
      KVM on a CPU that entered CPU idle.
      The code assumed that a CPU entering idle would actually be powered
      off, loosing its state entierely, and would then need to be
      reinitialized. It turns out that this is not always the case, and
      some HW performs CPU PM without actually killing the core. In this
      case, we try to reinitialize KVM while it is still live. It ends up
      badly, as reported by Andre Przywara (using a Calxeda Midway):
      [    3.663897] Kernel panic - not syncing: unexpected prefetch abort in Hyp mode at: 0x685760
      [    3.663897] unexpected data abort in Hyp mode at: 0xc067d150
      [    3.663897] unexpected HVC/SVC trap in Hyp mode at: 0xc0901dd0
      The trick here is to detect if we've been through a full re-init or
      not by looking at HVBAR (VBAR_EL2 on arm64). This involves
      implementing the backend for __hyp_get_vectors in the main KVM HYP
      code (rather small), and checking the return value against the
      default one when the CPU notifier is called on CPU_PM_EXIT.
      Reported-by: default avatarAndre Przywara <osp@andrep.de>
      Tested-by: default avatarAndre Przywara <osp@andrep.de>
      Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
      Cc: Rob Herring <rob.herring@linaro.org>
      Acked-by: default avatarChristoffer Dall <christoffer.dall@linaro.org>
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
  17. 06 Nov, 2013 1 commit
  18. 09 Aug, 2013 2 commits
    • Marc Zyngier's avatar
      arm64: KVM: add missing dsb before invalidating Stage-2 TLBs · f142e5ee
      Marc Zyngier authored
      When performing a Stage-2 TLB invalidation, it is necessary to
      make sure the write to the page tables is observable by all CPUs.
      For this purpose, add dsb instructions to __kvm_tlb_flush_vmid_ipa
      and __kvm_flush_vm_context before doing the TLB invalidation itself.
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
    • Marc Zyngier's avatar
      arm64: KVM: perform save/restore of PAR_EL1 · 1bbd8054
      Marc Zyngier authored
      Not saving PAR_EL1 is an unfortunate oversight. If the guest
      performs an AT* operation and gets scheduled out before reading
      the result of the translation from PAREL1, it could become
      corrupted by another guest or the host.
      Saving this register is made slightly more complicated as KVM also
      uses it on the permission fault handling path, leading to an ugly
      "stash and restore" sequence. Fortunately, this is already a slow
      path so we don't really care. Also, Linux doesn't do any AT*
      operation, so Linux guests are not impacted by this bug.
      Signed-off-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
  19. 12 Jun, 2013 4 commits