1. 04 Dec, 2018 11 commits
  2. 03 Dec, 2018 1 commit
  3. 30 Nov, 2018 1 commit
  4. 29 Nov, 2018 4 commits
  5. 28 Nov, 2018 1 commit
  6. 27 Nov, 2018 6 commits
  7. 26 Nov, 2018 8 commits
    • Jeenu Viswambharan's avatar
      docs: Add RAS framework documentation · 63eb2410
      Jeenu Viswambharan authored
      Change-Id: Ibf2b21b12ebc0af5815fc6643532a3be9100bf02
      Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
    • Joel Hutton's avatar
      Initial Spectre V1 mitigations (CVE-2017-5753). · 9edd8912
      Joel Hutton authored
      Initial Spectre Variant 1 mitigations (CVE-2017-5753).
      A potential speculative data leak was found in PSCI code, this depends
      on a non-robust implementation of the `plat_get_core_pos_by_mpidr()`
      function. This is considered very low-risk. This patch adds a macro to
      mitigate this. Note not all code paths could be analyzed with current
      Add a macro which makes a variable 'speculation safe', using the
       __builtin_speculation_safe_value function of GCC and llvm. This will be
      available in GCC 9, and is planned for llvm, but is not currently in
      mainline GCC or llvm. In order to implement this mitigation the compiler
      must support this builtin. Support is indicated by the
      The -mtrack-speculation option maintains a 'tracker' register, which
      determines if the processor is in false speculation at any point. This
      adds instructions and increases code size, but avoids the performance
      impact of a hard barrier.
      Without the -mtrack-speculation option, __builtin_speculation_safe_value
      expands to a
          DSB SY
      sequence after a conditional branch, before the
      speculation safe variable is used. With -mtrack-speculation a
          CSEL tracker, tracker, XZR, [cond];
          AND safeval,tracker;
      sequence is added instead, clearing the vulnerable variable by
      AND'ing it with the tracker register, which is zero during speculative
      execution. [cond] are the status flags which will only be true during
      speculative execution. For more information on
      __builtin_speculation_safe_value and the -mtrack-speculation option see
      The -mtracking option was not added, as the performance impact of the
      mitigation is low, and there is only one occurence.
      Change-Id: Ic9e66d1f4a5155e42e3e4055594974c230bfba3c
      Signed-off-by: default avatarJoel Hutton <Joel.Hutton@Arm.com>
    • Jeenu Viswambharan's avatar
      docs: Add Exception Handling Framework documentation · e31d76fd
      Jeenu Viswambharan authored
      Change-Id: I77d38758d18ba6dda1652b1b1e644fbfb14386cc
      Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
    • Jeenu Viswambharan's avatar
      SDEI: Unconditionally resume Secure if it was interrupted · 90a9213b
      Jeenu Viswambharan authored
      Secure world execution nearly always expect a controlled exit to
      Non-secure world. SDEI interrupts, although targets EL3, occur on behalf
      of Non-secure world, and may have higher priority than Secure world
      interrupts. Therefore they might preempt Secure execution, and yield
      execution to Non-secure SDEI handler. Upon completion of SDEI event
      handling (regardless of whether it's COPLETE or COMPLETE_AND_RESUME), we
      must resume Secure execution if it was preempted.
      Change-Id: I6edd991032588588427ba2fe6c3d7668f7080e3d
      Signed-off-by: default avatarJeenu Viswambharan <jeenu.viswambharan@arm.com>
    • Antonio Niño Díaz's avatar
      Merge pull request #1697 from antonio-nino-diaz-arm/an/arch · 85397ec4
      Antonio Niño Díaz authored
      Synchronise arch.h and arch_helpers.h with TF-A-Tests
    • Antonio Nino Diaz's avatar
      Synchronise arch.h and arch_helpers.h with TF-A-Tests · 932b3ae2
      Antonio Nino Diaz authored
      The headers forked at some point in the past and have diverged a lot. In
      order to make it easier to share code between TF-A-Tests and TF-A, this
      patch synchronises most of the definitions in the mentioned headers.
      This is not a complete sync, it has to be followed by more cleanup.
      This patch also removes the read helpers for the AArch32 instructions
      ats1cpr and ats1hr (they are write-only).
      Change-Id: Id13ecd7aeb83bd2318cd47156d71a42f1c9f6ba2
      Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
    • Haojian Zhuang's avatar
      hikey: remove delay after eMMC initialized · b79de2dc
      Haojian Zhuang authored
      commit 386b14bf64124ebf0368eab33ef07603e0c3138a
      Author: Haojian Zhuang <haojian.zhuang@linaro.org>
      Date:   Wed Nov 21 09:19:49 2018 +0800
          mmc: poll eMMC status after EXT_CSD command
          EXT_CSD command needs to access data from eMMC device. Add the
          operation of polling eMMC device status. Make sure the command is
      Signed-off-by: default avatarHaojian Zhuang <haojian.zhuang@linaro.org>
      A hacked delay time can't fit each eMMC device. Since the above commit
      enables the polling operation, remove the hacked delay time now.
      Signed-off-by: default avatarHaojian Zhuang <haojian.zhuang@linaro.org>
    • Haojian Zhuang's avatar
      mmc: poll eMMC status after EXT_CSD command · 93768644
      Haojian Zhuang authored
      EXT_CSD command needs to access data from eMMC device. Add the
      operation of polling eMMC device status. Make sure the command is
      Signed-off-by: default avatarHaojian Zhuang <haojian.zhuang@linaro.org>
  8. 23 Nov, 2018 4 commits
  9. 22 Nov, 2018 4 commits