Commit 29c02529 authored by Paul Beesley's avatar Paul Beesley

doc: Set correct syntax highlighting style

Several code blocks do not specify a language for syntax
highlighting. This results in Sphinx using a default highlighter
which is Python.

This patch adds the correct language to each code block that doesn't
already specify it.

Change-Id: Icce1949aabfdc11a334a42d49edf55fa673cddc3
Signed-off-by: default avatarPaul Beesley <paul.beesley@arm.com>
parent 8f62ca7b
......@@ -106,7 +106,7 @@ The environment variable ``CROSS_COMPILE`` must be set as per the user guide.
In the below example the usage of ROMLIB together with mbed TLS is demonstrated
to showcase the benefits of library at ROM - it's not mandatory.
::
.. code:: shell
make PLAT=fvp \
MBEDTLS_DIR=</path/to/mbedtls/> \
......
......@@ -224,7 +224,7 @@ activity, such as receiving a Secure interrupt or an exception.
The SDEI dispatcher implementation provides ``sdei_dispatch_event()`` API for
this purpose. The API has the following signature:
::
.. code:: c
int sdei_dispatch_event(int ev_num);
......
......@@ -130,7 +130,7 @@ First, build the Standalone MM Secure Partition. To build it, refer to the
Then build TF-A with SPM support and include the Standalone MM Secure Partition
image in the FIP:
::
.. code:: shell
BL32=path/to/standalone/mm/sp BL33=path/to/bl33.bin \
make PLAT=fvp ENABLE_SPM=1 ARM_BL31_IN_DRAM=1 fip all
......
......@@ -408,7 +408,7 @@ An IPL must provide functions with the following prototypes:
An IPL for each type must be registered using the following macro:
::
.. code:: c
REGISTER_IMG_PARSER_LIB(_type, _name, _init, _check_int, _get_param)
......
......@@ -2304,7 +2304,7 @@ result in build error. Subscribing to an undefined event however won't.
Subscribed handlers must be of type ``pubsub_cb_t``, with following function
signature:
::
.. code:: c
typedef void* (*pubsub_cb_t)(const void *arg);
......@@ -2331,7 +2331,7 @@ A publisher that wants to publish event ``foo`` would:
- Define the event ``foo`` in the ``pubsub_events.h``.
::
.. code:: c
REGISTER_PUBSUB_EVENT(foo);
......@@ -2467,7 +2467,7 @@ respectively.
From outside TF-A, timestamps for individual CPUs can be retrieved by calling
into ``pmf_smc_handler()``.
.. code:: c
::
Interface : pmf_smc_handler()
Argument : unsigned int smc_fid, u_register_t x1,
......@@ -2597,7 +2597,7 @@ Platform may choose to not define straight the toolchain target architecture
directive by defining ``MARCH32_DIRECTIVE``.
I.e:
::
.. code:: make
MARCH32_DIRECTIVE := -mach=armv7-a
......
......@@ -48,7 +48,7 @@ the exception level(s) it is handled in.
The following constants define the various interrupt types in the framework
implementation.
::
.. code:: c
#define INTR_TYPE_S_EL1 0
#define INTR_TYPE_EL3 1
......
......@@ -109,7 +109,7 @@ separately.
This tree is defined by the platform as the array described above as follows:
::
.. code:: c
#define PLAT_NUM_POWER_DOMAINS 20
#define PLATFORM_CORE_COUNT 13
......@@ -219,7 +219,7 @@ to represent leaf and non-leaf power domain nodes in the tree.
The power domain tree is implemented as a combination of the following data
structures.
::
.. code:: c
non_cpu_pd_node_t psci_non_cpu_pd_nodes[PSCI_NUM_NON_CPU_PWR_DOMAINS];
cpu_pd_node_t psci_cpu_pd_nodes[PLATFORM_CORE_COUNT];
......
......@@ -92,7 +92,7 @@ A runtime service is registered using the ``DECLARE_RT_SVC()`` macro, specifying
the name of the service, the range of OENs covered, the type of service and
initialization and call handler functions.
::
.. code:: c
#define DECLARE_RT_SVC(_name, _start, _end, _type, _setup, _smch)
......
This diff is collapsed.
......@@ -28,7 +28,7 @@ levels 0, 1 and 2 respectively. It does not support any retention states.
We used the upstream `TF master as of 31/01/2017`_, building the platform using
the ``ENABLE_RUNTIME_INSTRUMENTATION`` option:
::
.. code:: shell
make PLAT=juno ENABLE_RUNTIME_INSTRUMENTATION=1 \
SCP_BL2=<path/to/scp-fw.bin> \
......
......@@ -24,13 +24,13 @@ See the respective `U-Boot documentation`_ for more details.
To build for machines with an A64 or H5 SoC:
::
.. code:: shell
make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_a64 DEBUG=1 bl31
To build for machines with an H6 SoC:
::
.. code:: shell
make CROSS_COMPILE=aarch64-linux-gnu- PLAT=sun50i_h6 DEBUG=1 bl31
......
......@@ -15,7 +15,7 @@ and Linux:
In order to build it:
::
.. code:: shell
CROSS_COMPILE=aarch64-linux-gnu- make DEBUG=1 PLAT=gxbb bl31
......
......@@ -15,7 +15,7 @@ and Linux:
In order to build it:
::
.. code:: shell
CROSS_COMPILE=aarch64-linux-gnu- make DEBUG=1 PLAT=gxl
......
......@@ -33,13 +33,13 @@ is conveniently achieved with symlinks the local names as:
To build:
::
.. code:: shell
make CROSS_COMPILE=aarch64-none-elf- PLAT=qemu
To start (QEMU v2.6.0):
::
.. code:: shell
qemu-system-aarch64 -nographic -machine virt,secure=on -cpu cortex-a57 \
-kernel Image \
......
......@@ -292,7 +292,7 @@ of the size of an array is the same.
If ``MY_STRUCT_SIZE`` in the above example were wrong then the compiler would
emit an error like this:
.. code:: c
::
my_struct.h:10:1: error: size of array ‘assert_my_struct_size_mismatch’ is negative
......
......@@ -68,7 +68,7 @@ The vulnerability is mitigated by the following factors:
of the ``XN``, ``UXN`` or ``PXN`` bits in the translation tables. See the
``enable_mmu()`` function:
.. code:: c
::
sctlr = read_sctlr_el##_el(); \
sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT; \
......
......@@ -39,7 +39,7 @@ CPU context stored on the stack. This includes registers ``x0`` to ``x3``, as
can be seen in the ``lib/el3_runtime/aarch64/context.S`` file at line 339
(referring to the version of the code as of `commit c385955`_):
.. code:: c
::
/*
* This function restores all general purpose registers except x30 from the
......
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