Commit 3fa9dec4 authored by kenny liang's avatar kenny liang

Initialize platform for MediaTek mt8183

- Add basic platform setup
- Add generic CPU helper functions
- Add delay timer platform implementation
- Use TI 16550 uart driver

Change-Id: I1c29569c68fe9fca5e10e88a22a29690bab7141f
Signed-off-by: default avatarkenny liang <kenny.liang@mediatek.com>
parent f2f08465
Description
===========
MediaTek 8183 (MT8183) is a 64-bit ARM SoC introduced by MediaTek in early 2018.
The chip incorporates eight cores - four Cortex-A53 little cores and Cortex-A73.
Both clusters can operate at up to 2 GHz.
Boot Sequence
=============
::
Boot Rom --> Coreboot --> TF-A BL31 --> Depthcharge --> Linux Kernel
How to Build
============
.. code:: shell
make CROSS_COMPILE=aarch64-linux-gnu- PLAT=mt8183 DEBUG=1
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
#include <platform_def.h>
.globl plat_is_my_cpu_primary
.globl plat_my_core_pos
func plat_is_my_cpu_primary
mrs x0, mpidr_el1
and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
cmp x0, #PLAT_PRIMARY_CPU
cset x0, eq
ret
endfunc plat_is_my_cpu_primary
/* -----------------------------------------------------
* unsigned int plat_my_core_pos(void);
*
* result: CorePos = CoreId + (ClusterId << 2)
* -----------------------------------------------------
*/
func plat_my_core_pos
mrs x0, mpidr_el1
and x1, x0, #MPIDR_CPU_MASK
and x0, x0, #MPIDR_CLUSTER_MASK
add x0, x1, x0, LSR #6
ret
endfunc plat_my_core_pos
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch_helpers.h>
#include <common/bl_common.h>
#include <common/debug.h>
#include <platform_def.h>
#include <lib/utils.h>
#include <lib/xlat_tables/xlat_tables.h>
/* Table of regions to map using the MMU. */
const mmap_region_t plat_mmap[] = {
/* for TF text, RO, RW */
MAP_REGION_FLAT(TZRAM_BASE, TZRAM_SIZE,
MT_MEMORY | MT_RW | MT_SECURE),
MAP_REGION_FLAT(MTK_DEV_RNG0_BASE, MTK_DEV_RNG0_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(MTK_DEV_RNG1_BASE, MTK_DEV_RNG1_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(MTK_DEV_RNG2_BASE, MTK_DEV_RNG2_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
{ 0 }
};
/*******************************************************************************
* Macro generating the code for the function setting up the pagetables as per
* the platform memory map & initialize the mmu, for the given exception level
******************************************************************************/
void plat_configure_mmu_el3(uintptr_t total_base,
uintptr_t total_size,
uintptr_t ro_start,
uintptr_t ro_limit,
uintptr_t coh_start,
uintptr_t coh_limit)
{
mmap_add_region(total_base, total_base, total_size,
MT_MEMORY | MT_RW | MT_SECURE);
mmap_add_region(ro_start, ro_start, ro_limit - ro_start,
MT_MEMORY | MT_RO | MT_SECURE);
mmap_add_region(coh_start, coh_start, coh_limit - coh_start,
MT_DEVICE | MT_RW | MT_SECURE);
mmap_add(plat_mmap);
init_xlat_tables();
enable_mmu_el3(0);
}
unsigned int plat_get_syscnt_freq2(void)
{
return SYS_COUNTER_FREQ_IN_TICKS;
}
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <arch_helpers.h>
#include <common/bl_common.h>
#include <plat/common/common_def.h>
#include <drivers/console.h>
#include <common/debug.h>
#include <drivers/generic_delay_timer.h>
#include <mcucfg.h>
#include <lib/mmio.h>
#include <mtk_plat_common.h>
#include <plat_debug.h>
#include <plat_private.h>
#include <platform_def.h>
#include <scu.h>
#include <drivers/ti/uart/uart_16550.h>
static entry_point_info_t bl32_ep_info;
static entry_point_info_t bl33_ep_info;
static void platform_setup_cpu(void)
{
mmio_write_32((uintptr_t)&mt8183_mcucfg->mp0_rw_rsvd0, 0x00000001);
VERBOSE("addr of cci_adb400_dcm_config: 0x%x\n",
mmio_read_32((uintptr_t)&mt8183_mcucfg->cci_adb400_dcm_config));
VERBOSE("addr of sync_dcm_config: 0x%x\n",
mmio_read_32((uintptr_t)&mt8183_mcucfg->sync_dcm_config));
VERBOSE("mp0_spmc: 0x%x\n",
mmio_read_32((uintptr_t)&mt8183_mcucfg->mp0_cputop_spmc_ctl));
VERBOSE("mp1_spmc: 0x%x\n",
mmio_read_32((uintptr_t)&mt8183_mcucfg->mp1_cputop_spmc_ctl));
}
/*******************************************************************************
* Return a pointer to the 'entry_point_info' structure of the next image for
* the security state specified. BL33 corresponds to the non-secure image type
* while BL32 corresponds to the secure image type. A NULL pointer is returned
* if the image does not exist.
******************************************************************************/
entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
{
entry_point_info_t *next_image_info;
next_image_info = (type == NON_SECURE) ? &bl33_ep_info : &bl32_ep_info;
/* None of the images on this platform can have 0x0 as the entrypoint */
if (next_image_info->pc)
return next_image_info;
else
return NULL;
}
/*******************************************************************************
* Perform any BL31 early platform setup. Here is an opportunity to copy
* parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before they
* are lost (potentially). This needs to be done before the MMU is initialized
* so that the memory layout can be used while creating page tables.
* BL2 has flushed this information to memory, so we are guaranteed to pick up
* good data.
******************************************************************************/
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
struct mtk_bl31_params *arg_from_bl2 = (struct mtk_bl31_params *)arg0;
static console_16550_t console;
console_16550_register(UART0_BASE, UART_CLOCK, UART_BAUDRATE, &console);
NOTICE("MT8183 bl31_setup\n");
assert(arg_from_bl2 != NULL);
assert(arg_from_bl2->h.type == PARAM_BL31);
assert(arg_from_bl2->h.version >= VERSION_1);
bl32_ep_info = *arg_from_bl2->bl32_ep_info;
bl33_ep_info = *arg_from_bl2->bl33_ep_info;
}
/*******************************************************************************
* Perform any BL31 platform setup code
******************************************************************************/
void bl31_platform_setup(void)
{
platform_setup_cpu();
generic_delay_timer_init();
}
/*******************************************************************************
* Perform the very early platform specific architectural setup here. At the
* moment this is only intializes the mmu in a quick and dirty way.
******************************************************************************/
void bl31_plat_arch_setup(void)
{
enable_scu(read_mpidr());
plat_configure_mmu_el3(BL_CODE_BASE,
BL_COHERENT_RAM_END - BL_CODE_BASE,
BL_CODE_BASE,
BL_CODE_END,
BL_COHERENT_RAM_BASE,
BL_COHERENT_RAM_END);
}
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef MT8183_MCUCFG_H
#define MT8183_MCUCFG_H
#include <platform_def.h>
#include <stdint.h>
struct mt8183_mcucfg_regs {
uint32_t mp0_ca7l_cache_config; /* 0x0 */
struct {
uint32_t mem_delsel0;
uint32_t mem_delsel1;
} mp0_cpu[4]; /* 0x4 */
uint32_t mp0_cache_mem_delsel0; /* 0x24 */
uint32_t mp0_cache_mem_delsel1; /* 0x28 */
uint32_t mp0_axi_config; /* 0x2C */
uint32_t mp0_misc_config[10]; /* 0x30 */
uint32_t mp0_ca7l_cfg_dis; /* 0x58 */
uint32_t mp0_ca7l_clken_ctrl; /* 0x5C */
uint32_t mp0_ca7l_rst_ctrl; /* 0x60 */
uint32_t mp0_ca7l_misc_config; /* 0x64 */
uint32_t mp0_ca7l_dbg_pwr_ctrl; /* 0x68 */
uint32_t mp0_rw_rsvd0; /* 0x6C */
uint32_t mp0_rw_rsvd1; /* 0x70 */
uint32_t mp0_ro_rsvd; /* 0x74 */
uint32_t reserved0_0[98]; /* 0x78 */
uint32_t mp1_ca7l_cache_config; /* 0x200 */
uint32_t mp1_miscdbg; /* 0x204 */
uint32_t reserved0_1[9]; /* 0x208 */
uint32_t mp1_axi_config; /* 0x22C */
uint32_t mp1_misc_config[10]; /* 0x230 */
uint32_t reserved0_2[3]; /* 0x258 */
uint32_t mp1_ca7l_misc_config; /* 0x264 */
uint32_t reserved0_3[310]; /* 0x268 */
uint32_t cci_adb400_dcm_config; /* 0x740 */
uint32_t sync_dcm_config; /* 0x744 */
uint32_t reserved0_4[16]; /* 0x748 */
uint32_t mp0_cputop_spmc_ctl; /* 0x788 */
uint32_t mp1_cputop_spmc_ctl; /* 0x78C */
uint32_t mp1_cputop_spmc_sram_ctl; /* 0x790 */
uint32_t reserved0_5[23]; /* 0x794 */
uint32_t l2_cfg_mp0; /* 0x7F0 */
uint32_t l2_cfg_mp1; /* 0x7F4 */
uint32_t reserved0_6[1282]; /* 0x7F8 */
uint32_t cpusys0_sparkvretcntrl; /* 0x1C00 */
uint32_t cpusys0_sparken; /* 0x1C04 */
uint32_t cpusys0_amuxsel; /* 0x1C08 */
uint32_t reserved0_7[9]; /* 0x1C0C */
uint32_t cpusys0_cpu0_spmc_ctl; /* 0x1C30 */
uint32_t cpusys0_cpu1_spmc_ctl; /* 0x1C34 */
uint32_t cpusys0_cpu2_spmc_ctl; /* 0x1C38 */
uint32_t cpusys0_cpu3_spmc_ctl; /* 0x1C3C */
uint32_t reserved0_8[370]; /* 0x1C40 */
uint32_t mp2_cpucfg; /* 0x2208 */
uint32_t mp2_axi_config; /* 0x220C */
uint32_t reserved0_9[36]; /* 0x2210 */
uint32_t mp2_cputop_spm_ctl; /* 0x22A0 */
uint32_t mp2_cputop_spm_sta; /* 0x22A4 */
uint32_t reserved0_10[98]; /* 0x22A8 */
uint32_t cpusys2_cpu0_spmc_ctl; /* 0x2430 */
uint32_t cpusys2_cpu0_spmc_sta; /* 0x2434 */
uint32_t cpusys2_cpu1_spmc_ctl; /* 0x2438 */
uint32_t cpusys2_cpu1_spmc_sta; /* 0x243C */
uint32_t reserved0_11[176]; /* 0x2440 */
uint32_t spark2ld0; /* 0x2700 */
uint32_t reserved0_12[1355]; /* 0x2704 */
uint32_t cpusys1_cpu0_spmc_ctl; /* 0x3C30 */
uint32_t cpusys1_cpu1_spmc_ctl; /* 0x3C34 */
uint32_t cpusys1_cpu2_spmc_ctl; /* 0x3C38 */
uint32_t cpusys1_cpu3_spmc_ctl; /* 0x3C3C */
};
static struct mt8183_mcucfg_regs *const mt8183_mcucfg = (void *)MCUCFG_BASE;
enum {
SW_SPARK_EN = 1 << 0,
SW_NO_WAIT_FOR_Q_CHANNEL = 1 << 1,
SW_FSM_OVERRIDE = 1 << 2,
SW_LOGIC_PRE1_PDB = 1 << 3,
SW_LOGIC_PRE2_PDB = 1 << 4,
SW_LOGIC_PDB = 1 << 5,
SW_ISO = 1 << 6,
SW_SRAM_SLEEPB = 0x3f << 7,
SW_SRAM_ISOINTB = 1 << 13,
SW_CLK_DIS = 1 << 14,
SW_CKISO = 1 << 15,
SW_PD = 0x3f << 16,
SW_HOT_PLUG_RESET = 1 << 22,
SW_PWR_ON_OVERRIDE_EN = 1 << 23,
SW_PWR_ON = 1 << 24,
SW_COQ_DIS = 1 << 25,
LOGIC_PDBO_ALL_OFF_ACK = 1 << 26,
LOGIC_PDBO_ALL_ON_ACK = 1 << 27,
LOGIC_PRE2_PDBO_ALL_ON_ACK = 1 << 28,
LOGIC_PRE1_PDBO_ALL_ON_ACK = 1 << 29
};
enum {
CPU_SW_SPARK_EN = 1 << 0,
CPU_SW_NO_WAIT_FOR_Q_CHANNEL = 1 << 1,
CPU_SW_FSM_OVERRIDE = 1 << 2,
CPU_SW_LOGIC_PRE1_PDB = 1 << 3,
CPU_SW_LOGIC_PRE2_PDB = 1 << 4,
CPU_SW_LOGIC_PDB = 1 << 5,
CPU_SW_ISO = 1 << 6,
CPU_SW_SRAM_SLEEPB = 1 << 7,
CPU_SW_SRAM_ISOINTB = 1 << 8,
CPU_SW_CLK_DIS = 1 << 9,
CPU_SW_CKISO = 1 << 10,
CPU_SW_PD = 0x1f << 11,
CPU_SW_HOT_PLUG_RESET = 1 << 16,
CPU_SW_POWR_ON_OVERRIDE_EN = 1 << 17,
CPU_SW_PWR_ON = 1 << 18,
CPU_SPARK2LDO_ALLSWOFF = 1 << 19,
CPU_PDBO_ALL_ON_ACK = 1 << 20,
CPU_PRE2_PDBO_ALLON_ACK = 1 << 21,
CPU_PRE1_PDBO_ALLON_ACK = 1 << 22
};
enum {
MP2_AXI_CONFIG_ACINACTM = 1 << 0,
MPx_AXI_CONFIG_ACINACTM = 1 << 4,
MPX_CA7_MISC_CONFIG_STANDBYWFIL2 = 1 << 28
};
enum {
MP0_CPU0_STANDBYWFE = 1 << 20,
MP0_CPU1_STANDBYWFE = 1 << 21,
MP0_CPU2_STANDBYWFE = 1 << 22,
MP0_CPU3_STANDBYWFE = 1 << 23
};
enum {
MP1_CPU0_STANDBYWFE = 1 << 20,
MP1_CPU1_STANDBYWFE = 1 << 21,
MP1_CPU2_STANDBYWFE = 1 << 22,
MP1_CPU3_STANDBYWFE = 1 << 23
};
enum {
B_SW_HOT_PLUG_RESET = 1 << 30,
B_SW_PD_OFFSET = 18,
B_SW_PD = 0x3f << B_SW_PD_OFFSET,
B_SW_SRAM_SLEEPB_OFFSET = 12,
B_SW_SRAM_SLEEPB = 0x3f << B_SW_SRAM_SLEEPB_OFFSET
};
enum {
B_SW_SRAM_ISOINTB = 1 << 9,
B_SW_ISO = 1 << 8,
B_SW_LOGIC_PDB = 1 << 7,
B_SW_LOGIC_PRE2_PDB = 1 << 6,
B_SW_LOGIC_PRE1_PDB = 1 << 5,
B_SW_FSM_OVERRIDE = 1 << 4,
B_SW_PWR_ON = 1 << 3,
B_SW_PWR_ON_OVERRIDE_EN = 1 << 2
};
enum {
B_FSM_STATE_OUT_OFFSET = 6,
B_FSM_STATE_OUT_MASK = 0x1f << B_FSM_STATE_OUT_OFFSET,
B_SW_LOGIC_PDBO_ALL_OFF_ACK = 1 << 5,
B_SW_LOGIC_PDBO_ALL_ON_ACK = 1 << 4,
B_SW_LOGIC_PRE2_PDBO_ALL_ON_ACK = 1 << 3,
B_SW_LOGIC_PRE1_PDBO_ALL_ON_ACK = 1 << 2,
B_FSM_OFF = 0 << B_FSM_STATE_OUT_OFFSET,
B_FSM_ON = 1 << B_FSM_STATE_OUT_OFFSET,
B_FSM_RET = 2 << B_FSM_STATE_OUT_OFFSET
};
/* APB Module infracfg_ao */
enum {
INFRA_TOPAXI_PROTECTEN_1 = INFRACFG_AO_BASE + 0x250,
INFRA_TOPAXI_PROTECTSTA1_1 = INFRACFG_AO_BASE + 0x258,
INFRA_TOPAXI_PROTECTEN_1_SET = INFRACFG_AO_BASE + 0x2A8,
INFRA_TOPAXI_PROTECTEN_1_CLR = INFRACFG_AO_BASE + 0x2AC
};
enum {
IDX_PROTECT_MP0_CACTIVE = 10,
IDX_PROTECT_MP1_CACTIVE = 11,
IDX_PROTECT_ICC0_CACTIVE = 12,
IDX_PROTECT_ICD0_CACTIVE = 13,
IDX_PROTECT_ICC1_CACTIVE = 14,
IDX_PROTECT_ICD1_CACTIVE = 15,
IDX_PROTECT_L2C0_CACTIVE = 26,
IDX_PROTECT_L2C1_CACTIVE = 27
};
/* cpu boot mode */
enum {
MP0_CPUCFG_64BIT_SHIFT = 12,
MP1_CPUCFG_64BIT_SHIFT = 28,
MP0_CPUCFG_64BIT = 0xf << MP0_CPUCFG_64BIT_SHIFT,
MP1_CPUCFG_64BIT = 0xf << MP1_CPUCFG_64BIT_SHIFT
};
/* scu related */
enum {
MP0_ACINACTM_SHIFT = 4,
MP1_ACINACTM_SHIFT = 4,
MP2_ACINACTM_SHIFT = 0,
MP0_ACINACTM = 1 << MP0_ACINACTM_SHIFT,
MP1_ACINACTM = 1 << MP1_ACINACTM_SHIFT,
MP2_ACINACTM = 1 << MP2_ACINACTM_SHIFT
};
enum {
MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT = 0,
MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT = 4,
MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT = 8,
MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT = 12,
MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT = 16,
MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK =
0xf << MP1_DIS_RGU0_WAIT_PD_CPUS_L1_ACK_SHIFT,
MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK =
0xf << MP1_DIS_RGU1_WAIT_PD_CPUS_L1_ACK_SHIFT,
MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK =
0xf << MP1_DIS_RGU2_WAIT_PD_CPUS_L1_ACK_SHIFT,
MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK =
0xf << MP1_DIS_RGU3_WAIT_PD_CPUS_L1_ACK_SHIFT,
MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK =
0xf << MP1_DIS_RGU_NOCPU_WAIT_PD_CPUS_L1_ACK_SHIFT
};
enum {
MP1_AINACTS_SHIFT = 4,
MP1_AINACTS = 1 << MP1_AINACTS_SHIFT
};
enum {
MP1_SW_CG_GEN_SHIFT = 12,
MP1_SW_CG_GEN = 1 << MP1_SW_CG_GEN_SHIFT
};
enum {
MP1_L2RSTDISABLE_SHIFT = 14,
MP1_L2RSTDISABLE = 1 << MP1_L2RSTDISABLE_SHIFT
};
#endif /* MT8183_MCUCFG_H */
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PLATFORM_DEBUG_H
#define PLATFORM_DEBUG_H
#define sync_writel(addr, val) \
do { mmio_write_32((addr), (val)); dsbsy(); } while (0)
#define MCU_BIU_BASE 0x0c530000
#define MISC1_CFG_BASE 0xb00
#define CA15M_CFG_BASE 0x2000
#define DFD_INTERNAL_CTL (MCU_BIU_BASE + MISC1_CFG_BASE + 0x00)
#define CA15M_DBG_CONTROL (MCU_BIU_BASE + CA15M_CFG_BASE + 0x728)
#define CA15M_PWR_RST_CTL (MCU_BIU_BASE + CA15M_CFG_BASE + 0x08)
#define VPROC_EXT_CTL 0x10006290
#define CFG_SF_CTRL 0x0c510014
#define CFG_SF_INI 0x0c510010
#define BIT_CA15M_L2PARITY_EN (1 << 1)
#define BIT_CA15M_LASTPC_DIS (1 << 8)
#define MP1_CPUTOP_PWR_CON 0x10006218
#define MCU_ALL_PWR_ON_CTRL 0x0c530b58
#define PLAT_MTK_CIRCULAR_BUFFER_UNLOCK 0xefab4133
#define PLAT_MTK_CIRCULAR_BUFFER_LOCK 0xefab4134
extern void circular_buffer_setup(void);
extern void l2c_parity_check_setup(void);
extern void clear_all_on_mux(void);
#endif /* PLATFORM_DEBUG_H */
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <drivers/arm/cci.h>
#include <drivers/arm/gic_common.h>
#include <drivers/arm/gicv2.h>
#include <platform_def.h>
.section .rodata.gic_reg_name, "aS"
gicc_regs:
.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
gicd_pend_reg:
.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n" \
" Offset:\t\t\tvalue\n"
newline:
.asciz "\n"
spacer:
.asciz ":\t\t0x"
.section .rodata.cci_reg_name, "aS"
cci_iface_regs:
.asciz "cci_snoop_ctrl_cluster0", "cci_snoop_ctrl_cluster1" , ""
/* ---------------------------------------------
* The below macro prints out relevant GIC and
* CCI registers whenever an unhandled exception
* is taken in BL31.
* Clobbers: x0 - x10, x26, x27, sp
* ---------------------------------------------
*/
.macro plat_crash_print_regs
mov_imm x26, BASE_GICD_BASE
mov_imm x27, BASE_GICC_BASE
/* Load the gicc reg list to x6 */
adr x6, gicc_regs
/* Load the gicc regs to gp regs used by str_in_crash_buf_print */
ldr w8, [x27, #GICC_HPPIR]
ldr w9, [x27, #GICC_AHPPIR]
ldr w10, [x27, #GICC_CTLR]
/* Store to the crash buf and print to console */
bl str_in_crash_buf_print
/* Print the GICD_ISPENDR regs */
add x7, x26, #GICD_ISPENDR
adr x4, gicd_pend_reg
bl asm_print_str
gicd_ispendr_loop:
sub x4, x7, x26
cmp x4, #0x280
b.eq exit_print_gic_regs
bl asm_print_hex
adr x4, spacer
bl asm_print_str
ldr x4, [x7], #8
bl asm_print_hex
adr x4, newline
bl asm_print_str
b gicd_ispendr_loop
exit_print_gic_regs:
adr x6, cci_iface_regs
/* Store in x7 the base address of the first interface */
mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \
PLAT_MT_CCI_CLUSTER0_SL_IFACE_IX))
ldr w8, [x7, #SNOOP_CTRL_REG]
/* Store in x7 the base address of the second interface */
mov_imm x7, (PLAT_MT_CCI_BASE + SLAVE_IFACE_OFFSET( \
PLAT_MT_CCI_CLUSTER1_SL_IFACE_IX))
ldr w9, [x7, #SNOOP_CTRL_REG]
/* Store to the crash buf and print to console */
bl str_in_crash_buf_print
.endm
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PLAT_PRIVATE_H
#define PLAT_PRIVATE_H
/*******************************************************************************
* Function and variable prototypes
******************************************************************************/
void plat_configure_mmu_el3(uintptr_t total_base,
uintptr_t total_size,
uintptr_t ro_start,
uintptr_t ro_limit,
uintptr_t coh_start,
uintptr_t coh_limit);
void plat_cci_init(void);
void plat_cci_enable(void);
void plat_cci_disable(void);
void plat_cci_init_sf(void);
void plat_gic_init(void);
/* Declarations for plat_topology.c */
int mt_setup_topology(void);
#endif /* PLAT_PRIVATE_H */
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/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef POWER_TRACER_H
#define POWER_TRACER_H
#define CPU_UP 0
#define CPU_DOWN 1
#define CPU_SUSPEND 2
#define CLUSTER_UP 3
#define CLUSTER_DOWN 4
#define CLUSTER_SUSPEND 5
void trace_power_flow(u_register_t mpidr, unsigned char mode);
#endif /* POWER_TRACER_H */
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SCU_H
#define SCU_H
void disable_scu(u_register_t mpidr);
void enable_scu(u_register_t mpidr);
#endif /* SCU_H */
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch_helpers.h>
#include <common/debug.h>
#include <lib/mmio.h>
#include <plat_debug.h>
#include <platform_def.h>
void circular_buffer_setup(void)
{
/* Clear DBG_CONTROL.lastpc_disable to enable circular buffer */
sync_writel(CA15M_DBG_CONTROL,
mmio_read_32(CA15M_DBG_CONTROL) & ~(BIT_CA15M_LASTPC_DIS));
}
void circular_buffer_unlock(void)
{
unsigned int i;
/* Disable big vproc external off (set CPU_EXT_BUCK_ISO to 0x0) */
sync_writel(VPROC_EXT_CTL, mmio_read_32(VPROC_EXT_CTL) & ~(0x1 << 1));
/* Release vproc apb mask (set 0x0C53_2008[1] to 0x0) */
sync_writel(CA15M_PWR_RST_CTL, mmio_read_32(CA15M_PWR_RST_CTL) & ~(0x1 << 1));
for (i = 1; i <= 4; ++i)
sync_writel(MP1_CPUTOP_PWR_CON + i * 4,
(mmio_read_32(MP1_CPUTOP_PWR_CON + i * 4) & ~(0x4))|(0x4));
/* Set DFD.en */
sync_writel(DFD_INTERNAL_CTL, 0x1);
}
void circular_buffer_lock(void)
{
/* Clear DFD.en */
sync_writel(DFD_INTERNAL_CTL, 0x0);
}
void clear_all_on_mux(void)
{
sync_writel(MCU_ALL_PWR_ON_CTRL,
mmio_read_32(MCU_ALL_PWR_ON_CTRL) & ~(1 << 2));
sync_writel(MCU_ALL_PWR_ON_CTRL,
mmio_read_32(MCU_ALL_PWR_ON_CTRL) & ~(1 << 1));
}
void l2c_parity_check_setup(void)
{
/* Enable DBG_CONTROL.l2parity_en */
sync_writel(CA15M_DBG_CONTROL,
mmio_read_32(CA15M_DBG_CONTROL) | BIT_CA15M_L2PARITY_EN);
}
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
/* common headers */
#include <arch_helpers.h>
#include <assert.h>
#include <common/debug.h>
#include <lib/mmio.h>
#include <lib/psci/psci.h>
#include <errno.h>
/* mediatek platform specific headers */
#include <platform_def.h>
#include <scu.h>
#include <mtk_plat_common.h>
#include <power_tracer.h>
#include <plat_private.h>
/*******************************************************************************
* MTK_platform handler called when an affinity instance is about to be turned
* on. The level and mpidr determine the affinity instance.