Commit 46f9b2c3 authored by Peng Fan's avatar Peng Fan Committed by Bai Ping

drivers: add tzc380 support

Add tzc380 support.
Signed-off-by: default avatarPeng Fan <peng.fan@nxp.com>
Signed-off-by: default avatarBai Ping <ping.bai@nxp.com>
parent 37e8ab53
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <debug.h>
#include <mmio.h>
#include <stddef.h>
#include <tzc380.h>
struct tzc380_instance {
uintptr_t base;
uint8_t addr_width;
uint8_t num_regions;
};
struct tzc380_instance tzc380;
static unsigned int tzc380_read_build_config(uintptr_t base)
{
return mmio_read_32(base + TZC380_CONFIGURATION_OFF);
}
static void tzc380_write_action(uintptr_t base, tzc_action_t action)
{
mmio_write_32(base + ACTION_OFF, action);
}
static void tzc380_write_region_base_low(uintptr_t base, unsigned int region,
unsigned int val)
{
mmio_write_32(base + REGION_SETUP_LOW_OFF(region), val);
}
static void tzc380_write_region_base_high(uintptr_t base, unsigned int region,
unsigned int val)
{
mmio_write_32(base + REGION_SETUP_HIGH_OFF(region), val);
}
static void tzc380_write_region_attributes(uintptr_t base, unsigned int region,
unsigned int val)
{
mmio_write_32(base + REGION_ATTRIBUTES_OFF(region), val);
}
void tzc380_init(uintptr_t base)
{
unsigned int tzc_build;
assert(base != NULL);
tzc380.base = base;
/* Save values we will use later. */
tzc_build = tzc380_read_build_config(tzc380.base);
tzc380.addr_width = ((tzc_build >> BUILD_CONFIG_AW_SHIFT) &
BUILD_CONFIG_AW_MASK) + 1;
tzc380.num_regions = ((tzc_build >> BUILD_CONFIG_NR_SHIFT) &
BUILD_CONFIG_NR_MASK) + 1;
}
static uint32_t addr_low(uintptr_t addr)
{
return (uint32_t)addr;
}
static uint32_t addr_high(uintptr_t addr __unused)
{
#if (UINTPTR_MAX == UINT64_MAX)
return addr >> 32;
#else
return 0;
#endif
}
/*
* `tzc380_configure_region` is used to program regions into the TrustZone
* controller.
*/
void tzc380_configure_region(uint8_t region, uintptr_t region_base, unsigned int attr)
{
assert(tzc380.base != NULL);
assert(region < tzc380.num_regions);
tzc380_write_region_base_low(tzc380.base, region, addr_low(region_base));
tzc380_write_region_base_high(tzc380.base, region, addr_high(region_base));
tzc380_write_region_attributes(tzc380.base, region, attr);
}
void tzc380_set_action(tzc_action_t action)
{
assert(tzc380.base != NULL);
/*
* - Currently no handler is provided to trap an error via interrupt
* or exception.
* - The interrupt action has not been tested.
*/
tzc380_write_action(tzc380.base, action);
}
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef TZC380_H
#define TZC380_H
#include <tzc_common.h>
#include <utils_def.h>
#define TZC380_CONFIGURATION_OFF U(0x000)
#define ACTION_OFF U(0x004)
#define LOCKDOWN_RANGE_OFF U(0x008)
#define LOCKDOWN_SELECT_OFF U(0x00C)
#define INT_STATUS U(0x010)
#define INT_CLEAR U(0x014)
#define FAIL_ADDRESS_LOW_OFF U(0x020)
#define FAIL_ADDRESS_HIGH_OFF U(0x024)
#define FAIL_CONTROL_OFF U(0x028)
#define FAIL_ID U(0x02c)
#define SPECULATION_CTRL_OFF U(0x030)
#define SECURITY_INV_EN_OFF U(0x034)
#define REGION_SETUP_LOW_OFF(n) U(0x100 + (n) * 0x10)
#define REGION_SETUP_HIGH_OFF(n) U(0x104 + (n) * 0x10)
#define REGION_ATTRIBUTES_OFF(n) U(0x108 + (n) * 0x10)
#define BUILD_CONFIG_AW_SHIFT 8
#define BUILD_CONFIG_AW_MASK U(0x3f)
#define BUILD_CONFIG_NR_SHIFT 0
#define BUILD_CONFIG_NR_MASK U(0xf)
#define ACTION_RV_SHIFT 0
#define ACTION_RV_MASK U(0x3)
#define ACTION_RV_LOWOK U(0x0)
#define ACTION_RV_LOWERR U(0x1)
#define ACTION_RV_HIGHOK U(0x2)
#define ACTION_RV_HIGHERR U(0x3)
/* Speculation is enabled by default. */
#define SPECULATION_CTRL_WRITE_DISABLE BIT_32(1)
#define SPECULATION_CTRL_READ_DISABLE BIT_32(0)
#define INT_STATUS_OVERRUN_SHIFT 1
#define INT_STATUS_OVERRUN_MASK U(0x1)
#define INT_STATUS_STATUS_SHIFT 0
#define INT_STATUS_STATUS_MASK U(0x1)
#define INT_CLEAR_CLEAR_SHIFT 0
#define INT_CLEAR_CLEAR_MASK U(0x1)
#define TZC380_COMPONENT_ID U(0xb105f00d)
#define TZC380_PERIPH_ID_LOW U(0x001bb380)
#define TZC380_PERIPH_ID_HIGH U(0x00000004)
#define TZC_SP_NS_W BIT_32(0)
#define TZC_SP_NS_R BIT_32(1)
#define TZC_SP_S_W BIT_32(2)
#define TZC_SP_S_R BIT_32(3)
#define TZC_ATTR_SP_SHIFT 28
#define TZC_ATTR_SP_ALL ((TZC_SP_S_W | TZC_SP_S_R | TZC_SP_NS_W | \
TZC_SP_NS_R) << TZC_ATTR_SP_SHIFT)
#define TZC_ATTR_SP_S_RW ((TZC_SP_S_W | TZC_SP_S_R) << \
TZC_ATTR_SP_SHIFT)
#define TZC_ATTR_SP_NS_RW ((TZC_SP_NS_W | TZC_SP_NS_R) << \
TZC_ATTR_SP_SHIFT)
#define TZC_REGION_SIZE_32K U(0xe)
#define TZC_REGION_SIZE_64K U(0xf)
#define TZC_REGION_SIZE_128K U(0x10)
#define TZC_REGION_SIZE_256K U(0x11)
#define TZC_REGION_SIZE_512K U(0x12)
#define TZC_REGION_SIZE_1M U(0x13)
#define TZC_REGION_SIZE_2M U(0x14)
#define TZC_REGION_SIZE_4M U(0x15)
#define TZC_REGION_SIZE_8M U(0x16)
#define TZC_REGION_SIZE_16M U(0x17)
#define TZC_REGION_SIZE_32M U(0x18)
#define TZC_REGION_SIZE_64M U(0x19)
#define TZC_REGION_SIZE_128M U(0x1a)
#define TZC_REGION_SIZE_256M U(0x1b)
#define TZC_REGION_SIZE_512M U(0x1c)
#define TZC_REGION_SIZE_1G U(0x1d)
#define TZC_REGION_SIZE_2G U(0x1e)
#define TZC_REGION_SIZE_4G U(0x1f)
#define TZC_REGION_SIZE_8G U(0x20)
#define TZC_REGION_SIZE_16G U(0x21)
#define TZC_REGION_SIZE_32G U(0x22)
#define TZC_REGION_SIZE_64G U(0x23)
#define TZC_REGION_SIZE_128G U(0x24)
#define TZC_REGION_SIZE_256G U(0x25)
#define TZC_REGION_SIZE_512G U(0x26)
#define TZC_REGION_SIZE_1T U(0x27)
#define TZC_REGION_SIZE_2T U(0x28)
#define TZC_REGION_SIZE_4T U(0x29)
#define TZC_REGION_SIZE_8T U(0x2a)
#define TZC_REGION_SIZE_16T U(0x2b)
#define TZC_REGION_SIZE_32T U(0x2c)
#define TZC_REGION_SIZE_64T U(0x2d)
#define TZC_REGION_SIZE_128T U(0x2e)
#define TZC_REGION_SIZE_256T U(0x2f)
#define TZC_REGION_SIZE_512T U(0x30)
#define TZC_REGION_SIZE_1P U(0x31)
#define TZC_REGION_SIZE_2P U(0x32)
#define TZC_REGION_SIZE_4P U(0x33)
#define TZC_REGION_SIZE_8P U(0x34)
#define TZC_REGION_SIZE_16P U(0x35)
#define TZC_REGION_SIZE_32P U(0x36)
#define TZC_REGION_SIZE_64P U(0x37)
#define TZC_REGION_SIZE_128P U(0x38)
#define TZC_REGION_SIZE_256P U(0x39)
#define TZC_REGION_SIZE_512P U(0x3a)
#define TZC_REGION_SIZE_1E U(0x3b)
#define TZC_REGION_SIZE_2E U(0x3c)
#define TZC_REGION_SIZE_4E U(0x3d)
#define TZC_REGION_SIZE_8E U(0x3e)
#define TZC_REGION_SIZE_16E U(0x3f)
#define TZC_REGION_SIZE_SHIFT 0x1
#define TZC_REGION_SIZE_MASK U(0x7e)
#define TZC_ATTR_REGION_SIZE(s) ((s) << TZC_REGION_SIZE_SHIFT)
#define TZC_ATTR_REGION_EN_SHIFT 0x0
#define TZC_ATTR_REGION_EN_MASK U(0x1)
#define TZC_ATTR_REGION_EN
#define TZC_ATTR_REGION_ENABLE U(0x1)
#define TZC_ATTR_REGION_DISABLE U(0x0)
#define REGION_MAX 16
void tzc380_init(uintptr_t base);
void tzc380_configure_region(uint8_t region,
uintptr_t region_base,
unsigned int attr);
void tzc380_set_action(tzc_action_t action);
static inline void tzc_init(uintptr_t base)
{
tzc380_init(base);
}
static inline void tzc_configure_region(uint8_t region,
uintptr_t region_base,
unsigned int attr)
{
tzc380_configure_region(region, region_base, attr);
}
static inline void tzc_set_action(tzc_action_t action)
{
tzc380_set_action(action);
}
#endif /* TZC380_H */
......@@ -7,8 +7,6 @@
#ifndef SOC_TZASC_H
#define SOC_TZASC_H
#include "tzc380.h"
#define MAX_NUM_TZC_REGION 3
/* TZASC related constants */
......@@ -58,6 +56,15 @@
#define CCI_TERMINATE_BARRIER_TX 0x8
#define CONFIG_SYS_FSL_TZASC_ADDR 0x1500000
struct tzc380_reg {
unsigned int secure;
unsigned int enabled;
unsigned int low_addr;
unsigned int high_addr;
unsigned int size;
unsigned int sub_mask;
};
/* List of MAX_NUM_TZC_REGION TZC regions' boundaries and configurations. */
static const struct tzc380_reg tzc380_reg_list[] = {
......
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef TZC380_H
#define TZC380_H
struct tzc380_reg {
unsigned int secure;
unsigned int enabled;
unsigned int low_addr;
unsigned int high_addr;
unsigned int size;
unsigned int sub_mask;
};
#endif /* TZC380_H */
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