Commit 7e532c4b authored by Jorge Ramirez-Ortiz's avatar Jorge Ramirez-Ortiz Committed by ldts

rcar-gen3: initial commit for the rcar-gen3 boards

Reference code:
==============

rar_gen3: IPL and Secure Monitor Rev1.0.22
https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3]

Author: Takuya Sakata <takuya.sakata.wz@bp.renesas.com>
Date:   Thu Aug 30 21:26:41 2018 +0900
	Update IPL and Secure Monitor Rev1.0.22

General Information:
===================

This port has been tested on the Salvator-X Soc_id r8a7795 revision
ES1.1 (uses an SPD).

Build Tested:
-------------
ATFW_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1"
MBEDTLS_DIR=$mbedtls

$ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed

Other dependencies:
------------------
* mbed_tls:
  git@github.com:ARMmbed/mbedtls.git [devel]

  Merge: 68dbc94 f34a4c1
  Author: Simon Butcher <simon.butcher@arm.com>
  Date:   Thu Aug 30 00:57:28 2018 +0100

* optee_os:
  https://github.com/BayLibre/optee_os

  Until it gets merged into OP-TEE, the port requires Renesas' Trusted
  Environment with a modification to support power management.

  Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
  Date:   Thu Aug 30 16:49:49 2018 +0200
    plat-rcar: cpu-suspend: handle the power level
Signed-off-by: default avatarJorge Ramirez-Ortiz <jramirez@baylibre.com>

* u-boot:
  The port has beent tested using mainline uboot.

  Author: Fabio Estevam <festevam@gmail.com>
  Date:   Tue Sep 4 10:23:12 2018 -0300

*linux:
  The port has beent tested using mainline kernel.

  Author: Linus Torvalds <torvalds@linux-foundation.org>
  Date:   Sun Sep 16 11:52:37 2018 -0700
      Linux 4.19-rc4

Overview
---------

BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered
at this exception level (the Renesas' ATF reference tree [1] resets into
EL1 before entering BL2 - see its bl2.ld.S)

BL2 initializes DDR (and i2c to talk to the PMIC on some platforms)
before determining the boot reason (cold or warm).

During suspend all CPUs are switched off and the DDR is put in
backup mode (some kind of self-refresh mode). This means that BL2 is
always entered in a cold boot scenario.

Once BL2 boots, it determines the boot reason, writes it to shared
memory (BOOT_KIND_BASE) together with the BL31 parameters
(PARAMS_BASE) and jumps to BL31.

To all effects, BL31 is as if it is being entered in reset mode since
it still needs to initialize the rest of the cores; this is the reason
behind using direct shared memory access to  BOOT_KIND_BASE and
PARAMS_BASE instead of using registers to get to those locations (see
el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use
case).

Depending on the boot reason BL31 initializes the rest of the cores:
in case of suspend, it uses a MBOX memory region to recover the
program counters.

[1] https://github.com/renesas-rcar/arm-trusted-firmware
Tests
-----

* cpuidle
  -------
   enable kernel's cpuidle arm_idle driver and boot

* system suspend
  --------------
  $ cat suspend.sh
    #!/bin/bash
    i2cset -f -y 7 0x30 0x20 0x0F
    read -p "Switch off SW23 and press return " foo
    echo mem > /sys/power/state

* cpu hotplug:
  ------------
  $ cat offline.sh
    #!/bin/bash
    nbr=$1
    echo 0 > /sys/devices/system/cpu/cpu$nbr/online
    printf "ONLINE:  " && cat /sys/devices/system/cpu/online
    printf "OFFLINE: " && cat /sys/devices/system/cpu/offline

  $ cat online.sh
    #!/bin/bash
    nbr=$1
    echo 1 > /sys/devices/system/cpu/cpu$nbr/online
    printf "ONLINE:  " && cat /sys/devices/system/cpu/online
    printf "OFFLINE: " && cat /sys/devices/system/cpu/offline
Signed-off-by: default avatarldts <jramirez@baylibre.com>
parent 0a09313e
...@@ -11,6 +11,10 @@ build/ ...@@ -11,6 +11,10 @@ build/
# Ignore build products from tools # Ignore build products from tools
tools/**/*.o tools/**/*.o
tools/renesas/rcar_layout_create/*.bin
tools/renesas/rcar_layout_create/*.srec
tools/renesas/rcar_layout_create/*.map
tools/renesas/rcar_layout_create/*.elf
tools/fiptool/fiptool tools/fiptool/fiptool
tools/fiptool/fiptool.exe tools/fiptool/fiptool.exe
tools/cert_create/src/*.o tools/cert_create/src/*.o
......
Description
===========
"R-Car" is the nickname for Renesas' system-on-chip (SoC) family for
car information systems designed for the next-generation of automotive
computing for the age of autonomous vehicles.
The scalable R-Car hardware platform and flexible software platform
cover the full product range, from the premium class to the entry
level. Plug-ins are available for multiple open-source software tools.
Renesas R-Car Gen3 evaluation boards:
-------------------------------------
+------------+-----------------+-----------------------------+
| | Standard | Low Cost Boards (LCB) |
+============+=================+=============================+
| R-Car H3 | - Salvator-X | - R-Car Starter Kit Premier |
| | - Salvator-XS | |
+------------+-----------------+-----------------------------+
| R-Car M3-W | - Salvator-X | |
| | - Salvator-XS | - R-Car Starter Kit Pro |
+------------+-----------------+-----------------------------+
| R-Car M3-N | - Salvator-X | |
| | - Salvator-XS | |
+------------+-----------------+-----------------------------+
| R-Car V3M | - Eagle | - Starter Kit |
+------------+-----------------+-----------------------------+
| R-Car V3H | - Condor | - Starter Kit |
+------------+-----------------+-----------------------------+
| R-Car D3 | - Draak | |
+------------+-----------------+-----------------------------+
`boards info <https://elinux.org/R-Car>`__
The current TF-A port has been tested on the R-Car H3 Salvator-X
Soc_id r8a7795 revision ES1.1 (uses a Secure Payload Dispatcher)
::
ARM CA57 (ARMv8) 1.5 GHz quad core, with NEON/VFPv4, L1$ I/D
48K/32K, L2$ 2MB
ARM CA53 (ARMv8) 1.2 GHz quad core, with NEON/VFPv4, L1$ I/D 32K/32K,
L2$ 512K
Memory controller for LPDDR4-3200 4GB in 2 channels, each 64-bit wide
Two- and three-dimensional graphics engines,
Video processing units,
3 channels Display Output,
6 channels Video Input,
SD card host interface,
USB3.0 and USB2.0 interfaces,
CAN interfaces
Ethernet AVB
PCI Express Interfaces
Memories
INTERNAL 384KB SYSTEM RAM
DDR 4 GB LPDDR4
HYPERFLASH 64 MB HYPER FLASH (512 MBITS, 160 MHZ, 320 MBYTES/S)
QSPI FLASH 16MB QSPI (128 MBITS,80 MHZ,80 MBYTES/S)1 HEADER QSPI
MODULE
EMMC 32 GB EMMC (HS400 240 MBYTES/S)
MICROSD-CARD SLOT (SDR104 100 MBYTES/S)
Overview
--------
On the rcar-gen3 the BOOTROM starts the cpu at EL3; for this port BL2
will therefore be entered at this exception level (the Renesas' ATF
reference tree [1] resets into EL1 before entering BL2 - see its
bl2.ld.S)
BL2 initializes DDR (and on some platforms i2c to interface to the
PMIC) before determining the boot reason (cold or warm).
During suspend all CPUs are switched off and the DDR is put in backup
mode (some kind of self-refresh mode). This means that BL2 is always
entered in a cold boot scenario.
Once BL2 boots, it determines the boot reason, writes it to shared
memory (BOOT_KIND_BASE) together with the BL31 parameters
(PARAMS_BASE) and jumps to BL31.
To all effects, BL31 is as if it is being entered in reset mode since
it still needs to initialize the rest of the cores; this is the reason
behind using direct shared memory access to BOOT_KIND_BASE _and_
PARAMS_BASE instead of using registers to get to those locations (see
el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use
case).
Depending on the boot reason BL31 initializes the rest of the cores:
in case of suspend, it uses a MBOX memory region to recover the
program counters.
[1] https://github.com/renesas-rcar/arm-trusted-firmware
How to build
============
The TF-A build options depend on the target board so you will have to
refer to those specific instructions. What follows is customized to
the H3 SiP Salvator-X development system used in this port.
Build Tested:
-------------
RCAR_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1"
MBEDTLS_DIR=$mbedtls_src
$ MBEDTLS_DIR=$mbedtls_src_tree make clean bl2 bl31 rcar_layout_tool \
PLAT=rcar ${RCAR_OPT} SPD=opteed
System Tested:
--------------------
* mbed_tls:
git@github.com:ARMmbed/mbedtls.git [devel]
commit 552754a6ee82bab25d1bdf28c8261a4518e65e4d
Merge: 68dbc94 f34a4c1
Author: Simon Butcher <simon.butcher@arm.com>
Date: Thu Aug 30 00:57:28 2018 +0100
* optee_os:
https://github.com/BayLibre/optee_os
Until it gets merged into OP-TEE, the port requires Renesas'
Trusted Environment with a modification to support power
management.
commit 80105192cba9e704ebe8df7ab84095edc2922f84
Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
Date: Thu Aug 30 16:49:49 2018 +0200
plat-rcar: cpu-suspend: handle the power level
Signed-off-by: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
* u-boot:
The port has beent tested using mainline uboot.
commit 4cdeda511f8037015b568396e6dcc3d8fb41e8c0
Author: Fabio Estevam <festevam@gmail.com>
Date: Tue Sep 4 10:23:12 2018 -0300
* linux:
The port has beent tested using mainline kernel.
commit 7876320f88802b22d4e2daf7eb027dd14175a0f8
Author: Linus Torvalds <torvalds@linux-foundation.org>
Date: Sun Sep 16 11:52:37 2018 -0700
Linux 4.19-rc4
TF-A Build Procedure
--------------------
- Fetch all the above 4 repositories.
- Prepare the AARCH64 toolchain.
- Build u-boot using r8a7795_salvator-x_defconfig.
Result: u-boot-elf.srec
.. code:: bash
make CROSS_COMPILE=aarch64-linux-gnu-
r8a7795_salvator-x_defconfig
make CROSS_COMPILE=aarch64-linux-gnu-
- Build atf
Result: bootparam_sa0.srec, cert_header_sa6.srec, bl2.srec, bl31.srec
.. code:: bash
RCAR_OPT="LSI=H3 RCAR_DRAM_SPLIT=1 RCAR_LOSSY_ENABLE=1"
MBEDTLS_DIR=$mbedtls_src_tree make clean bl2 bl31 rcar \
PLAT=rcar ${RCAR_OPT} SPD=opteed
- Build optee-os
Result: tee.srec
.. code:: bash
make -j8 PLATFORM="rcar" CFG_ARM64_core=y
Install Procedure
-----------------
- Boot the board in Mini-monitor mode and enable access to the
Hyperflash.
- Use the XSL2 Mini-monitor utility to accept all the SREC ascii
transfers over serial.
Boot trace
==========
Notice that BL31 traces are not accessible via the console and that in
order to verbose the BL2 output you will have to compile TF-A with
LOG_LEVEL=50 and DEBUG=1
::
Initial Program Loader(CA57) Rev.1.0.22
NOTICE: BL2: PRR is R-Car H3 Ver.1.1
NOTICE: BL2: Board is Salvator-X Rev.1.0
NOTICE: BL2: Boot device is HyperFlash(80MHz)
NOTICE: BL2: LCM state is CM
NOTICE: AVS setting succeeded. DVFS_SetVID=0x53
NOTICE: BL2: DDR1600(rev.0.33)NOTICE: [COLD_BOOT]NOTICE: ..0
NOTICE: BL2: DRAM Split is 4ch
NOTICE: BL2: QoS is default setting(rev.0.37)
NOTICE: BL2: Lossy Decomp areas
NOTICE: Entry 0: DCMPAREACRAx:0x80000540 DCMPAREACRBx:0x570
NOTICE: Entry 1: DCMPAREACRAx:0x40000000 DCMPAREACRBx:0x0
NOTICE: Entry 2: DCMPAREACRAx:0x20000000 DCMPAREACRBx:0x0
NOTICE: BL2: v2.0(release):v2.0-rc0-32-gbcda69a
NOTICE: BL2: Built : 16:41:23, Oct 2 2018
NOTICE: BL2: Normal boot
INFO: BL2: Doing platform setup
INFO: BL2: Loading image id 3
NOTICE: BL2: dst=0xe6322000 src=0x8180000 len=512(0x200)
NOTICE: BL2: dst=0x43f00000 src=0x8180400 len=6144(0x1800)
WARNING: r-car ignoring the BL31 size from certificate,using
RCAR_TRUSTED_SRAM_SIZE instead
INFO: Loading image id=3 at address 0x44000000
NOTICE: rcar_file_len: len: 0x0003e000
NOTICE: BL2: dst=0x44000000 src=0x81c0000 len=253952(0x3e000)
INFO: Image id=3 loaded: 0x44000000 - 0x4403e000
INFO: BL2: Loading image id 4
INFO: Loading image id=4 at address 0x44100000
NOTICE: rcar_file_len: len: 0x00100000
NOTICE: BL2: dst=0x44100000 src=0x8200000 len=1048576(0x100000)
INFO: Image id=4 loaded: 0x44100000 - 0x44200000
INFO: BL2: Loading image id 5
INFO: Loading image id=5 at address 0x50000000
NOTICE: rcar_file_len: len: 0x00100000
NOTICE: BL2: dst=0x50000000 src=0x8640000 len=1048576(0x100000)
INFO: Image id=5 loaded: 0x50000000 - 0x50100000
NOTICE: BL2: Booting BL31
INFO: Entry point address = 0x44000000
INFO: SPSR = 0x3cd
VERBOSE: Argument #0 = 0xe6325578
VERBOSE: Argument #1 = 0x0
VERBOSE: Argument #2 = 0x0
VERBOSE: Argument #3 = 0x0
VERBOSE: Argument #4 = 0x0
VERBOSE: Argument #5 = 0x0
VERBOSE: Argument #6 = 0x0
VERBOSE: Argument #7 = 0x0
U-Boot 2018.09-rc3-00028-g3711616 (Sep 27 2018 - 18:50:24 +0200)
CPU: Renesas Electronics R8A7795 rev 1.1
Model: Renesas Salvator-X board based on r8a7795 ES2.0+
DRAM: 3.5 GiB
Flash: 64 MiB
MMC: sd@ee100000: 0, sd@ee140000: 1, sd@ee160000: 2
Loading Environment from MMC... OK
In: serial@e6e88000
Out: serial@e6e88000
Err: serial@e6e88000
Net: eth0: ethernet@e6800000
Hit any key to stop autoboot: 0
=>
/*
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <mmio.h>
#include "rcar_private.h"
void
#if IMAGE_BL31
__attribute__ ((section(".system_ram")))
#endif
cpg_write(uintptr_t regadr, uint32_t regval)
{
uint32_t value = (regval);
mmio_write_32((uintptr_t) RCAR_CPGWPR, ~value);
mmio_write_32(regadr, value);
}
void
#if IMAGE_BL31
__attribute__ ((section(".system_ram")))
#endif
mstpcr_write(uint32_t mstpcr, uint32_t mstpsr, uint32_t target_bit)
{
uint32_t reg;
reg = mmio_read_32(mstpcr);
reg &= ~target_bit;
cpg_write(mstpcr, reg);
while ((mmio_read_32(mstpsr) & target_bit) != 0U) {
}
}
...@@ -140,6 +140,15 @@ Raspberry Pi 3 platform port ...@@ -140,6 +140,15 @@ Raspberry Pi 3 platform port
:F: docs/plat/rpi3.rst :F: docs/plat/rpi3.rst
:F: plat/rpi3/ :F: plat/rpi3/
Renesas rcar-gen3 platform port
-------------------------------
:M: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
:G: `ldts`_
:F: docs/plat/rcar-gen3.rst
:F: plat/renesas/rcar
:F: drivers/renesas/rcar
:F: tools/renesas/rcar_layout_create
RockChip platform port RockChip platform port
---------------------- ----------------------
:M: Tony Xie <tony.xie@rock-chips.com> :M: Tony Xie <tony.xie@rock-chips.com>
...@@ -208,6 +217,7 @@ Xilinx platform port ...@@ -208,6 +217,7 @@ Xilinx platform port
.. _glneo: https://github.com/glneo .. _glneo: https://github.com/glneo
.. _hzhuang1: https://github.com/hzhuang1 .. _hzhuang1: https://github.com/hzhuang1
.. _jenswi-linaro: https://github.com/jenswi-linaro .. _jenswi-linaro: https://github.com/jenswi-linaro
.. _ldts: https://github.com/ldts
.. _niej: https://github.com/niej .. _niej: https://github.com/niej
.. _kostapr: https://github.com/kostapr .. _kostapr: https://github.com/kostapr
.. _masahir0y: https://github.com/masahir0y .. _masahir0y: https://github.com/masahir0y
......
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
#include <bl_common.h>
#include <cortex_a57.h>
#include <platform_def.h>
#include <runtime_svc.h>
#include "rcar_def.h"
.globl plat_get_my_entrypoint
.extern plat_set_my_stack
.globl platform_mem_init
.globl plat_crash_console_init
.globl plat_crash_console_putc
.globl plat_invalidate_icache
.globl plat_report_exception
.globl plat_secondary_reset
.globl plat_reset_handler
.globl plat_my_core_pos
.extern rcar_log_init
#if IMAGE_BL2
#define INT_ID_MASK (0x3ff)
.extern bl2_interrupt_error_type
.extern bl2_interrupt_error_id
.globl bl2_enter_bl31
.extern gicv2_acknowledge_interrupt
.extern rcar_swdt_exec
#endif
/* -----------------------------------------------------
* void platform_get_core_pos (mpidr)
* -----------------------------------------------------
*/
func platform_get_core_pos
and x1, x0, #MPIDR_CPU_MASK
and x0, x0, #MPIDR_CLUSTER_MASK
add x0, x1, x0, LSR #6
ret
endfunc platform_get_core_pos
/* -----------------------------------------------------
* void platform_my_core_pos
* -----------------------------------------------------
*/
func plat_my_core_pos
mrs x0, mpidr_el1
b platform_get_core_pos
endfunc plat_my_core_pos
/* -----------------------------------------------------
* void platform_get_my_entrypoint (unsigned int mpid);
*
* Main job of this routine is to distinguish between
* a cold and warm boot.
* On a cold boot the secondaries first wait for the
* platform to be initialized after which they are
* hotplugged in. The primary proceeds to perform the
* platform initialization.
* On a warm boot, each cpu jumps to the address in its
* mailbox.
*
* TODO: Not a good idea to save lr in a temp reg
* -----------------------------------------------------
*/
func plat_get_my_entrypoint
mrs x0, mpidr_el1
mov x9, x30 /* lr */
#if defined(IMAGE_BL2)
/* always cold boot on bl2 */
mov x0, #0
ret x9
#else
ldr x1, =BOOT_KIND_BASE
ldr x21, [x1]
/* Check the reset info */
and x1, x21, #0x000c
cmp x1, #0x0008
beq el3_panic
cmp x1, #0x000c
beq el3_panic
/* Check the boot kind */
and x1, x21, #0x0003
cmp x1, #0x0002
beq el3_panic
cmp x1, #0x0003
beq el3_panic
/* warm boot or cold boot */
and x1, x21, #1
cmp x1, #0
bne warm_reset
/* Cold boot */
mov x0, #0
b exit
warm_reset:
/* --------------------------------------------------------------------
* A per-cpu mailbox is maintained in the trusted SDRAM. Its flushed out
* of the caches after every update using normal memory so its safe to
* read it here with SO attributes
* ---------------------------------------------------------------------
*/
ldr x10, =MBOX_BASE
bl platform_get_core_pos
lsl x0, x0, #CACHE_WRITEBACK_SHIFT
ldr x0, [x10, x0]
cbz x0, _panic
exit:
ret x9
_panic:
b do_panic
#endif
endfunc plat_get_my_entrypoint
/* ---------------------------------------------
* plat_secondary_reset
*
* ---------------------------------------------
*/
func plat_secondary_reset
mrs x0, sctlr_el3
bic x0, x0, #SCTLR_EE_BIT
msr sctlr_el3, x0
isb
mrs x0, cptr_el3
bic w0, w0, #TCPAC_BIT
bic w0, w0, #TTA_BIT
bic w0, w0, #TFP_BIT
msr cptr_el3, x0
mov_imm x0, PARAMS_BASE
mov_imm x2, BL31_BASE
ldr x3, =BOOT_KIND_BASE
mov x1, #0x1
str x1, [x3]
br x2 /* jump to BL31 */
nop
nop
nop
endfunc plat_secondary_reset
/* ---------------------------------------------
* plat_enter_bl31
*
* ---------------------------------------------
*/
func bl2_enter_bl31
mov x20, x0
/*
* MMU needs to be disabled because both BL2 and BL31 execute
* in EL3, and therefore share the same address space.
* BL31 will initialize the address space according to its
* own requirement.
*/
#if RCAR_BL2_DCACHE == 1
/* Disable mmu and data cache */
bl disable_mmu_el3
/* Data cache clean and invalidate */
mov x0, #DCCISW
bl dcsw_op_all
/* TLB invalidate all, EL3 */
tlbi alle3
#endif /* RCAR_BL2_DCACHE == 1 */
bl disable_mmu_icache_el3
/* Invalidate instruction cache */
ic iallu
dsb sy
isb
ldp x0, x1, [x20, #ENTRY_POINT_INFO_PC_OFFSET]
msr elr_el3, x0
msr spsr_el3, x1
eret
endfunc bl2_enter_bl31
/* -----------------------------------------------------
* void platform_mem_init (void);
*
* Zero out the mailbox registers in the shared memory
* and set the rcar_boot_kind_flag.
* The mmu is turned off right now and only the primary can
* ever execute this code. Secondaries will read the
* mailboxes using SO accesses.
* -----------------------------------------------------
*/
func platform_mem_init
#if !IMAGE_BL2
ldr x0, =MBOX_BASE
mov w1, #PLATFORM_CORE_COUNT
loop:
str xzr, [x0], #CACHE_WRITEBACK_GRANULE
subs w1, w1, #1
b.gt loop
#endif
ret
endfunc platform_mem_init
/* ---------------------------------------------
* void plat_report_exception(unsigned int type)
* Function to report an unhandled exception
* with platform-specific means.
* ---------------------------------------------
*/
func plat_report_exception
#if IMAGE_BL2
mov w1, #FIQ_SP_EL0
cmp w0, w1
beq rep_exec_fiq_elx
b rep_exec_panic_type
rep_exec_fiq_elx:
bl gicv2_acknowledge_interrupt
mov x2, #INT_ID_MASK
and x0, x0, x2
mov x1, #ARM_IRQ_SEC_WDT
cmp x0, x1
bne rep_exec_panic_id
mrs x0, ELR_EL3
b rcar_swdt_exec
rep_exec_panic_type:
/* x0 is interrupt TYPE */
b bl2_interrupt_error_type
rep_exec_panic_id:
/* x0 is interrupt ID */
b bl2_interrupt_error_id
rep_exec_end:
#endif
ret
endfunc plat_report_exception
/* ---------------------------------------------
* int plat_crash_console_init(void)
* Function to initialize log area
* ---------------------------------------------
*/
func plat_crash_console_init
#if IMAGE_BL2
mov x0, #0
#else
mov x1, sp
mov_imm x2, RCAR_CRASH_STACK
mov sp, x2
str x1, [sp, #-16]!
str x30, [sp, #-16]!
bl console_core_init
ldr x30, [sp], #16
ldr x1, [sp], #16
mov sp, x1
#endif
ret
endfunc plat_crash_console_init
/* ---------------------------------------------
* int plat_crash_console_putc(int c)
* Function to store a character to log area
* ---------------------------------------------
*/
func plat_crash_console_putc
mov x1, sp
mov_imm x2, RCAR_CRASH_STACK
mov sp, x2
str x1, [sp, #-16]!
str x30, [sp, #-16]!
str x3, [sp, #-16]!
str x4, [sp, #-16]!
str x5, [sp, #-16]!
bl console_core_putc
ldr x5, [sp], #16
ldr x4, [sp], #16
ldr x3, [sp], #16
ldr x30, [sp], #16
ldr x1, [sp], #16
mov sp, x1
ret
endfunc plat_crash_console_putc
/* --------------------------------------------------------------------
* void plat_reset_handler(void);
*
* Before adding code in this function, refer to the guidelines in
* docs/firmware-design.md to determine whether the code should reside
* within the FIRST_RESET_HANDLER_CALL block or not.
*
* For R-Car H3:
* - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
* - Set the L2 Data setup latency to 1 (i.e. 1 cycles) for Cortex-A57
* - Set the L2 Data RAM latency to 3 (i.e. 4 cycles) for Cortex-A57
* For R-Car M3/M3N:
* - Set the L2 Tag RAM latency to 2 (i.e. 3 cycles) for Cortex-A57
* - Set the L2 Data setup latency to 0 (i.e. 0 cycles) for Cortex-A57
* - Set the L2 Data RAM latency to 3 (i.e. 4 cycles) for Cortex-A57
*
* --------------------------------------------------------------------
*/
func plat_reset_handler
/*
* On R-Car H3 : x2 := 0
* On R-Car M3/M3N: x2 := 1
*/
/* read PRR */
ldr x0, =0xFFF00044
ldr w0, [x0]
ubfx w0, w0, 8, 8
/* H3? */
cmp w0, #0x4F
b.eq H3
/* set R-Car M3/M3N */
mov x2, #1
b CHK_A5x
H3:
/* set R-Car H3 */
mov x2, #0
/* --------------------------------------------------------------------
* Determine whether this code is executed on a Cortex-A53 or on a
* Cortex-A57 core.
* --------------------------------------------------------------------
*/
CHK_A5x:
mrs x0, midr_el1
ubfx x1, x0, MIDR_PN_SHIFT, #12
cmp w1, #((CORTEX_A57_MIDR >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
b.eq A57
ret
A57:
/* Get data from CORTEX_A57_L2CTLR_EL1 */
mrs x0, CORTEX_A57_L2CTLR_EL1
/*
* On R-Car H3/M3/M3N
*
* L2 Tag RAM latency is bit8-6 of CORTEX_A57_L2CTLR_EL1
* L2 Data RAM setup is bit5 of CORTEX_A57_L2CTLR_EL1
* L2 Data RAM latency is bit2-0 of CORTEX_A57_L2CTLR_EL1
*/
/* clear bit of L2 RAM */
/* ~(0x1e7) -> x1 */
mov x1, #0x1e7
neg x1, x1
/* clear bit of L2 RAM -> x0 */
and x0, x0, x1
/* L2 Tag RAM latency (3 cycles) */
orr x0, x0, #0x2 << 6
/* If M3/M3N then L2 RAM setup is 0 */
cbnz x2, M3_L2
/* L2 Data RAM setup (1 cycle) */
orr x0, x0, #0x1 << 5
M3_L2:
/* L2 Data RAM latency (4 cycles) */
orr x0, x0, #0x3
/* Store data to L2CTLR_EL1 */
msr CORTEX_A57_L2CTLR_EL1, x0
apply_l2_ram_latencies:
ret
endfunc plat_reset_handler
/* ---------------------------------------------
* void plat_invalidate_icache(void)
* Instruction Cache Invalidate All to PoU
* ---------------------------------------------
*/
func plat_invalidate_icache
ic iallu
ret
endfunc plat_invalidate_icache
/*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <arch_helpers.h>
#include <bl_common.h>
#include <debug.h>
#include <gicv2.h>
#include <gic_common.h>
#include <interrupt_props.h>
#include <mmio.h>
#include <platform.h>
#include <platform_def.h>
#include <xlat_tables_v2.h>
#include "rcar_def.h"
#include "rcar_private.h"
#include "rcar_version.h"
#if (IMAGE_BL2)
extern void rcar_read_certificate(uint64_t cert, uint32_t *len, uintptr_t *p);
extern int32_t rcar_get_certificate(const int32_t name, uint32_t *cert);
#endif
const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN]
__attribute__ ((__section__("ro"))) = VERSION_OF_RENESAS;
#define MAP_SHARED_RAM MAP_REGION_FLAT(RCAR_SHARED_MEM_BASE, \
RCAR_SHARED_MEM_SIZE, \
MT_MEMORY | MT_RW | MT_SECURE)
#define MAP_FLASH0 MAP_REGION_FLAT(FLASH0_BASE, \
FLASH0_SIZE, \
MT_MEMORY | MT_RO | MT_SECURE)