1. 17 Jun, 2019 1 commit
  2. 22 May, 2019 4 commits
    • Paul Beesley's avatar
      doc: Use proper note and warning annotations · e1c5026a
      Paul Beesley authored
      The documentation contains plenty of notes and warnings. Enable
      special rendering of these blocks by converting the note prefix
      into a .. note:: annotation.
      Change-Id: I34e26ca6bf313d335672ab6c2645741900338822
      Signed-off-by: default avatarPaul Beesley <paul.beesley@arm.com>
    • Paul Beesley's avatar
      doc: Set correct syntax highlighting style · 29c02529
      Paul Beesley authored
      Several code blocks do not specify a language for syntax
      highlighting. This results in Sphinx using a default highlighter
      which is Python.
      This patch adds the correct language to each code block that doesn't
      already specify it.
      Change-Id: Icce1949aabfdc11a334a42d49edf55fa673cddc3
      Signed-off-by: default avatarPaul Beesley <paul.beesley@arm.com>
    • Paul Beesley's avatar
      doc: Remove per-page contents lists · 57354abb
      Paul Beesley authored
      These are no longer needed as there will always be a table of contents
      rendered to the left of every page.
      Some of these lists can be quite long and, when opening a page, the
      reader sees nothing but a huge list of contents! After this patch,
      the document contents are front-and-centre and the contents are
      nicely rendered in the sidebar without duplication.
      Change-Id: I444754d548ec91d00f2b04e861de8dde8856aa62
      Signed-off-by: default avatarPaul Beesley <paul.beesley@arm.com>
    • Paul Beesley's avatar
      doc: Reformat platform port documents · 24dba2b3
      Paul Beesley authored
      The platform port documents are not very standardised right now and
      they don't integrate properly into the document tree so:
      1) Make sure each port has a proper name and title (incl. owner)
      2) Correct use of headings, subheadings, etc in each port
      3) Resolve any naming conflicts between documents
      Change-Id: I4c2da6f57172b7f2af3512e766ae9ce3b840b50f
      Signed-off-by: default avatarPaul Beesley <paul.beesley@arm.com>
  3. 21 May, 2019 1 commit
    • Paul Beesley's avatar
      doc: Move documents into subdirectories · 40d553cf
      Paul Beesley authored
      This change creates the following directories under docs/
      in order to provide a grouping for the content:
      - components
      - design
      - getting_started
      - perf
      - process
      In each of these directories an index.rst file is created
      and this serves as an index / landing page for each of the
      groups when the pages are compiled. Proper layout of the
      top-level table of contents relies on this directory/index
      Without this patch it is possible to build the documents
      correctly with Sphinx but the output looks messy because
      there is no overall hierarchy.
      Change-Id: I3c9f4443ec98571a56a6edf775f2c8d74d7f429f
      Signed-off-by: default avatarPaul Beesley <paul.beesley@arm.com>
  4. 10 May, 2019 1 commit
  5. 26 Apr, 2019 1 commit
  6. 25 Apr, 2019 1 commit
    • Heiko Stuebner's avatar
      rockchip: document platform · 55617251
      Heiko Stuebner authored
      This adds a rockchip.rst to docs/plat documenting the general
      approach to using the Rockchip ATF platforms together with the
      supported bootloaders and also adds myself as maintainer after
      making sure Tony Xie is ok with that.
      Signed-off-by: default avatarHeiko Stuebner <heiko@sntech.de>
      Change-Id: Idce53d15eff4ac6de05bbb35d86e57ed50d0cbb9
  7. 23 Apr, 2019 1 commit
    • Yann Gautier's avatar
      stm32mp1: add OP-TEE support · 1989a19c
      Yann Gautier authored
      Support booting OP-TEE as BL32 boot stage and secure runtime
      OP-TEE executes in internal RAM and uses a secure DDR area to store
      the pager pagestore. Memory mapping and TZC are configured accordingly
      prior OP-TEE boot. OP-TEE image is expected in OP-TEE v2 format where
      a header file describes the effective boot images. This change
      post processes header file content to get OP-TEE load addresses
      and set OP-TEE boot arguments.
      Change-Id: I02ef8b915e4be3e95b27029357d799d70e01cd44
      Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
      Signed-off-by: default avatarEtienne Carriere <etienne.carriere@st.com>
  8. 02 Apr, 2019 1 commit
  9. 13 Mar, 2019 1 commit
    • Jacky Bai's avatar
      plat: imx8m: Add the basic support for imx8mm · 179f82a2
      Jacky Bai authored
      The i.MX8M Mini is new SOC of the i.MX8M family. it is
      focused on delivering the latest and greatest video and
      audio experience combining state-of-the-art media-specific
      features with high-performance processing while optimized
      for lowest power consumption. The i.MX 8M Mini Media Applications
      Processor is  14nm FinFET product of the growing i.MX8M family
      targeting the consumer & industrial market. It is built in 14LPP
      to achieve both high performance and low power consumption
      and relies on a powerful fully coherent core complex based on
      a quad Cortex-A53 cluster with video and graphics accelerators
      this patch add the basic support for i.MX8MM.
      Signed-off-by: default avatarJacky Bai <ping.bai@nxp.com>
  10. 27 Feb, 2019 1 commit
    • Varun Wadekar's avatar
      Tegra: Support for scatterfile for the BL31 image · c2ad38ce
      Varun Wadekar authored
      This patch provides support for using the scatterfile format as
      the linker script with the 'armlink' linker for Tegra platforms.
      In order to enable the scatterfile usage the following changes
      have been made:
      * provide mapping for ld.S symbols in bl_common.h
      * include bl_common.h from all the affected files
      * update the makefile rules to use the scatterfile and armlink
        to compile BL31
      * update pubsub.h to add sections to the scatterfile
      Change-Id: I7bb78b991c97d74a842e5635c74cb0b18e0fce67
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
  11. 26 Feb, 2019 1 commit
  12. 20 Feb, 2019 1 commit
  13. 19 Feb, 2019 1 commit
  14. 08 Feb, 2019 1 commit
  15. 05 Feb, 2019 1 commit
  16. 18 Jan, 2019 2 commits
    • Varun Wadekar's avatar
      Tegra: lib: library for profiling the cold boot path · 087cf68a
      Varun Wadekar authored
      The non secure world would like to profile the boot path for
      the EL3 and S-EL1 firmwares. To allow it to do that, a non-secure
      DRAM region (4K) is allocated and the base address is passed to
      the EL3 firmware.
      This patch adds a library to allow the platform code to store the
      tag:timestamp pair to the shared memory. The tegra platform code
      then uses the `record` method to add timestamps.
      Original change by Akshay Sharan <asharan@nvidia.com>
      Change-Id: Idbbef9c83ed84a508b04d85a6637775960dc94ba
      Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
    • Bryan O'Donoghue's avatar
      docs: warp7: Update WaRP7 description for TBB · 31e4c20d
      Bryan O'Donoghue authored
      This patch updates the WaRP7 build descriptions for booting WaRP7 in
      Trusted Board Boot mode. TBB is the only mode we really intend to support
      for this board so rather than maintain documentation for the old way of
      doing it, this patch updates the description for TBB mode only.
      Signed-off-by: default avatarBryan O'Donoghue <bryan.odonoghue@linaro.org>
  17. 16 Jan, 2019 1 commit
  18. 05 Dec, 2018 1 commit
    • Bai Ping's avatar
      plat: imx: Add i.MX8MQ basic support · 81136819
      Bai Ping authored
      i.MX8MQ is new SOC of NXP's i.MX8M family based on
      A53. It can provide industry-leading audio, voice
      and video processing for applications that scale
      from consumer home audio to industrial building
      automation and mobile computers
      this patchset add the basic supoort to boot up
      the 4 X A53. more feature will be added later.
      Signed-off-by: default avatarBai Ping <ping.bai@nxp.com>
  19. 20 Nov, 2018 1 commit
  20. 19 Nov, 2018 1 commit
    • Pete Batard's avatar
      rpi3: add RPI3_USE_UEFI_MAP build option · 4dcf1fad
      Pete Batard authored
      The default Raspberry Pi 3 memory mapping for ATF is geared towards
      the use of uboot + Linux. This creates issues when trying to use
      ATF with an UEFI payload and Windows on ARM64.
      We therefore introduce new build option RPI3_USE_UEFI_MAP, that
      enables the build process to use an alternate memory mapping that
      is compatible with UEFI + Windows (as well as UEFI + Linux).
      Fixes ARM-software/tf-issues#649
      Signed-off-by: default avatarPete Batard <pete@akeo.ie>
  21. 13 Nov, 2018 1 commit
    • Pete Batard's avatar
      rpi3: add RPI3_RUNTIME_UART build option · 6d5c61de
      Pete Batard authored
      Some OSes (e.g. Ubuntu 18.04 LTS on Raspberry Pi 3) may disable the
      runtime UART in a manner that prevents the system from rebooting if
      ATF tries to send runtime messages there.
      Also, we don't want the firmware to share the UART with normal
      world, as this can be a DoS attack vector into the secure world.
      This patch fixes these 2 issues by introducing new build option
      RPI3_RUNTIME_UART, that disables the runtime UART by default.
      Fixes ARM-software/tf-issues#647
      Signed-off-by: default avatarPete Batard <pete@akeo.ie>
  22. 09 Nov, 2018 1 commit
    • Siva Durga Prasad Paladugu's avatar
      arm64: versal: Add support for new Xilinx Versal ACAPs · f91c3cb1
      Siva Durga Prasad Paladugu authored
      Xilinx is introducing Versal, an adaptive compute acceleration platform
      (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar
      Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with
      leading-edge memory and interfacing technologies to deliver powerful
      heterogeneous acceleration for any application. The Versal AI Core series has
      five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm
      Cortex-A72 application processors, dual-core Arm Cortex-R5 real-time
      processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines
      optimized for high-precision floating point with low latency.
      This patch adds Virtual QEMU platform support for
      this SoC "versal_virt".
      Signed-off-by: default avatarSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
      Signed-off-by: default avatarMichal Simek <michal.simek@xilinx.com>
  23. 26 Oct, 2018 1 commit
  24. 24 Oct, 2018 2 commits
    • Antonio Nino Diaz's avatar
      rpi3: Add mem reserve region to DTB if present · 5341b42e
      Antonio Nino Diaz authored
      When a device tree blob is present at a known address, instead of, for
      example, relying on the user modifying the Linux command line to warn
      about the memory reserved for the Trusted Firmware, pass it on the DTB.
      The current code deletes the memory reserved for the default bootstrap
      of the Raspberry Pi and adds the region used by the Trusted Firmware.
      This system replaces the previous one consisting on adding
      ``memmap=16M$256M`` to the Linux command line. It's also meant to be
      used by U-Boot and any other bootloader that understands DTB files.
      Change-Id: I13ee528475fb043d6e8d9e9f24228e37ac3ac436
      Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
    • Yann Gautier's avatar
      docs: stm32mp1: complete compilation and flashing steps · 1ebb915a
      Yann Gautier authored
      Add U-Boot compilation information.
      Add a chapter about how to populate SD-card.
      Signed-off-by: default avatarYann Gautier <yann.gautier@st.com>
  25. 17 Oct, 2018 1 commit
    • Jorge Ramirez-Ortiz's avatar
      rcar-gen3: initial commit for the rcar-gen3 boards · 7e532c4b
      Jorge Ramirez-Ortiz authored
      Reference code:
      rar_gen3: IPL and Secure Monitor Rev1.0.22
      https://github.com/renesas-rcar/arm-trusted-firmware [rcar_gen3]
      Author: Takuya Sakata <takuya.sakata.wz@bp.renesas.com>
      Date:   Thu Aug 30 21:26:41 2018 +0900
      	Update IPL and Secure Monitor Rev1.0.22
      General Information:
      This port has been tested on the Salvator-X Soc_id r8a7795 revision
      ES1.1 (uses an SPD).
      Build Tested:
      $ make clean bl2 bl31 rcar PLAT=rcar ${ATFW_OPT} SPD=opteed
      Other dependencies:
      * mbed_tls:
        git@github.com:ARMmbed/mbedtls.git [devel]
        Merge: 68dbc94 f34a4c1
        Author: Simon Butcher <simon.butcher@arm.com>
        Date:   Thu Aug 30 00:57:28 2018 +0100
      * optee_os:
        Until it gets merged into OP-TEE, the port requires Renesas' Trusted
        Environment with a modification to support power management.
        Author: Jorge Ramirez-Ortiz <jramirez@baylibre.com>
        Date:   Thu Aug 30 16:49:49 2018 +0200
          plat-rcar: cpu-suspend: handle the power level
      Signed-off-by: default avatarJorge Ramirez-Ortiz <jramirez@baylibre.com>
      * u-boot:
        The port has beent tested using mainline uboot.
        Author: Fabio Estevam <festevam@gmail.com>
        Date:   Tue Sep 4 10:23:12 2018 -0300
        The port has beent tested using mainline kernel.
        Author: Linus Torvalds <torvalds@linux-foundation.org>
        Date:   Sun Sep 16 11:52:37 2018 -0700
            Linux 4.19-rc4
      BOOTROM starts the cpu at EL3; In this port BL2 will therefore be entered
      at this exception level (the Renesas' ATF reference tree [1] resets into
      EL1 before entering BL2 - see its bl2.ld.S)
      BL2 initializes DDR (and i2c to talk to the PMIC on some platforms)
      before determining the boot reason (cold or warm).
      During suspend all CPUs are switched off and the DDR is put in
      backup mode (some kind of self-refresh mode). This means that BL2 is
      always entered in a cold boot scenario.
      Once BL2 boots, it determines the boot reason, writes it to shared
      memory (BOOT_KIND_BASE) together with the BL31 parameters
      (PARAMS_BASE) and jumps to BL31.
      To all effects, BL31 is as if it is being entered in reset mode since
      it still needs to initialize the rest of the cores; this is the reason
      behind using direct shared memory access to  BOOT_KIND_BASE and
      PARAMS_BASE instead of using registers to get to those locations (see
      el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use
      Depending on the boot reason BL31 initializes the rest of the cores:
      in case of suspend, it uses a MBOX memory region to recover the
      program counters.
      [1] https://github.com/renesas-rcar/arm-trusted-firmware
      * cpuidle
         enable kernel's cpuidle arm_idle driver and boot
      * system suspend
        $ cat suspend.sh
          i2cset -f -y 7 0x30 0x20 0x0F
          read -p "Switch off SW23 and press return " foo
          echo mem > /sys/power/state
      * cpu hotplug:
        $ cat offline.sh
          echo 0 > /sys/devices/system/cpu/cpu$nbr/online
          printf "ONLINE:  " && cat /sys/devices/system/cpu/online
          printf "OFFLINE: " && cat /sys/devices/system/cpu/offline
        $ cat online.sh
          echo 1 > /sys/devices/system/cpu/cpu$nbr/online
          printf "ONLINE:  " && cat /sys/devices/system/cpu/online
          printf "OFFLINE: " && cat /sys/devices/system/cpu/offline
      Signed-off-by: default avatarldts <jramirez@baylibre.com>
  26. 28 Sep, 2018 1 commit
  27. 04 Sep, 2018 1 commit
  28. 24 Jul, 2018 1 commit
  29. 16 Jul, 2018 5 commits
  30. 13 Jul, 2018 1 commit
  31. 12 Jul, 2018 1 commit