fsl-imx8qxp-lpddr4-arm2.dts 11.2 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
/*
 * Copyright 2017 NXP
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

/dts-v1/;

/* First 128KB is for PSCI ATF. */
/* Last 3M is for M4/RPMSG */
/memreserve/ 0x80000000 0x00400000;

#include "fsl-imx8qxp.dtsi"

/ {
	model = "Freescale i.MX8QXP LPDDR4 ARM2";
	compatible = "fsl,imx8qxp-lpddr4-arm2", "fsl,imx8qxp";

	chosen {
		bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
		stdout-path = &lpuart0;
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

37 38 39 40 41 42 43 44 45 46
		reg_usb_otg1_vbus: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			regulator-name = "usb_otg1_vbus";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>;
			enable-active-high;
		};

47
		reg_usdhc2_vmmc: usdhc2_vmmc {
48 49 50 51 52 53
			compatible = "regulator-fixed";
			regulator-name = "SD1_SPWR";
			regulator-min-microvolt = <3000000>;
			regulator-max-microvolt = <3000000>;
			gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>;
			enable-active-high;
54
			startup-delay-us = <300>;
55
			off-on-delay-us = <5000>;
56 57 58 59 60
		};
	};
};

&iomuxc {
61 62 63
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_hog_1>;

64
	imx8qxp-arm2 {
65 66 67 68 69
		pinctrl_hog_1: hoggrp-1 {
			fsl,pins = <
				SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03	  0x06000048
			>;
		};
70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108

		pinctrl_fec1: fec1grp {
			fsl,pins = <
				SC_P_ENET0_MDC_CONN_ENET0_MDC			0x06000048
				SC_P_ENET0_MDIO_CONN_ENET0_MDIO			0x06000048
				SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL	0x06000048
				SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC	0x06000048
				SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0	0x06000048
				SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1	0x06000048
				SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2	0x06000048
				SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3	0x06000048
				SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC	0x06000048
				SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL	0x06000048
				SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0	0x06000048
				SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1	0x06000048
				SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2	0x06000048
				SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3	0x06000048
			>;
		};

		pinctrl_fec2: fec2grp {
			fsl,pins = <
				SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL		0x06000048
				SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC		0x06000048
				SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0	0x06000048
				SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1	0x06000048
				SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2		0x06000048
				SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3		0x06000048
				SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC		0x06000048
				SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL		0x06000048
				SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0		0x06000048
				SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1	0x06000048
				SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2	0x06000048
				SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3		0x06000048
			>;
		};

		pinctrl_lpi2c1: lpi1cgrp {
			fsl,pins = <
109
				SC_P_USB_SS3_TC1_ADMA_I2C1_SCL	0x06000020
110 111 112 113 114 115 116 117 118 119 120 121 122
				SC_P_USB_SS3_TC3_ADMA_I2C1_SDA	0x06000020
			>;
		};

		pinctrl_lpi2c3: lpi2cgrp {
			fsl,pins = <
				SC_P_SPI3_CS1_ADMA_I2C3_SCL	0x06000020
				SC_P_MCLK_IN1_ADMA_I2C3_SDA	0x06000020
			>;
		};

		pinctrl_lpuart0: lpuart0grp {
			fsl,pins = <
123 124
				SC_P_UART0_RX_ADMA_UART0_RX	0x06000020
				SC_P_UART0_TX_ADMA_UART0_TX	0x06000020
125 126 127 128 129
			>;
		};

		pinctrl_usdhc1: usdhc1grp {
			fsl,pins = <
130
				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000041
131 132 133 134 135 136 137 138 139
				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000021
				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000021
				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000021
				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000021
				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000021
				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000021
				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000021
				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000021
				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000021
140
				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000041
141 142 143 144
				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000021
			>;
		};

145 146
		pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
			fsl,pins = <
147 148 149 150 151 152 153 154 155 156 157 158
				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000040
				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
159 160 161 162 163
			>;
		};

		pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
			fsl,pins = <
164 165 166 167 168 169 170 171 172 173 174 175
				SC_P_EMMC0_CLK_CONN_EMMC0_CLK		0x06000040
				SC_P_EMMC0_CMD_CONN_EMMC0_CMD		0x00000020
				SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0	0x00000020
				SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1	0x00000020
				SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2	0x00000020
				SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3	0x00000020
				SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4	0x00000020
				SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5	0x00000020
				SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6	0x00000020
				SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7	0x00000020
				SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE	0x06000040
				SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B	0x00000020
176 177 178 179
			>;
		};

		pinctrl_usdhc2_gpio: usdhc2gpiogrp {
180
			fsl,pins = <
181
				SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19	0x06000021
182 183
				SC_P_USDHC1_WP_LSIO_GPIO4_IO21		0x06000021
				SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22	0x06000021
184 185 186 187 188
			>;
		};

		pinctrl_usdhc2: usdhc2grp {
			fsl,pins = <
189
				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000041
190 191 192 193 194 195
				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x06000021
				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x06000021
				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x06000021
				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x06000021
				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x06000021
				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x06000021
196 197 198 199 200
			>;
		};

		pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
			fsl,pins = <
201 202 203 204 205 206 207
				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x06000020
				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x06000020
				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x06000020
				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x06000020
				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x06000020
				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x06000020
208 209 210 211 212
			>;
		};

		pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
			fsl,pins = <
213 214 215 216 217 218 219
				SC_P_USDHC1_CLK_CONN_USDHC1_CLK		0x06000040
				SC_P_USDHC1_CMD_CONN_USDHC1_CMD		0x06000020
				SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0	0x06000020
				SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1	0x06000020
				SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2	0x06000020
				SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3	0x06000020
				SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT	0x06000020
220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242
			>;
		};

		pinctrl_flexspi0: flexspi0grp {
			fsl,pins = <
				SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0	0x0600004c
				SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1	0x0600004c
				SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2	0x0600004c
				SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3	0x0600004c
				SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS		0x0600004c
				SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B	0x0600004c
				SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B	0x0600004c
				SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK	0x0600004c
				SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK	0x0600004c
				SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0	0x0600004c
				SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1	0x0600004c
				SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2	0x0600004c
				SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3	0x0600004c
				SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS		0x0600004c
				SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B	0x0600004c
				SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B	0x0600004c
			>;
		};
243 244 245 246 247 248 249 250 251 252 253 254 255 256

		pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp {
			fsl,pins = <
				SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020
				SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020
			>;
		};

		pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp {
			fsl,pins = <
				SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020
				SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020
			>;
		};
257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358
	};
};

&gpio0 {
	status = "okay";
};

&gpio3 {
	status = "okay";
};

&gpio4 {
	status = "okay";
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii";
	phy-handle = <&ethphy0>;
	fsl,ar8031-phy-fixup;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <0>;
		};

		ethphy1: ethernet-phy@1 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
		};
	};
};

&fec2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec2>;
	phy-mode = "rgmii";
	phy-handle = <&ethphy1>;
	fsl,ar8031-phy-fixup;
	fsl,magic-packet;
	status = "disabled";
};

&flexspi0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexspi0>;
	status = "okay";

	flash0: mt35xu512aba@0 {
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "spi-flash";
		spi-max-frequency = <29000000>;
		spi-nor,ddr-quad-read-dummy = <8>;
	};
};

&i2c1 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpi2c1>;
	status = "okay";
};

&i2c3 {
	#address-cells = <1>;
	#size-cells = <0>;
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpi2c3>;
	status = "okay";

	pca9557_a: gpio@18 {
		compatible = "nxp,pca9557";
		reg = <0x18>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	pca9557_b: gpio@19 {
		compatible = "nxp,pca9557";
		reg = <0x19>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	pca9557_c: gpio@1b {
		compatible = "nxp,pca9557";
		reg = <0x1b>;
		gpio-controller;
		#gpio-cells = <2>;
	};
};

359
&i2c0_mipi_lvds0 {
360 361 362
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
363
	pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>;
364 365 366 367 368 369 370 371 372
	clock-frequency = <100000>;
	status = "okay";

	it6263-0@4c {
		compatible = "ITE,it6263";
		reg = <0x4c>;
	};
};

373
&i2c0_mipi_lvds1 {
374 375 376
	#address-cells = <1>;
	#size-cells = <0>;
	pinctrl-names = "default";
377
	pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>;
378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393
	clock-frequency = <100000>;
	status = "okay";

	it6263-1@4c {
		compatible = "ITE,it6263";
		reg = <0x4c>;
	};
};

&lpuart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_lpuart0>;
	status = "okay";
};

&usdhc1 {
394
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
395
	pinctrl-0 = <&pinctrl_usdhc1>;
396 397
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
398 399 400 401 402 403 404
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
405 406 407
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
408 409 410
	bus-width = <4>;
	cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
	wp-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>;
411
	vmmc-supply = <&reg_usdhc2_vmmc>;
412 413
	status = "okay";
};
414 415 416 417 418 419 420 421

&usbotg1 {
	vbus-supply = <&reg_usb_otg1_vbus>;
	srp-disable;
	hnp-disable;
	adp-disable;
	status = "okay";
};
422 423 424

&usb2 {
	status = "okay";
425
};