imx8m_som.h 10.9 KB
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/*
 * Copyright 2017 NXP
 * Copyright 2018 Emcraft Systems
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __IMX8M_SOM_H
#define __IMX8M_SOM_H

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/* #define DEBUG */

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#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>

#ifdef CONFIG_SECURE_BOOT
#define CONFIG_CSF_SIZE			0x2000 /* 8K region */
#endif

#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_TEXT_BASE		0x7E1000
#define CONFIG_SPL_MAX_SIZE		(124 * 1024)
#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	0x300
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1

#ifdef CONFIG_SPL_BUILD
/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/
#define CONFIG_SPL_THERM_SUPPORT
#define CONFIG_SPL_WATCHDOG_SUPPORT
#define CONFIG_SPL_DRIVERS_MISC_SUPPORT
#define CONFIG_SPL_POWER_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_LDSCRIPT		"arch/arm/cpu/armv8/u-boot-spl.lds"
#define CONFIG_SPL_STACK		0x187FF0
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT
#define CONFIG_SPL_BSS_START_ADDR      0x00180000
#define CONFIG_SPL_BSS_MAX_SIZE        0x2000	/* 8 KB */
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#define CONFIG_SPL_STACK_R_ADDR		0x42300000
#define CONFIG_SPL_STACK_R
#define CONFIG_SPL_SEPARATE_BSS		
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#define CONFIG_SYS_SPL_MALLOC_START    0x42200000
#define CONFIG_SYS_SPL_MALLOC_SIZE     0x80000	/* 512 KB */
#define CONFIG_SYS_ICACHE_OFF
#define CONFIG_SYS_DCACHE_OFF

#define CONFIG_MALLOC_F_ADDR		0x182000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */

#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */

#undef CONFIG_DM_MMC
#undef CONFIG_DM_PMIC
#undef CONFIG_DM_PMIC_PFUZE100

#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */

#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG

#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_BD71837
#define CONFIG_POWER_BD71837_I2C_BUS	0
#define CONFIG_POWER_BD71837_I2C_ADDR	0x4B

#if defined(CONFIG_NAND_BOOT)
#define CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SPL_DMA_SUPPORT
#define CONFIG_SPL_NAND_MXS
#define CONFIG_SYS_NAND_U_BOOT_OFFS 	0x8000000 /* Put the FIT out of first 128MB boot area */
#endif
#define CONFIG_SPL_DMA_SUPPORT

#endif /* CONFIG_SPL_BUILD*/

#define CONFIG_REMAKE_ELF

#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_POSTCLK_INIT
#define CONFIG_BOARD_LATE_INIT

/* Flat Device Tree Definitions */
#define CONFIG_OF_BOARD_SETUP

#undef CONFIG_CMD_EXPORTENV
#undef CONFIG_CMD_IMPORTENV
#undef CONFIG_CMD_IMLS

#undef CONFIG_CMD_CRC32
#undef CONFIG_BOOTM_NETBSD

/* ENET Config */
/* ENET1 */
#if defined(CONFIG_CMD_NET)
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_MII
#define CONFIG_ETHPRIME                 "FEC"

#define CONFIG_FEC_MXC
#define FEC_QUIRK_ENET_MAC

#define IMX_FEC_BASE			0x30BE0000

#define CONFIG_PHYLIB

#define CONFIG_FEC_XCV_TYPE             RGMII
#define CONFIG_PHY_REALTEK
#define CONFIG_FEC_MXC_PHYADDR          1

#endif

#ifdef CONFIG_NAND_BOOT
#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:64m(boot),16m(fit),32m(kernel),16m(dtb),8m(misc),-(rootfs) "
#else
#define MFG_NAND_PARTITION ""
#endif

#define CONFIG_MFG_ENV_SETTINGS \
	"mfgtool_args=setenv bootargs console=${console},${baudrate} " \
		"rdinit=/linuxrc " \
		"g_mass_storage.stall=0 g_mass_storage.removable=1 " \
		"g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
		"g_mass_storage.iSerialNumber=\"\" "\
		MFG_NAND_PARTITION \
		"clk_ignore_unused "\
		"\0" \
	"initrd_addr=0x43800000\0" \
	"initrd_high=0xffffffff\0" \
	"bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \

/* Initial environment variables */
#if defined(CONFIG_NAND_BOOT)
#define CONFIG_EXTRA_ENV_SETTINGS \
	CONFIG_MFG_ENV_SETTINGS \
	"fdt_addr=0x43000000\0"			\
	"fdt_high=0xffffffffffffffff\0" \
	"console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200\0" \
	"bootargs=console=${console} ubi.mtd=5 "  \
		"root=ubi0:rootfs rootfstype=ubifs "		     \
		MFG_NAND_PARTITION \
		"\0" \
	"bootcmd=nand read ${loadaddr} 0x5000000 0x1400000;"\
		"nand read ${fdt_addr} 0x7000000 0x100000;"\
		"booti ${loadaddr} - ${fdt_addr}"

#else
#define CONFIG_EXTRA_ENV_SETTINGS		\
	CONFIG_MFG_ENV_SETTINGS \
	"script=boot.scr\0" \
	"image=Image\0" \
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	"fdt_file=dtbs/librem5-evk.dtb\0" \
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	"ethaddr=3C:FB:96:77:88:A0\0" \
	"ip_dyn=no\0" \
	"ipaddr=172.17.33.41\0" \
	"serverip=172.17.0.1\0" \
	"fdt_addr=0x43000000\0"			\
	"fdt_high=0xffffffffffffffff\0"		\
	"boot_fdt=try\0" \
	"initrd_addr=0x43800000\0"		\
	"initrd_high=0xffffffffffffffff\0" \
	"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
	"mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
	"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
	"mmcautodetect=yes\0" \
	"args_common=console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200 " \
	"video=HDMI-A-1:1920x1080-32@60\0" \
	"args_quiet=setenv bootargs ${args_common} quiet=quiet\0" \
	"args_verbose=setenv bootargs ${args_common} ignore_loglevel\0" \
	"args=run args_quiet\0" \
	"netargs=setenv bootargs ${bootargs} " \
                "root=/dev/nfs nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
	"mmcargs=setenv bootargs ${bootargs} root=${mmcroot}\0 " \
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	"loadbootscript=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
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	"bootscript=echo Running bootscript from mmc ...; " \
		"source\0" \
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	"loadimage=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
	"loadfdt=ext2load mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
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	"rtos_file=imx8mq_m4_TCM_rpmsg_lite_str_echo_rtos.bin\0"       \
	"rtos_bootaddr=0x7e0000\0"				       \
	"rtosmmcboot=fatload mmc ${mmcdev}:${mmcpart} ${rtos_bootaddr} "  \
		"${rtos_file} && bootaux ${rtos_bootaddr}\0"	       \
	"rtosnetboot=tftp ${rtos_bootaddr} ${rtos_file} && "\
		"bootaux ${rtos_bootaddr}\0"\
	"rtosboot=run rtosmmcboot\0" \
	"mmcboot=echo Booting from mmc ...; " \
		"mmc dev ${mmcdev}; if mmc rescan; then "	\
		"if run loadbootscript; then "			\
			"run bootscript; "		       \
		   "else " \
			"run rtosboot; "				      \
			"run args mmcargs addip loadfdt && run loadimage && " \
			"booti ${loadaddr} - ${fdt_addr};" \
		    "fi;" \
		"fi\0" \
	"addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}:" \
		"${netmask}:${hostname}:eth0:off\0" \
	"netboot=echo Booting from net ...; " \
		"run args mmcargs;  " \
		"if test ${ip_dyn} = yes; then " \
			"setenv get_cmd dhcp; " \
		"else " \
			"setenv get_cmd tftp; " \
		"fi; " \
		"run rtosboot; " \
		"${get_cmd} ${loadaddr} ${image} && " \
		"${get_cmd} ${fdt_addr} ${fdt_file} && " \
		"run addip && booti ${loadaddr} - ${fdt_addr};\0"
#define CONFIG_BOOTCOMMAND "run mmcboot"
#endif

/* Link Definitions */
#define CONFIG_LOADADDR			0x40480000
#define CONFIG_SYS_TEXT_BASE		0x40200000

#define CONFIG_SYS_LOAD_ADDR           CONFIG_LOADADDR

#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000
#define CONFIG_SYS_INIT_RAM_SIZE        0x80000
#define CONFIG_SYS_INIT_SP_OFFSET \
        (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
        (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_OFFSET               (64 * SZ_64K)
#define CONFIG_ENV_SIZE			0x1000
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV		1   /* USDHC2 */
#define CONFIG_MMCROOT			"/dev/mmcblk1p2"  /* USDHC2 */

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		((CONFIG_ENV_SIZE + (2*1024)) * 1024)

#define CONFIG_SYS_SDRAM_BASE           0x40000000
#define PHYS_SDRAM                      0x40000000
#if defined(CONFIG_TARGET_EMCRAFT_IMX8M_LPDDR4_SOM)
#define PHYS_SDRAM_SIZE			0x40000000 /* 1GB LPDDR4 one Rank */
#elif defined(CONFIG_TARGET_EMCRAFT_IMX8M_LPDDR4_2GB_SOM)
#define PHYS_SDRAM_SIZE			0x80000000 /* 2GB LPDDR4 one Rank */
#elif defined(CONFIG_TARGET_EMCRAFT_IMX8M_LPDDR4_3GB_SOM)
#define PHYS_SDRAM_SIZE			0xc0000000 /* 3GB LPDDR4 one Rank */
#elif defined(CONFIG_TARGET_EMCRAFT_IMX8M_SOM)
#define PHYS_SDRAM_SIZE			0x20000000 /* 512MB DDR3L one Rank */
#elif defined(CONFIG_TARGET_EMCRAFT_IMX8M_LPDDR4_800MHZ_2GB_SOM)
#define PHYS_SDRAM_SIZE			0x80000000 /* 2GB LPDDR4 one Rank */
#else
#error "i.MX8M-SOM installed DDR size is not defined"
#endif
#define CONFIG_NR_DRAM_BANKS		1

#define CONFIG_SYS_MEMTEST_START	0x40000000
/* Save upper 2MB for U-Boot code and data */
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
			PHYS_SDRAM_SIZE - 32*1024*1024)
#define CONFIG_SYS_ALT_MEMTEST

#define CONFIG_BAUDRATE			115200

#define CONFIG_MXC_UART
#define CONFIG_MXC_UART_BASE		UART1_BASE_ADDR

/* Monitor Command Prompt */
#undef CONFIG_SYS_PROMPT
#define CONFIG_SYS_PROMPT		"u-boot=> "
#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
#define CONFIG_AUTO_COMPLETE
#define CONFIG_SYS_CBSIZE              1024
#define CONFIG_SYS_MAXARGS             64
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_CMDLINE_EDITING

#define CONFIG_IMX_BOOTAUX

#define CONFIG_CMD_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_FSL_USDHC

#define CONFIG_SYS_FSL_USDHC_NUM	2
#define CONFIG_SYS_FSL_ESDHC_ADDR       0

#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_CMD_FAT

#define CONFIG_SUPPORT_EMMC_BOOT	/* eMMC specific */
#define CONFIG_SYS_MMC_IMG_LOAD_PART	1

#define CONFIG_FSL_QSPI    /* enable the QUADSPI driver */

#ifdef CONFIG_FSL_QSPI
#define CONFIG_CMD_SF
#define	CONFIG_SPI_FLASH
#define	CONFIG_SPI_FLASH_GIGADEVICE
#define	CONFIG_SF_DEFAULT_BUS		0
#define	CONFIG_SF_DEFAULT_CS		1
#define	CONFIG_SF_DEFAULT_SPEED		40000000
#define	CONFIG_SF_DEFAULT_MODE		SPI_MODE_0

#define FSL_QSPI_FLASH_SIZE		(SZ_2M)
#define FSL_QSPI_FLASH_NUM		2
#endif

#define CONFIG_MXC_GPIO

#define CONFIG_MXC_OCOTP
#define CONFIG_CMD_FUSE

/* I2C Configs */
#define CONFIG_SYS_I2C_SPEED		  100000

/* USB configs */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_HAS_FSL_XHCI_USB

#ifdef CONFIG_HAS_FSL_XHCI_USB
#define CONFIG_USB_XHCI_IMX8M
#define CONFIG_USB_XHCI_DWC3
#define CONFIG_USB_XHCI_HCD
#define CONFIG_USB_MAX_CONTROLLER_COUNT         1
#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS      2
#endif

#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_EXT2

#define CONFIG_USBD_HS

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/*
#define CONFIG_USB_DWC3
#define CONFIG_USB_DWC3_GADGET
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#define CONFIG_USB_GADGET
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#define CONFIG_CMD_USB_MASS_STORAGE
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#define CONFIG_USB_GADGET_MASS_STORAGE
#define CONFIG_USB_GADGET_DOWNLOAD
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*/
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#define CONFIG_USB_GADGET_VBUS_DRAW 2
/* #define CONFIG_USB_GADGET_DUALSPEED
#define CONFIG_USB_FUNCTION_MASS_STORAGE
*/
/*
#define CONFIG_G_DNL_VENDOR_NUM		0x0525
#define CONFIG_G_DNL_PRODUCT_NUM	0xa4a5
#define CONFIG_G_DNL_MANUFACTURER	"FSL"
*/

#endif

#define CONFIG_OF_SYSTEM_SETUP

#endif