MPC8360EMDS.h 19.2 KB
Newer Older
1 2 3 4 5 6 7 8 9 10 11 12
/*
 * Copyright (C) 2006 Freescale Semiconductor, Inc.
 *
 * Dave Liu <daveliu@freescale.com>
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
Wolfgang Denk's avatar
Wolfgang Denk committed
13
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1 /* E300 family */
#define CONFIG_QE		1 /* Has QE */
30
#define CONFIG_MPC83xx		1 /* MPC83xx family */
31 32
#define CONFIG_MPC8360		1 /* MPC8360 CPU specific */
#define CONFIG_MPC8360EMDS	1 /* MPC8360EMDS board specific */
33 34
#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */
35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

/*
 * System Clock Setup
 */
#ifdef CONFIG_PCISLAVE
#define CONFIG_83XX_PCICLK	66000000 /* in HZ */
#else
#define CONFIG_83XX_CLKIN	66000000 /* in Hz */
#endif

#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ	66000000
#endif

/*
 * Hardware Reset Configuration Word
 */
52
#define CONFIG_SYS_HRCW_LOW (\
53 54 55 56 57 58 59 60 61 62
	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
	HRCWL_DDR_TO_SCB_CLK_1X1 |\
	HRCWL_CSB_TO_CLKIN_4X1 |\
	HRCWL_VCO_1X2 |\
	HRCWL_CE_PLL_VCO_DIV_4 |\
	HRCWL_CE_PLL_DIV_1X1 |\
	HRCWL_CE_TO_PLL_1X6 |\
	HRCWL_CORE_TO_CSB_2X1)

#ifdef CONFIG_PCISLAVE
63
#define CONFIG_SYS_HRCW_HIGH (\
64 65 66 67 68 69 70 71 72
	HRCWH_PCI_AGENT |\
	HRCWH_PCI1_ARBITER_DISABLE |\
	HRCWH_PCICKDRV_DISABLE |\
	HRCWH_CORE_ENABLE |\
	HRCWH_FROM_0XFFF00100 |\
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_ROM_LOC_LOCAL_16BIT)
#else
73
#define CONFIG_SYS_HRCW_HIGH (\
74 75 76 77 78 79 80 81 82 83 84 85 86
	HRCWH_PCI_HOST |\
	HRCWH_PCI1_ARBITER_ENABLE |\
	HRCWH_PCICKDRV_ENABLE |\
	HRCWH_CORE_ENABLE |\
	HRCWH_FROM_0X00000100 |\
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_ROM_LOC_LOCAL_16BIT)
#endif

/*
 * System IO Config
 */
87 88
#define CONFIG_SYS_SICRH		0x00000000
#define CONFIG_SYS_SICRL		0x40000000
89 90

#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
91
#define CONFIG_BOARD_EARLY_INIT_R
92 93 94 95

/*
 * IMMR new address
 */
96
#define CONFIG_SYS_IMMR		0xE0000000
97 98 99 100

/*
 * DDR Setup
 */
101 102
#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
103
#define CONFIG_SYS_SDRAM_BASE2		(CONFIG_SYS_SDRAM_BASE + 0x10000000) /* + 256M */
104 105
#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	(DDR_SDRAM_CLK_CNTL_SS_EN | \
106
				DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
107

108
#define CONFIG_SYS_83XX_DDR_USES_CS0
109

110
#define CONFIG_DDR_ECC		/* support DDR ECC function */
111 112
#define CONFIG_DDR_ECC_CMD	/* Use DDR ECC user commands */

113 114 115
/*
 * DDRCDR - DDR Control Driver Register
 */
116
#define CONFIG_SYS_DDRCDR_VALUE	0x80080001
117

118 119 120 121 122 123 124 125 126 127
#define CONFIG_SPD_EEPROM	/* Use SPD EEPROM for DDR setup */
#if defined(CONFIG_SPD_EEPROM)
/*
 * Determine DDR configuration from I2C interface.
 */
#define SPD_EEPROM_ADDRESS	0x52 /* DDR SODIMM */
#else
/*
 * Manually set up DDR parameters
 */
128
#define CONFIG_SYS_DDR_SIZE		256 /* MB */
129
#if defined(CONFIG_DDR_II)
130 131 132 133 134 135 136 137 138 139 140 141 142
#define CONFIG_SYS_DDRCDR		0x80080001
#define CONFIG_SYS_DDR_CS0_BNDS	0x0000000f
#define CONFIG_SYS_DDR_CS0_CONFIG	0x80330102
#define CONFIG_SYS_DDR_TIMING_0	0x00220802
#define CONFIG_SYS_DDR_TIMING_1	0x38357322
#define CONFIG_SYS_DDR_TIMING_2	0x2f9048c8
#define CONFIG_SYS_DDR_TIMING_3	0x00000000
#define CONFIG_SYS_DDR_CLK_CNTL	0x02000000
#define CONFIG_SYS_DDR_MODE		0x47d00432
#define CONFIG_SYS_DDR_MODE2		0x8000c000
#define CONFIG_SYS_DDR_INTERVAL	0x03cf0080
#define CONFIG_SYS_DDR_SDRAM_CFG	0x43000000
#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
143
#else
144 145 146 147 148 149
#define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_9)
#define CONFIG_SYS_DDR_TIMING_1	0x37344321 /* tCL-tRCD-tRP-tRAS=2.5-3-3-7 */
#define CONFIG_SYS_DDR_TIMING_2	0x00000800 /* may need tuning */
#define CONFIG_SYS_DDR_CONTROL		0x42008000 /* Self refresh,2T timing */
#define CONFIG_SYS_DDR_MODE		0x20000162 /* DLL,normal,seq,4/2.5 */
#define CONFIG_SYS_DDR_INTERVAL	0x045b0100 /* page mode */
150
#endif
151
#endif
152 153 154 155

/*
 * Memory test
 */
156 157 158
#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START	0x00000000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END		0x00100000
159 160 161 162 163

/*
 * The reserved memory
 */

164
#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE /* start of monitor */
165

166 167
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
168
#else
169
#undef	CONFIG_SYS_RAMBOOT
170 171
#endif

172
/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
173
#define CONFIG_SYS_MONITOR_LEN		(384 * 1024) /* Reserve 384 kB for Mon */
174
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024) /* Reserved for malloc */
175 176 177 178

/*
 * Initial RAM Base Address Setup
 */
179 180 181 182 183
#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_END	0x1000 /* End of used area in RAM */
#define CONFIG_SYS_GBL_DATA_SIZE	0x100 /* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
184 185 186 187

/*
 * Local Bus Configuration & Clock Setup
 */
188 189
#define CONFIG_SYS_LCRR		(LCRR_DBYP | LCRR_CLKDIV_4)
#define CONFIG_SYS_LBC_LBCR		0x00000000
190 191 192 193

/*
 * FLASH on the Local Bus
 */
194
#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
195
#define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
196 197 198
#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE		32 /* max FLASH size is 32M */
#define CONFIG_SYS_FLASH_PROTECTION	1		/* Use h/w Flash protection. */
199
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
200

201 202
#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE /* Window base at flash base */
#define CONFIG_SYS_LBLAWAR0_PRELIM	0x80000018 /* 32MB window size */
203

204
#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \
205 206
			(2 << BR_PS_SHIFT) | /* 16 bit port size */ \
			BR_V)	/* valid */
207
#define CONFIG_SYS_OR0_PRELIM		((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \
208
				OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \
209
				OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
210

211 212
#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	256 /* max sectors per device */
213

214
#undef	CONFIG_SYS_FLASH_CHECKSUM
215 216 217 218

/*
 * BCSR on the Local Bus
 */
219 220 221
#define CONFIG_SYS_BCSR		0xF8000000
#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_BCSR /* Access window base at BCSR base */
#define CONFIG_SYS_LBLAWAR1_PRELIM	0x8000000F /* Access window size 64K */
222

223 224
#define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_BCSR|0x00000801) /* Port size=8bit, MSEL=GPCM */
#define CONFIG_SYS_OR1_PRELIM		0xFFFFE9f7 /* length 32K */
225 226 227 228

/*
 * SDRAM on the Local Bus
 */
229 230
#define CONFIG_SYS_LBC_SDRAM_BASE	0xF0000000	/* SDRAM base address */
#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
231

232
#define CONFIG_SYS_LB_SDRAM		/* if board has SRDAM on local bus */
233

234
#ifdef CONFIG_SYS_LB_SDRAM
235 236
#define CONFIG_SYS_LBLAWBAR2		0
#define CONFIG_SYS_LBLAWAR2		0x80000019 /* 64MB */
237 238 239 240 241 242

/*local bus BR2, OR2 definition for SDRAM if soldered on the EPB board */
/*
 * Base Register 2 and Option Register 2 configure SDRAM.
 *
 * For BR2, need:
243
 *    Base address = BR[0:16] = dynamic
244 245 246 247 248
 *    port size = 32-bits = BR2[19:20] = 11
 *    no parity checking = BR2[21:22] = 00
 *    SDRAM for MSEL = BR2[24:26] = 011
 *    Valid = BR[31] = 1
 *
Wolfgang Denk's avatar
Wolfgang Denk committed
249
 * 0	4    8	  12   16   20	 24   28
250
 * xxxx xxxx xxxx xxxx x001 1000 0110 0001 = 00001861
251 252
 */

253
#define CONFIG_SYS_BR2		0x00001861 /*Port size=32bit, MSEL=SDRAM */
254 255

/*
256
 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
257 258 259 260 261
 *
 * For OR2, need:
 *    64MB mask for AM, OR2[0:7] = 1111 1100
 *		   XAM, OR2[17:18] = 11
 *    9 columns OR2[19-21] = 010
Wolfgang Denk's avatar
Wolfgang Denk committed
262
 *    13 rows	OR2[23-25] = 100
263 264
 *    EAD set for extra time OR[31] = 1
 *
Wolfgang Denk's avatar
Wolfgang Denk committed
265
 * 0	4    8	  12   16   20	 24   28
266 267 268
 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 */

269
#define CONFIG_SYS_OR2		0xfc006901
270

271 272
#define CONFIG_SYS_LBC_LSRT	0x32000000 /* LB sdram refresh timer, about 6us */
#define CONFIG_SYS_LBC_MRTPR	0x20000000 /* LB refresh timer prescal, 266MHz/32 */
273

274
#define CONFIG_SYS_LBC_LSDMR_COMMON	0x0063b723
275 276 277 278

/*
 * SDRAM Controller configuration sequence.
 */
279 280 281 282 283
#define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
#define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
#define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
#define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
#define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
284 285 286 287 288 289

#endif

/*
 * Windows to access PIB via local bus
 */
290 291
#define CONFIG_SYS_LBLAWBAR3_PRELIM	0xf8010000 /* windows base 0xf8010000 */
#define CONFIG_SYS_LBLAWAR3_PRELIM	0x8000000e /* windows size 32KB */
292 293 294 295

/*
 * CS4 on Local Bus, to PIB
 */
296 297
#define CONFIG_SYS_BR4_PRELIM	0xf8010801 /* CS4 base address at 0xf8010000 */
#define CONFIG_SYS_OR4_PRELIM	0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
298 299 300 301

/*
 * CS5 on Local Bus, to PIB
 */
302 303
#define CONFIG_SYS_BR5_PRELIM	0xf8008801 /* CS5 base address at 0xf8008000 */
#define CONFIG_SYS_OR5_PRELIM	0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
304 305 306 307 308 309

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX	1
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
310 311 312 313
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
314

315
#define CONFIG_SYS_BAUDRATE_TABLE  \
316 317
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

318 319
#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)
320

321
#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
322
/* Use the HUSH parser */
323 324 325
#define CONFIG_SYS_HUSH_PARSER
#ifdef	CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
326 327
#endif

328
/* pass open firmware flat tree */
329
#define CONFIG_OF_LIBFDT	1
330
#define CONFIG_OF_BOARD_SETUP	1
331
#define CONFIG_OF_STDOUT_VIA_ALIAS	1
332

333 334 335
/* I2C */
#define CONFIG_HARD_I2C		/* I2C with hardware support */
#undef	CONFIG_SOFT_I2C		/* I2C bit-banged */
336
#define CONFIG_FSL_I2C
337 338 339 340 341
#define CONFIG_SYS_I2C_SPEED	400000	/* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE	0x7F
#define CONFIG_SYS_I2C_NOPROBES	{0x52} /* Don't probe these addrs */
#define CONFIG_SYS_I2C_OFFSET	0x3000
#define CONFIG_SYS_I2C2_OFFSET 0x3100
342 343 344 345 346

/*
 * Config on-board RTC
 */
#define CONFIG_RTC_DS1374		/* use ds1374 rtc via i2c */
347
#define CONFIG_SYS_I2C_RTC_ADDR	0x68	/* at address 0x68 */
348 349 350 351 352

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
353 354 355 356 357 358 359 360 361
#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000 /* 256M */
#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000 /* 256M */
#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS		0xE0300000
#define CONFIG_SYS_PCI1_IO_SIZE		0x100000 /* 1M */
362

363 364 365
#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
#define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000
366 367 368 369 370 371


#ifdef CONFIG_PCI

#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP		/* do pci plug-and-play */
372
#define CONFIG_83XX_PCI_STREAMING
373 374 375

#undef CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
376
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
377 378 379 380 381 382 383 384

#endif	/* CONFIG_PCI */


#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI	1
#endif

Dave Liu's avatar
Dave Liu committed
385 386 387 388
/*
 * QE UEC ethernet configuration
 */
#define CONFIG_UEC_ETH
389
#define CONFIG_ETHPRIME		"FSL UEC0"
Dave Liu's avatar
Dave Liu committed
390 391 392 393 394
#define CONFIG_PHY_MODE_NEED_CHANGE

#define CONFIG_UEC_ETH1		/* GETH1 */

#ifdef CONFIG_UEC_ETH1
395 396 397 398 399 400
#define CONFIG_SYS_UEC1_UCC_NUM	0	/* UCC1 */
#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK_NONE
#define CONFIG_SYS_UEC1_TX_CLK		QE_CLK9
#define CONFIG_SYS_UEC1_ETH_TYPE	GIGA_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR	0
#define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_GMII
Dave Liu's avatar
Dave Liu committed
401 402 403 404 405
#endif

#define CONFIG_UEC_ETH2		/* GETH2 */

#ifdef CONFIG_UEC_ETH2
406 407 408 409 410 411
#define CONFIG_SYS_UEC2_UCC_NUM	1	/* UCC2 */
#define CONFIG_SYS_UEC2_RX_CLK		QE_CLK_NONE
#define CONFIG_SYS_UEC2_TX_CLK		QE_CLK4
#define CONFIG_SYS_UEC2_ETH_TYPE	GIGA_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR	1
#define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_GMII
Dave Liu's avatar
Dave Liu committed
412 413
#endif

414 415 416 417
/*
 * Environment
 */

418
#ifndef CONFIG_SYS_RAMBOOT
419
	#define CONFIG_ENV_IS_IN_FLASH	1
420
	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
421 422
	#define CONFIG_ENV_SECT_SIZE	0x20000
	#define CONFIG_ENV_SIZE		0x2000
423
#else
424
	#define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
425
	#define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
426
	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
427
	#define CONFIG_ENV_SIZE		0x2000
428 429 430
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
431
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
432

433 434 435 436 437 438 439 440 441
/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


442 443 444 445 446 447 448 449
/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_ASKENV
450
#define CONFIG_CMD_SDRAM
451

452
#if defined(CONFIG_PCI)
453
    #define CONFIG_CMD_PCI
454
#endif
455

456
#if defined(CONFIG_SYS_RAMBOOT)
457
    #undef CONFIG_CMD_SAVEENV
458
    #undef CONFIG_CMD_LOADS
459 460 461 462 463 464 465 466
#endif


#undef CONFIG_WATCHDOG		/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
467 468 469
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */
470

471
#if defined(CONFIG_CMD_KGDB)
472
	#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */
473
#else
474
	#define CONFIG_SYS_CBSIZE	256 /* Console I/O Buffer Size */
475 476
#endif

477 478 479 480
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */
#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1ms ticks */
481 482 483 484 485 486

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
487
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */
488 489 490 491

/*
 * Core HID Setup
 */
492 493 494
#define CONFIG_SYS_HID0_INIT		0x000000000
#define CONFIG_SYS_HID0_FINAL		HID0_ENABLE_MACHINE_CHECK
#define CONFIG_SYS_HID2		HID2_HBE
495 496 497 498 499

/*
 * MMU Setup
 */

500 501
#define CONFIG_HIGH_BATS	1	/* High BATs supported */

502
/* DDR/LBC SDRAM: cacheable */
503 504 505 506
#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U
507 508

/* IMMRBAR & PCI IO: cache-inhibit and guarded */
509
#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR | BATL_PP_10 | \
510
			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
511 512 513
#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U
514 515

/* BCSR: cache-inhibit and guarded */
516
#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_BCSR | BATL_PP_10 | \
517
			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
518 519 520
#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_BCSR | BATU_BL_128K | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U
521 522

/* FLASH: icache cacheable, but dcache-inhibit and guarded */
523 524 525
#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT3L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
526
			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
527
#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U
528

529 530 531
/* DDR/LBC SDRAM next 256M: cacheable */
#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_SDRAM_BASE2 | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_SDRAM_BASE2 | BATU_BL_256M | BATU_VS | BATU_VP)
532 533
#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U
534 535

/* Stack in dcache: cacheable, no memory coherence */
536 537 538 539
#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
540 541 542

#ifdef CONFIG_PCI
/* PCI MEM space: cacheable */
543 544
#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
545 546
#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
547
/* PCI MMIO space: cache-inhibit and guarded */
548
#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_PCI1_MMIO_PHYS | BATL_PP_10 | \
549
			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
550
#define CONFIG_SYS_IBAT7U	(CONFIG_SYS_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
551 552
#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
553
#else
554 555 556 557 558 559 560 561
#define CONFIG_SYS_IBAT6L	(0)
#define CONFIG_SYS_IBAT6U	(0)
#define CONFIG_SYS_IBAT7L	(0)
#define CONFIG_SYS_IBAT7U	(0)
#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
562 563 564 565 566 567 568 569 570 571
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02 /* Software reboot */

572
#if defined(CONFIG_CMD_KGDB)
573 574 575 576 577 578 579 580 581 582 583
#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

/*
 * Environment Configuration
 */

#define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_UEC_ETH)
584
#define CONFIG_HAS_ETH0
585 586
#define CONFIG_ETHADDR	00:04:9f:ef:01:01
#define CONFIG_HAS_ETH1
Wolfgang Denk's avatar
Wolfgang Denk committed
587
#define CONFIG_ETH1ADDR 00:04:9f:ef:01:02
588 589
#endif

Wolfgang Denk's avatar
Wolfgang Denk committed
590
#define CONFIG_BAUDRATE 115200
591

592
#define CONFIG_LOADADDR 800000	/* default location for tftp and bootm */
593

Wolfgang Denk's avatar
Wolfgang Denk committed
594 595
#define CONFIG_BOOTDELAY 6	/* -1 disables auto-boot */
#undef	CONFIG_BOOTARGS		/* the boot command will set bootargs */
596

Wolfgang Denk's avatar
Wolfgang Denk committed
597 598 599 600
#define CONFIG_EXTRA_ENV_SETTINGS					\
   "netdev=eth0\0"							\
   "consoledev=ttyS0\0"							\
   "ramdiskaddr=1000000\0"						\
601
   "ramdiskfile=ramfs.83xx\0"						\
602
   "fdtaddr=780000\0"							\
603
   "fdtfile=mpc836x_mds.dtb\0"						\
604
   ""
605

Wolfgang Denk's avatar
Wolfgang Denk committed
606 607 608
#define CONFIG_NFSBOOTCOMMAND						\
   "setenv bootargs root=/dev/nfs rw "					\
      "nfsroot=$serverip:$rootpath "					\
609
      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
Wolfgang Denk's avatar
Wolfgang Denk committed
610 611
      "console=$consoledev,$baudrate $othbootargs;"			\
   "tftp $loadaddr $bootfile;"						\
612 613
   "tftp $fdtaddr $fdtfile;"						\
   "bootm $loadaddr - $fdtaddr"
614

615
#define CONFIG_RAMBOOTCOMMAND						\
Wolfgang Denk's avatar
Wolfgang Denk committed
616 617 618 619
   "setenv bootargs root=/dev/ram rw "					\
      "console=$consoledev,$baudrate $othbootargs;"			\
   "tftp $ramdiskaddr $ramdiskfile;"					\
   "tftp $loadaddr $bootfile;"						\
620 621 622
   "tftp $fdtaddr $fdtfile;"						\
   "bootm $loadaddr $ramdiskaddr $fdtaddr"

623 624 625 626

#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND

#endif	/* __CONFIG_H */