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/*
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 * (C) Copyright 2004-2006 Freescale Semiconductor, Inc.
 *
 * MPC83xx Internal Memory Map
 *
 * History :
 * 20060601: Daveliu (daveliu@freescale.com)
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 *	     TanyaJiang (tanya.jiang@freescale.com)
 *	     Unified variable names for mpc83xx
 * 2005	   : Mandy Lavi (mandy.lavi@freescale.com)
 *	     support for mpc8360e
 * 2004	   : Eran Liberty (liberty@freescale.com)
 *	     Initialized for mpc8349
 *	     based on:
 *	     MPC8260 Internal Memory Map
 *	     Copyright (c) 1999 Dan Malek (dmalek@jlc.net)
 *	     MPC85xx Internal Memory Map
 *	     Copyright(c) 2002,2003 Motorola Inc.
 *	     Xianghua Xiao (x.xiao@motorola.com)
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 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
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 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
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 *
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 */
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#ifndef __IMMAP_83xx__
#define __IMMAP_83xx__
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#include <config.h>
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#include <asm/types.h>
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#include <asm/fsl_i2c.h>
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/*
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 * Local Access Window.
 */
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typedef struct law83xx {
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	u32 bar;		/* LBIU local access window base address register */
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/* Identifies the 20 most-significant address bits of the base of local
 * access window n. The specified base address should be aligned to the
 * window size, as defined by LBLAWARn[SIZE].
 */
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#define LAWBAR_BAR	   0xFFFFF000
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#define LAWBAR_RES	     ~(LAWBAR_BAR)
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	u32 ar;			/* LBIU local access window attribute register */
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} law83xx_t;
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/*
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 * System configuration registers.
 */
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typedef struct sysconf83xx {
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	u32 immrbar;		/* Internal memory map base address register */
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	u8 res0[0x04];
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	u32 altcbar;		/* Alternate configuration base address register */
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/* Identifies the12 most significant address bits of an alternate base
 * address used for boot sequencer configuration accesses.
 */
#define ALTCBAR_BASE_ADDR     0xFFF00000
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#define ALTCBAR_RES	      ~(ALTCBAR_BASE_ADDR)	/* Reserved. Write has no effect, read returns 0. */
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	u8 res1[0x14];
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	law83xx_t lblaw[4];	/* LBIU local access window */
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	u8 res2[0x20];
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	law83xx_t pcilaw[2];	/* PCI local access window */
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	u8 res3[0x30];
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	law83xx_t ddrlaw[2];	/* DDR local access window */
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	u8 res4[0x50];
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	u32 sgprl;		/* System General Purpose Register Low */
	u32 sgprh;		/* System General Purpose Register High */
	u32 spridr;		/* System Part and Revision ID Register */
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#define SPRIDR_PARTID	      0xFFFF0000	/* Part Identification. */
#define SPRIDR_REVID	      0x0000FFFF	/* Revision Identification. */
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	u8 res5[0x04];
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	u32 spcr;		/* System Priority Configuration Register */
#define SPCR_PCIHPE   0x10000000	/* PCI Highest Priority Enable. */
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#define SPCR_PCIHPE_SHIFT	(31-3)
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#define SPCR_PCIPR    0x03000000	/* PCI bridge system bus request priority. */
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#define SPCR_PCIPR_SHIFT	(31-7)
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#define SPCR_OPT      0x00800000	/* Optimize */
#define SPCR_TBEN     0x00400000	/* E300 PowerPC core time base unit enable. */
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#define SPCR_TBEN_SHIFT		(31-9)
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#define SPCR_COREPR   0x00300000	/* E300 PowerPC Core system bus request priority. */
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#define SPCR_COREPR_SHIFT	(31-11)
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#if defined (CONFIG_MPC8349)
#define SPCR_TSEC1DP  0x00003000	/* TSEC1 data priority. */
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#define SPCR_TSEC1DP_SHIFT	(31-19)
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#define SPCR_TSEC1BDP 0x00000C00	/* TSEC1 buffer descriptor priority. */
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#define SPCR_TSEC1BDP_SHIFT	(31-21)
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#define SPCR_TSEC1EP  0x00000300	/* TSEC1 emergency priority. */
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#define SPCR_TSEC1EP_SHIFT	(31-23)
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#define SPCR_TSEC2DP  0x00000030	/* TSEC2 data priority. */
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#define SPCR_TSEC2DP_SHIFT	(31-27)
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#define SPCR_TSEC2BDP 0x0000000C	/* TSEC2 buffer descriptor priority. */
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#define SPCR_TSEC2BDP_SHIFT	(31-29)
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#define SPCR_TSEC2EP  0x00000003	/* TSEC2 emergency priority. */
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#define SPCR_TSEC2EP_SHIFT	(31-31)
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#define SPCR_RES      ~(SPCR_PCIHPE | SPCR_PCIPR | SPCR_TBEN | SPCR_COREPR \
			| SPCR_TSEC1DP | SPCR_TSEC1BDP | SPCR_TSEC1EP \
			| SPCR_TSEC2DP | SPCR_TSEC2BDP | SPCR_TSEC2EP)
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#elif defined (CONFIG_MPC8360)
#define SPCR_RES      ~(SPCR_PCIHPE|SPCR_PCIPR|SPCR_OPT|SPCR_TBEN|SPCR_COREPR)
#endif
	u32 sicrl;		/* System General Purpose Register Low */
#if defined (CONFIG_MPC8349)
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#define SICRL_LDP_A   0x80000000
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#define SICRL_USB1    0x40000000
#define SICRL_USB0    0x20000000
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#define SICRL_UART    0x0C000000
#define SICRL_GPIO1_A 0x02000000
#define SICRL_GPIO1_B 0x01000000
#define SICRL_GPIO1_C 0x00800000
#define SICRL_GPIO1_D 0x00400000
#define SICRL_GPIO1_E 0x00200000
#define SICRL_GPIO1_F 0x00180000
#define SICRL_GPIO1_G 0x00040000
#define SICRL_GPIO1_H 0x00020000
#define SICRL_GPIO1_I 0x00010000
#define SICRL_GPIO1_J 0x00008000
#define SICRL_GPIO1_K 0x00004000
#define SICRL_GPIO1_L 0x00003000
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#define SICRL_RES ~(SICRL_LDP_A | SICRL_USB0 | SICRL_USB1 | SICRL_UART \
			| SICRL_GPIO1_A | SICRL_GPIO1_B | SICRL_GPIO1_C \
			| SICRL_GPIO1_D | SICRL_GPIO1_E | SICRL_GPIO1_F \
			| SICRL_GPIO1_G | SICRL_GPIO1_H | SICRL_GPIO1_I \
			| SICRL_GPIO1_J | SICRL_GPIO1_K | SICRL_GPIO1_L )
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#elif defined (CONFIG_MPC8360)
#define SICRL_LDP_A   0xC0000000
#define SICRL_LCLK_1  0x10000000
#define SICRL_LCLK_2  0x08000000
#define SICRL_SRCID_A 0x03000000
#define SICRL_IRQ_CKSTP_A 0x00C00000
#define SICRL_RES     ~(SICRL_LDP_A | SICRL_LCLK_1 | SICRL_LCLK_2 | \
			SICRL_SRCID_A | SICRL_IRQ_CKSTP_A)
#endif
	u32 sicrh;		/* System General Purpose Register High */
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#define SICRH_DDR     0x80000000
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#if defined (CONFIG_MPC8349)
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#define SICRH_TSEC1_A 0x10000000
#define SICRH_TSEC1_B 0x08000000
#define SICRH_TSEC1_C 0x04000000
#define SICRH_TSEC1_D 0x02000000
#define SICRH_TSEC1_E 0x01000000
#define SICRH_TSEC1_F 0x00800000
#define SICRH_TSEC2_A 0x00400000
#define SICRH_TSEC2_B 0x00200000
#define SICRH_TSEC2_C 0x00100000
#define SICRH_TSEC2_D 0x00080000
#define SICRH_TSEC2_E 0x00040000
#define SICRH_TSEC2_F 0x00020000
#define SICRH_TSEC2_G 0x00010000
#define SICRH_TSEC2_H 0x00008000
#define SICRH_GPIO2_A 0x00004000
#define SICRH_GPIO2_B 0x00002000
#define SICRH_GPIO2_C 0x00001000
#define SICRH_GPIO2_D 0x00000800
#define SICRH_GPIO2_E 0x00000400
#define SICRH_GPIO2_F 0x00000200
#define SICRH_GPIO2_G 0x00000180
#define SICRH_GPIO2_H 0x00000060
#define SICRH_TSOBI1  0x00000002
#define SICRH_TSOBI2  0x00000001
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#define SICRH_RES     ~(  SICRH_DDR | SICRH_TSEC1_A | SICRH_TSEC1_B \
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			| SICRH_TSEC1_C | SICRH_TSEC1_D | SICRH_TSEC1_E \
			| SICRH_TSEC1_F | SICRH_TSEC2_A | SICRH_TSEC2_B \
			| SICRH_TSEC2_C | SICRH_TSEC2_D | SICRH_TSEC2_E \
			| SICRH_TSEC2_F | SICRH_TSEC2_G | SICRH_TSEC2_H \
			| SICRH_GPIO2_A | SICRH_GPIO2_B | SICRH_GPIO2_C \
			| SICRH_GPIO2_D | SICRH_GPIO2_E | SICRH_GPIO2_F \
			| SICRH_GPIO2_G | SICRH_GPIO2_H | SICRH_TSOBI1 \
			| SICRH_TSOBI2)
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#elif defined (CONFIG_MPC8360)
#define SICRH_SECONDARY_DDR 0x40000000
#define SICRH_SDDROE   0x02000000	/* SDDRIOE bit from reset configuration word high. */
#define SICRH_UC1EOBI  0x00000004	/* UCC1 Ethernet Output Buffer Impedance. */
#define SICRH_UC2E1OBI 0x00000002	/* UCC2 Ethernet pin option 1 Output Buffer Impedance. */
#define SICRH_UC2E2OBI 0x00000001	/* UCC2 Ethernet pin option 2 Output Buffer Impedance. */
#define SICRH_RES     ~(SICRH_DDR | SICRH_SECONDARY_DDR | SICRH_SDDROE | \
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			SICRH_UC2E1OBI | SICRH_UC2E2OBI | SICRH_UC2E2OBI)
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#endif
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	u8 res6[0xE4];
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} sysconf83xx_t;
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/*
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 * Watch Dog Timer (WDT) Registers
 */
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typedef struct wdt83xx {
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	u8 res0[4];
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	u32 swcrr;		/* System watchdog control register */
	u32 swcnr;		/* System watchdog count register */
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#define SWCNR_SWCN 0x0000FFFF Software Watchdog Count Field.
#define SWCNR_RES  ~(SWCNR_SWCN)
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	u8 res1[2];
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	u16 swsrr;		/* System watchdog service register */
#define SWSRR_WS 0x0000FFFF	/* Software Watchdog Service Field. */
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	u8 res2[0xF0];
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} wdt83xx_t;
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/*
 * RTC/PIT Module Registers
 */
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typedef struct rtclk83xx {
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	u32 cnr;		/* control register */
#define CNR_CLEN 0x00000080	/* Clock Enable Control Bit  */
#define CNR_CLIN 0x00000040	/* Input Clock Control Bit  */
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#define CNR_AIM	 0x00000002	/* Alarm Interrupt Mask Bit  */
#define CNR_SIM	 0x00000001	/* Second Interrupt Mask Bit  */
#define CNR_RES	 ~(CNR_CLEN | CNR_CLIN | CNR_AIM | CNR_SIM)
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	u32 ldr;		/* load register */
#define LDR_CLDV 0xFFFFFFFF	/* Contains the 32-bit value to be
				 * loaded in a 32-bit RTC counter.*/
	u32 psr;		/* prescale register */
#define PSR_PRSC 0xFFFFFFFF	/*  RTC Prescaler bits. */
	u32 ctr;		/* Counter value field register */
#define CRT_CNTV 0xFFFFFFFF	/* RTC Counter value field. */
	u32 evr;		/* event register */
#define RTEVR_SIF  0x00000001	/* Second Interrupt Flag Bit  */
#define RTEVR_AIF  0x00000002	/* Alarm Interrupt Flag Bit  */
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#define RTEVR_RES ~(RTEVR_SIF | RTEVR_AIF)
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#define PTEVR_PIF  0x00000001	/* Periodic interrupt flag bit. */
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#define PTEVR_RES ~(PTEVR_PIF)
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	u32 alr;		/* alarm register */
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	u8 res0[0xE8];
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} rtclk83xx_t;
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/*
 * Global timper module
 */

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typedef struct gtm83xx {
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	u8 cfr1;		/* Timer1/2 Configuration  */
#define CFR1_PCAS 0x80		/* Pair Cascade mode  */
#define CFR1_BCM  0x40		/* Backward compatible mode  */
#define CFR1_STP2 0x20		/* Stop timer  */
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#define CFR1_RST2 0x10		/* Reset timer	*/
#define CFR1_GM2  0x08		/* Gate mode for pin 2	*/
#define CFR1_GM1  0x04		/* Gate mode for pin 1	*/
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#define CFR1_STP1 0x02		/* Stop timer  */
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#define CFR1_RST1 0x01		/* Reset timer	*/
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#define CFR1_RES ~(CFR1_PCAS | CFR1_STP2 | CFR1_RST2 | CFR1_GM2 |\
		 CFR1_GM1 | CFR1_STP1 | CFR1_RST1)
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	u8 res0[3];
	u8 cfr2;		/* Timer3/4 Configuration  */
#define CFR2_PCAS 0x80		/* Pair Cascade mode  */
#define CFR2_SCAS 0x40		/* Super Cascade mode  */
#define CFR2_STP4 0x20		/* Stop timer  */
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#define CFR2_RST4 0x10		/* Reset timer	*/
#define CFR2_GM4  0x08		/* Gate mode for pin 4	*/
#define CFR2_GM3  0x04		/* Gate mode for pin 3	*/
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#define CFR2_STP3 0x02		/* Stop timer  */
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#define CFR2_RST3 0x01		/* Reset timer	*/
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	u8 res1[10];
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	u16 mdr1;		/* Timer1 Mode Register	 */
#define MDR_SPS	 0xff00		/* Secondary Prescaler value  */
#define MDR_CE	 0x00c0		/* Capture edge and enable interrupt  */
#define MDR_OM	 0x0020		/* Output mode	*/
#define MDR_ORI	 0x0010		/* Output reference interrupt enable  */
#define MDR_FRR	 0x0008		/* Free run/restart  */
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#define MDR_ICLK 0x0006		/* Input clock source for the timer  */
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#define MDR_GE	 0x0001		/* Gate enable	*/
	u16 mdr2;		/* Timer2 Mode Register	 */
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	u16 rfr1;		/* Timer1 Reference Register  */
	u16 rfr2;		/* Timer2 Reference Register  */
	u16 cpr1;		/* Timer1 Capture Register  */
	u16 cpr2;		/* Timer2 Capture Register  */
	u16 cnr1;		/* Timer1 Counter Register  */
	u16 cnr2;		/* Timer2 Counter Register  */
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	u16 mdr3;		/* Timer3 Mode Register	 */
	u16 mdr4;		/* Timer4 Mode Register	 */
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	u16 rfr3;		/* Timer3 Reference Register  */
	u16 rfr4;		/* Timer4 Reference Register  */
	u16 cpr3;		/* Timer3 Capture Register  */
	u16 cpr4;		/* Timer4 Capture Register  */
	u16 cnr3;		/* Timer3 Counter Register  */
	u16 cnr4;		/* Timer4 Counter Register  */
	u16 evr1;		/* Timer1 Event Register  */
	u16 evr2;		/* Timer2 Event Register  */
	u16 evr3;		/* Timer3 Event Register  */
	u16 evr4;		/* Timer4 Event Register  */
#define GTEVR_REF 0x0002	/* Output reference event  */
#define GTEVR_CAP 0x0001	/* Counter Capture event   */
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#define GTEVR_RES ~(EVR_CAP|EVR_REF)
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	u16 psr1;		/* Timer1 Prescaler Register  */
	u16 psr2;		/* Timer2 Prescaler Register  */
	u16 psr3;		/* Timer3 Prescaler Register  */
	u16 psr4;		/* Timer4 Prescaler Register  */
#define GTPSR_PPS  0x00FF	/* Primary Prescaler Bits. */
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#define GTPSR_RES  ~(GTPSR_PPS)
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	u8 res[0xC0];
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} gtm83xx_t;
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/*
 * Integrated Programmable Interrupt Controller
 */
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typedef struct ipic83xx {
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	u32 sicfr;		/*  System Global Interrupt Configuration Register (SICFR)  */
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#define SICFR_HPI  0x7f000000	/*  Highest Priority Interrupt	*/
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#define SICFR_MPSB 0x00400000	/*  Mixed interrupts Priority Scheme for group B  */
#define SICFR_MPSA 0x00200000	/*  Mixed interrupts Priority Scheme for group A  */
#define SICFR_IPSD 0x00080000	/*  Internal interrupts Priority Scheme for group D  */
#define SICFR_IPSA 0x00010000	/*  Internal interrupts Priority Scheme for group A  */
#define SICFR_HPIT 0x00000300	/*  HPI priority position IPIC output interrupt Type  */
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#define SICFR_RES ~(SICFR_HPI|SICFR_MPSB|SICFR_MPSA|SICFR_IPSD|SICFR_IPSA|SICFR_HPIT)
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	u32 sivcr;		/*  System Global Interrupt Vector Register (SIVCR)  */
#define SICVR_IVECX 0xfc000000	/*  Interrupt vector (for CE compatibility purpose only not used in 8349 IPIC implementation)  */
#define SICVR_IVEC  0x0000007f	/*  Interrupt vector  */
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#define SICVR_RES ~(SICVR_IVECX|SICVR_IVEC)
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	u32 sipnr_h;		/*  System Internal Interrupt Pending Register - High (SIPNR_H)	 */
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#if defined (CONFIG_MPC8349)
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#define SIIH_TSEC1TX 0x80000000 /*  TSEC1 Tx interrupt	*/
#define SIIH_TSEC1RX 0x40000000 /*  TSEC1 Rx interrupt	*/
#define SIIH_TSEC1ER 0x20000000 /*  TSEC1 Eror interrupt  */
#define SIIH_TSEC2TX 0x10000000 /*  TSEC2 Tx interrupt	*/
#define SIIH_TSEC2RX 0x08000000 /*  TSEC2 Rx interrupt	*/
#define SIIH_TSEC2ER 0x04000000 /*  TSEC2 Eror interrupt  */
#define SIIH_USB2DR  0x02000000 /*  USB2 DR interrupt  */
#define SIIH_USB2MPH 0x01000000 /*  USB2 MPH interrupt	*/
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#endif
#if defined (CONFIG_MPC8360)
#define SIIH_H_QE_H   0x80000000	/*  QE high interrupt */
#define SIIH_H_QE_L   0x40000000	/*  QE low interrupt */
#endif
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#define SIIH_UART1   0x00000080 /*  UART1 interrupt  */
#define SIIH_UART2   0x00000040 /*  UART2 interrupt  */
#define SIIH_SEC     0x00000020 /*  SEC interrupt  */
#define SIIH_I2C1    0x00000004 /*  I2C1 interrupt  */
#define SIIH_I2C2    0x00000002 /*  I2C2 interrupt  */
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#if defined (CONFIG_MPC8349)
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#define SIIH_SPI     0x00000001 /*  SPI interrupt  */
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#define SIIH_RES	~(SIIH_TSEC1TX | SIIH_TSEC1RX | SIIH_TSEC1ER \
			| SIIH_TSEC2TX | SIIH_TSEC2RX | SIIH_TSEC2ER \
			| SIIH_USB2DR | SIIH_USB2MPH | SIIH_UART1 \
			| SIIH_UART2 | SIIH_SEC | SIIH_I2C1 \
			| SIIH_I2C2 | SIIH_SPI)
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#endif
#if defined (CONFIG_MPC8360)
#define SIIH_RES       ~(SIIH_H_QE_H | SIIH_H_QE_L | SIIH_H_UART1 | \
			SIIH_H_UART2| SIIH_H_SEC  | SIIH_H_I2C1 |SIIH_H_I2C2)
#endif
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	u32 sipnr_l;		/*  System Internal Interrupt Pending Register - Low (SIPNR_L)	*/
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#define SIIL_RTCS  0x80000000	/*  RTC SECOND interrupt  */
#define SIIL_PIT   0x40000000	/*  PIT interrupt  */
#define SIIL_PCI1  0x20000000	/*  PCI1 interrupt  */
#if defined (CONFIG_MPC8349)
#define SIIL_PCI2  0x10000000	/*  PCI2 interrupt  */
#endif
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#define SIIL_RTCA  0x08000000	/*  RTC ALARM interrupt	 */
#define SIIL_MU	   0x04000000	/*  Message Unit interrupt  */
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#define SIIL_SBA   0x02000000	/*  System Bus Arbiter interrupt  */
#define SIIL_DMA   0x01000000	/*  DMA interrupt  */
#define SIIL_GTM4  0x00800000	/*  GTM4 interrupt  */
#define SIIL_GTM8  0x00400000	/*  GTM8 interrupt  */
#if defined (CONFIG_MPC8349)
#define SIIL_GPIO1 0x00200000	/*  GPIO1 interrupt  */
#define SIIL_GPIO2 0x00100000	/*  GPIO2 interrupt  */
#endif
#if defined (CONFIG_MPC8360)
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#define SIIL_QEP   0x00200000	/*  QE ports interrupt	*/
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#define SIIL_SDDR  0x00100000	/*  SDDR interrupt  */
#endif
#define SIIL_DDR   0x00080000	/*  DDR interrupt  */
#define SIIL_LBC   0x00040000	/*  LBC interrupt  */
#define SIIL_GTM2  0x00020000	/*  GTM2 interrupt  */
#define SIIL_GTM6  0x00010000	/*  GTM6 interrupt  */
#define SIIL_PMC   0x00008000	/*  PMC interrupt  */
#define SIIL_GTM3  0x00000800	/*  GTM3 interrupt  */
#define SIIL_GTM7  0x00000400	/*  GTM7 interrupt  */
#define SIIL_GTM1  0x00000020	/*  GTM1 interrupt  */
#define SIIL_GTM5  0x00000010	/*  GTM5 interrupt  */
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#define SIIL_DPTC  0x00000001	/*  DPTC interrupt (!!! Invisible for user !!!)	 */
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#if defined (CONFIG_MPC8349)
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#define SIIL_RES	~(SIIL_RTCS | SIIL_PIT | SIIL_PCI1 | SIIL_PCI2 \
			| SIIL_RTCA | SIIL_MU | SIIL_SBA | SIIL_DMA \
			| SIIL_GTM4 | SIIL_GTM8 | SIIL_GPIO1 | SIIL_GPIO2 \
			| SIIL_DDR | SIIL_LBC | SIIL_GTM2 | SIIL_GTM6 \
			| SIIL_PMC |SIIL_GTM3 | SIIL_GTM7 | SIIL_GTM1 \
			| SIIL_GTM5 |SIIL_DPTC )
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#endif
#if defined (CONFIG_MPC8360)
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#define SIIL_RES	~(SIIL_RTCS  |SIIL_PIT	|SIIL_PCI1 |SIIL_RTCALR \
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			|SIIL_MU |SIIL_SBA  |SIIL_DMA  |SIIL_GTM4 |SIIL_GTM8 \
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			|SIIL_QEP | SIIL_SDDR| SIIL_DDR	 |SIIL_LBC  |SIIL_GTM2 \
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			|SIIL_GTM6 |SIIL_PMC  |SIIL_GTM3 |SIIL_GTM7 |SIIL_GTM1 \
			|SIIL_GTM5 )
#endif
	u32 siprr_a;		/*  System Internal Interrupt Group A Priority Register (PRR)  */
	u8 res0[8];
	u32 siprr_d;		/*  System Internal Interrupt Group D Priority Register (PRR)  */
	u32 simsr_h;		/*  System Internal Interrupt Mask Register - High (SIIH)  */
	u32 simsr_l;		/*  System Internal Interrupt Mask Register - Low (SIIL)  */
	u8 res1[4];
	u32 sepnr;		/*  System External Interrupt Pending Register (SEI)  */
	u32 smprr_a;		/*  System Mixed Interrupt Group A Priority Register (PRR)  */
	u32 smprr_b;		/*  System Mixed Interrupt Group B Priority Register (PRR)  */
#define PRR_0 0xe0000000	/* Priority Register, Position 0 programming */
#define PRR_1 0x1c000000	/* Priority Register, Position 1 programming */
#define PRR_2 0x03800000	/* Priority Register, Position 2 programming */
#define PRR_3 0x00700000	/* Priority Register, Position 3 programming */
#define PRR_4 0x0000e000	/* Priority Register, Position 4 programming */
#define PRR_5 0x00001c00	/* Priority Register, Position 5 programming */
#define PRR_6 0x00000380	/* Priority Register, Position 6 programming */
#define PRR_7 0x00000070	/* Priority Register, Position 7 programming */
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#define PRR_RES ~(PRR_0|PRR_1|PRR_2|PRR_3|PRR_4|PRR_5|PRR_6|PRR_7)
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	u32 semsr;		/*  System External Interrupt Mask Register (SEI)  */
#define SEI_IRQ0  0x80000000	/*  IRQ0 external interrupt  */
#define SEI_IRQ1  0x40000000	/*  IRQ1 external interrupt  */
#define SEI_IRQ2  0x20000000	/*  IRQ2 external interrupt  */
#define SEI_IRQ3  0x10000000	/*  IRQ3 external interrupt  */
#define SEI_IRQ4  0x08000000	/*  IRQ4 external interrupt  */
#define SEI_IRQ5  0x04000000	/*  IRQ5 external interrupt  */
#define SEI_IRQ6  0x02000000	/*  IRQ6 external interrupt  */
#define SEI_IRQ7  0x01000000	/*  IRQ7 external interrupt  */
#define SEI_SIRQ0 0x00008000	/*  SIRQ0 external interrupt  */
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#define SEI_RES		~( SEI_IRQ0 | SEI_IRQ1 | SEI_IRQ2 | SEI_IRQ3 \
			| SEI_IRQ4 | SEI_IRQ5 | SEI_IRQ6 | SEI_IRQ7 \
			| SEI_SIRQ0)
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	u32 secnr;		/*  System External Interrupt Control Register (SECNR) */
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#define SECNR_MIXB0T 0xc0000000 /*  MIXB0 priority position IPIC output interrupt type	*/
#define SECNR_MIXB1T 0x30000000 /*  MIXB1 priority position IPIC output interrupt type	*/
#define SECNR_MIXA0T 0x00c00000 /*  MIXA0 priority position IPIC output interrupt type	*/
#define SECNR_SYSA1T 0x00300000 /*  MIXA1 priority position IPIC output interrupt type	*/
#define SECNR_EDI0   0x00008000 /*  IRQ0 external interrupt edge/level detect  */
#define SECNR_EDI1   0x00004000 /*  IRQ1 external interrupt edge/level detect  */
#define SECNR_EDI2   0x00002000 /*  IRQ2 external interrupt edge/level detect  */
#define SECNR_EDI3   0x00001000 /*  IRQ3 external interrupt edge/level detect  */
#define SECNR_EDI4   0x00000800 /*  IRQ4 external interrupt edge/level detect  */
#define SECNR_EDI5   0x00000400 /*  IRQ5 external interrupt edge/level detect  */
#define SECNR_EDI6   0x00000200 /*  IRQ6 external interrupt edge/level detect  */
#define SECNR_EDI7   0x00000100 /*  IRQ7 external interrupt edge/level detect  */
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#define SECNR_RES	~( SECNR_MIXB0T | SECNR_MIXB1T | SECNR_MIXA0T \
			| SECNR_SYSA1T | SECNR_EDI0 | SECNR_EDI1 \
			| SECNR_EDI2 | SECNR_EDI3 | SECNR_EDI4 \
			| SECNR_EDI5 | SECNR_EDI6 | SECNR_EDI7)
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	u32 sersr;		/*  System Error Status Register (SERR)	 */
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	u32 sermr;		/*  System Error Mask Register (SERR)  */
#define SERR_IRQ0 0x80000000	/*  IRQ0 MCP request  */
#define SERR_WDT  0x40000000	/*  WDT MCP request  */
#define SERR_SBA  0x20000000	/*  SBA MCP request  */
#if defined (CONFIG_MPC8349)
#define SERR_DDR  0x10000000	/*  DDR MCP request  */
#define SERR_LBC  0x08000000	/*  LBC MCP request  */
#define SERR_PCI1 0x04000000	/*  PCI1 MCP request  */
#define SERR_PCI2 0x02000000	/*  PCI2 MCP request  */
#endif
#if defined (CONFIG_MPC8360)
#define SERR_CIEE 0x10000000	/*  CIEE MCP request  */
#define SERR_CMEE 0x08000000	/*  CMEEMCP request  */
#define SERR_PCI  0x04000000	/*  PCI MCP request  */
#endif
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#define SERR_MU	  0x01000000	/*  MU MCP request  */
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#define SERR_RNC  0x00010000	/*  MU MCP request (!!! Non-visible for users !!!)  */
#if defined (CONFIG_MPC8349)
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#define SERR_RES	~( SERR_IRQ0 | SERR_WDT | SERR_SBA | SERR_DDR \
			|SERR_LBC | SERR_PCI1 | SERR_PCI2 | SERR_MU \
			|SERR_RNC )
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#elif defined (CONFIG_MPC8360)
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#define SERR_RES	~( SERR_IRQ0|SERR_WDT |SERR_SBA |SERR_CIEE\
			|SERR_CMEE|SERR_PCI|SERR_MU)
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#endif
	u32 sercr;		/*  System Error Control Register  (SERCR)  */
#define SERCR_MCPR 0x00000001	/*  MCP Route  */
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#define SERCR_RES ~(SERCR_MCPR)
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	u8 res2[4];
	u32 sifcr_h;		/*  System Internal Interrupt Force Register - High (SIIH)  */
	u32 sifcr_l;		/*  System Internal Interrupt Force Register - Low (SIIL)  */
	u32 sefcr;		/*  System External Interrupt Force Register (SEI)  */
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	u32 serfr;		/*  System Error Force Register (SERR)	*/
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	u32 scvcr;		/* System Critical Interrupt Vector Register */
#define SCVCR_CVECX	0xFC000000	/* Backward (MPC8260) compatible
					   critical interrupt vector. */
#define SCVCR_CVEC	0x0000007F	/* Critical interrupt vector */
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#define SCVCR_RES	~(SCVCR_CVECX|SCVCR_CVEC)
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	u32 smvcr;		/* System Management Interrupt Vector Register */
#define SMVCR_CVECX	0xFC000000	/* Backward (MPC8260) compatible
					   critical interrupt vector. */
#define SMVCR_CVEC	0x0000007F	/* Critical interrupt vector */
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#define SMVCR_RES	~(SMVCR_CVECX|SMVCR_CVEC)
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	u8 res3[0x98];
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} ipic83xx_t;
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/*
 * System Arbiter Registers
 */
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typedef struct arbiter83xx {
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	u32 acr;		/* Arbiter Configuration Register */
#define ACR_COREDIS    0x10000000	/* Core disable. */
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#define ACR_COREDIS_SHIFT		(31-7)
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#define ACR_PIPE_DEP   0x00070000	/* Pipeline depth (number of outstanding transactions). */
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#define ACR_PIPE_DEP_SHIFT		(31-15)
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#define ACR_PCI_RPTCNT 0x00007000	/* PCI repeat count. */
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#define ACR_PCI_RPTCNT_SHIFT		(31-19)
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#define ACR_RPTCNT     0x00000700	/* Repeat count. */
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#define ACR_RPTCNT_SHIFT		(31-23)
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#define ACR_APARK      0x00000030	/* Address parking. */
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#define ACR_APARK_SHIFT			(31-27)
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#define ACR_PARKM	   0x0000000F	/* Parking master. */
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#define ACR_PARKM_SHIFT			(31-31)
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#define ACR_RES ~(ACR_COREDIS|ACR_PIPE_DEP|ACR_PCI_RPTCNT|ACR_RPTCNT|ACR_APARK|ACR_PARKM)
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	u32 atr;		/* Arbiter Timers Register */
#define ATR_DTO 0x00FF0000	/* Data time out. */
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#define ATR_ATO 0x000000FF	/* Address time out. */
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#define ATR_RES ~(ATR_DTO|ATR_ATO)
	u8 res[4];
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	u32 aer;		/* Arbiter Event Register (AE) */
	u32 aidr;		/* Arbiter Interrupt Definition Register (AE) */
	u32 amr;		/* Arbiter Mask Register (AE) */
	u32 aeatr;		/* Arbiter Event Attributes Register */
#define AEATR_EVENT   0x07000000	/* Event type. */
#define AEATR_MSTR_ID 0x001F0000	/* Master Id. */
#define AEATR_TBST    0x00000800	/* Transfer burst. */
#define AEATR_TSIZE   0x00000700	/* Transfer Size. */
#define AEATR_TTYPE	  0x0000001F	/* Transfer Type. */
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#define AEATR_RES ~(AEATR_EVENT|AEATR_MSTR_ID|AEATR_TBST|AEATR_TSIZE|AEATR_TTYPE)
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	u32 aeadr;		/* Arbiter Event Address Register */
	u32 aerr;		/* Arbiter Event Response Register (AE) */
#define AE_ETEA 0x00000020	/* Transfer error. */
#define AE_RES_ 0x00000010	/* Reserved transfer type. */
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#define AE_ECW	0x00000008	/* External control word transfer type. */
#define AE_AO	0x00000004	/* Address Only transfer type. */
#define AE_DTO	0x00000002	/* Data time out. */
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#define AE_ATO	0x00000001	/* Address time out. */
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#define AE_RSRV ~(AE_ETEA|AE_RES_|AE_ECW|AE_AO|AE_DTO|AE_ATO)
	u8 res1[0xDC];
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} arbiter83xx_t;
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/*
 * Reset Module
 */
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typedef struct reset83xx {
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	u32 rcwl;		/* RCWL Register  */
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#define RCWL_LBIUCM  0x80000000 /* LBIUCM  */
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#define RCWL_LBIUCM_SHIFT    31
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#define RCWL_DDRCM   0x40000000 /* DDRCM  */
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#define RCWL_DDRCM_SHIFT     30
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#if defined (CONFIG_MPC8349)
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#define RCWL_SVCOD   0x30000000 /* SVCOD  */
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#endif
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#define RCWL_SPMF    0x0f000000 /* SPMF	 */
#define RCWL_SPMF_SHIFT	     24
#define RCWL_COREPLL 0x007F0000 /* COREPLL  */
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#define RCWL_COREPLL_SHIFT   16
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#define RCWL_CEVCOD  0x000000C0 /* CEVCOD  */
#define RCWL_CEPDF   0x00000020 /* CEPDF  */
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#define RCWL_CEPDF_SHIFT      5
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#define RCWL_CEPMF   0x0000001F /* CEPMF  */
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#define RCWL_CEPMF_SHIFT      0
#if defined (CONFIG_MPC8349)
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#define RCWL_RES ~(RCWL_LBIUCM|RCWL_DDRCM|RCWL_SVCOD|RCWL_SPMF|RCWL_COREPLL|RCWL_CEVCOD|RCWL_CEPDF|RCWL_CEPMF)
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#elif defined (CONFIG_MPC8360)
#define RCWL_RES ~(RCWL_LBIUCM|RCWL_DDRCM|RCWL_SPMF|RCWL_COREPLL|RCWL_CEPDF|RCWL_CEPMF)
#endif
	u32 rcwh;		/* RCHL Register  */
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#define RCWH_PCIHOST 0x80000000 /* PCIHOST  */
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#define RCWH_PCIHOST_SHIFT   31
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#if defined (CONFIG_MPC8349)
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#define RCWH_PCI64   0x40000000 /* PCI64  */
#define RCWH_PCI1ARB 0x20000000 /* PCI1ARB  */
#define RCWH_PCI2ARB 0x10000000 /* PCI2ARB  */
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#elif defined (CONFIG_MPC8360)
#define RCWH_PCIARB   0x20000000	/* PCI internal arbiter mode. */
#define RCWH_PCICKDRV 0x10000000	/* PCI clock output drive. */
#endif
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#define RCWH_COREDIS 0x08000000 /* COREDIS  */
#define RCWH_BMS     0x04000000 /* BMS	*/
#define RCWH_BOOTSEQ 0x03000000 /* BOOTSEQ  */
#define RCWH_SWEN    0x00800000 /* SWEN	 */
#define RCWH_ROMLOC  0x00700000 /* ROMLOC  */
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#if defined (CONFIG_MPC8349)
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#define RCWH_TSEC1M  0x0000c000 /* TSEC1M  */
#define RCWH_TSEC2M  0x00003000 /* TSEC2M  */
#define RCWH_TPR     0x00000100 /* TPR	*/
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#elif defined (CONFIG_MPC8360)
#define RCWH_SDDRIOE  0x00000010	/* Secondary DDR IO Enable.  */
#endif
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#define RCWH_TLE     0x00000008 /* TLE	*/
#define RCWH_LALE    0x00000004 /* LALE	 */
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#if defined (CONFIG_MPC8349)
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#define RCWH_RES	~(RCWH_PCIHOST | RCWH_PCI64 | RCWH_PCI1ARB \
			| RCWH_PCI2ARB | RCWH_COREDIS | RCWH_BMS \
			| RCWH_BOOTSEQ | RCWH_SWEN | RCWH_ROMLOC \
			| RCWH_TSEC1M | RCWH_TSEC2M | RCWH_TPR \
			| RCWH_TLE | RCWH_LALE)
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#elif defined (CONFIG_MPC8360)
#define RCWH_RES	~(RCWH_PCIHOST|RCWH_PCIARB|RCWH_PCICKDRV \
			|RCWH_COREDIS|RCWH_BMS|RCWH_BOOTSEQ|RCWH_SWEN \
			|RCWH_SDDRIOE |RCWH_TLE)
#endif
	u8 res0[8];
	u32 rsr;		/* Reset status Register  */
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#define RSR_RSTSRC 0xE0000000	/* Reset source	 */
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#define RSR_RSTSRC_SHIFT   29
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#define RSR_BSF	   0x00010000	/* Boot seq. fail  */
#define RSR_BSF_SHIFT	   16
#define RSR_SWSR   0x00002000	/* software soft reset	*/
#define RSR_SWSR_SHIFT	   13
#define RSR_SWHR   0x00001000	/* software hard reset	*/
#define RSR_SWHR_SHIFT	   12
#define RSR_JHRS   0x00000200	/* jtag hreset	*/
#define RSR_JHRS_SHIFT	    9
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#define RSR_JSRS   0x00000100	/* jtag sreset status  */
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#define RSR_JSRS_SHIFT	    8
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#define RSR_CSHR   0x00000010	/* checkstop reset status  */
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#define RSR_CSHR_SHIFT	    4
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#define RSR_SWRS   0x00000008	/* software watchdog reset status  */
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#define RSR_SWRS_SHIFT	    3
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#define RSR_BMRS   0x00000004	/* bus monitop reset status  */
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#define RSR_BMRS_SHIFT	    2
#define RSR_SRS	   0x00000002	/* soft reset status  */
#define RSR_SRS_SHIFT	    1
#define RSR_HRS	   0x00000001	/* hard reset status  */
#define RSR_HRS_SHIFT	    0
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#define RSR_RES ~(RSR_RSTSRC | RSR_BSF | RSR_SWSR | RSR_SWHR | RSR_JHRS | RSR_JSRS | RSR_CSHR | RSR_SWRS | RSR_BMRS | RSR_SRS | RSR_HRS)
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	u32 rmr;		/* Reset mode Register	*/
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#define RMR_CSRE   0x00000001	/* checkstop reset enable  */
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#define RMR_CSRE_SHIFT	    0
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#define RMR_RES ~(RMR_CSRE)
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	u32 rpr;		/* Reset protection Register  */
	u32 rcr;		/* Reset Control Register  */
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#define RCR_SWHR 0x00000002	/* software hard reset	*/
#define RCR_SWSR 0x00000001	/* software soft reset	*/
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#define RCR_RES ~(RCR_SWHR | RCR_SWSR)
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	u32 rcer;		/* Reset Control Enable Register  */
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#define RCER_CRE 0x00000001	/* software hard reset	*/
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#define RCER_RES ~(RCER_CRE)
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	u8 res1[0xDC];
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} reset83xx_t;
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typedef struct clk83xx {
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	u32 spmr;		/* system PLL mode Register  */
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#define SPMR_LBIUCM  0x80000000 /* LBIUCM  */
#define SPMR_DDRCM   0x40000000 /* DDRCM  */
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#if defined (CONFIG_MPC8349)
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#define SPMR_SVCOD   0x30000000 /* SVCOD  */
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#endif
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#define SPMR_SPMF    0x0F000000 /* SPMF	 */
#define SPMR_CKID    0x00800000 /* CKID	 */
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#define SPMR_CKID_SHIFT 23
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#define SPMR_COREPLL 0x007F0000 /* COREPLL  */
#define SPMR_CEVCOD  0x000000C0 /* CEVCOD  */
#define SPMR_CEPDF   0x00000020 /* CEPDF  */
#define SPMR_CEPMF   0x0000001F /* CEPMF  */
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#if defined (CONFIG_MPC8349)
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#define SPMR_RES	~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SVCOD \
			| SPMR_SPMF | SPMR_CKID | SPMR_COREPLL \
			| SPMR_CEVCOD | SPMR_CEPDF | SPMR_CEPMF)
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#elif defined (CONFIG_MPC8360)
#define SPMR_RES	~(SPMR_LBIUCM | SPMR_DDRCM | SPMR_SPMF \
			| SPMR_CKID | SPMR_COREPLL | SPMR_CEVCOD \
			| SPMR_CEPDF | SPMR_CEPMF)
#endif
	u32 occr;		/* output clock control Register  */
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#define OCCR_PCICOE0 0x80000000 /* PCICOE0  */
#define OCCR_PCICOE1 0x40000000 /* PCICOE1  */
#define OCCR_PCICOE2 0x20000000 /* PCICOE2  */
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#if defined (CONFIG_MPC8349)
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#define OCCR_PCICOE3 0x10000000 /* PCICOE3  */
#define OCCR_PCICOE4 0x08000000 /* PCICOE4  */
#define OCCR_PCICOE5 0x04000000 /* PCICOE5  */
#define OCCR_PCICOE6 0x02000000 /* PCICOE6  */
#define OCCR_PCICOE7 0x01000000 /* PCICOE7  */
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#endif
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#define OCCR_PCICD0  0x00800000 /* PCICD0  */
#define OCCR_PCICD1  0x00400000 /* PCICD1  */
#define OCCR_PCICD2  0x00200000 /* PCICD2  */
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#if defined (CONFIG_MPC8349)
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#define OCCR_PCICD3  0x00100000 /* PCICD3  */
#define OCCR_PCICD4  0x00080000 /* PCICD4  */
#define OCCR_PCICD5  0x00040000 /* PCICD5  */
#define OCCR_PCICD6  0x00020000 /* PCICD6  */
#define OCCR_PCICD7  0x00010000 /* PCICD7  */
#define OCCR_PCI1CR  0x00000002 /* PCI1CR  */
#define OCCR_PCI2CR  0x00000001 /* PCI2CR  */
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#define OCCR_RES	~(OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 \
			| OCCR_PCICOE3 | OCCR_PCICOE4 | OCCR_PCICOE5 \
			| OCCR_PCICOE6 | OCCR_PCICOE7 | OCCR_PCICD0 \
			| OCCR_PCICD1 | OCCR_PCICD2  | OCCR_PCICD3 \
			| OCCR_PCICD4  | OCCR_PCICD5 | OCCR_PCICD6  \
			| OCCR_PCICD7  | OCCR_PCI1CR  | OCCR_PCI2CR )
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#endif
#if defined (CONFIG_MPC8360)
#define OCCR_PCICR	0x00000002	/* PCI clock rate  */
#define OCCR_RES	~(OCCR_PCICOE0|OCCR_PCICOE1|OCCR_PCICOE2 \
			|OCCR_PCICD0|OCCR_PCICD1|OCCR_PCICD2|OCCR_PCICR )
#endif
	u32 sccr;		/* system clock control Register  */
#if defined (CONFIG_MPC8349)
#define SCCR_TSEC1CM  0xc0000000	/* TSEC1CM  */
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#define SCCR_TSEC1CM_SHIFT 30
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#define SCCR_TSEC2CM  0x30000000	/* TSEC2CM  */
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#define SCCR_TSEC2CM_SHIFT 28
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#endif
#define SCCR_ENCCM    0x03000000	/* ENCCM  */
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#define SCCR_ENCCM_SHIFT 24
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#if defined (CONFIG_MPC8349)
#define SCCR_USBMPHCM 0x00c00000	/* USBMPHCM  */
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#define SCCR_USBMPHCM_SHIFT 22
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#define SCCR_USBDRCM  0x00300000	/* USBDRCM  */
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#define SCCR_USBDRCM_SHIFT 20
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#endif
#define SCCR_PCICM    0x00010000	/* PCICM  */
#if defined (CONFIG_MPC8349)
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#define SCCR_RES	~( SCCR_TSEC1CM | SCCR_TSEC2CM | SCCR_ENCCM \
			| SCCR_USBMPHCM | SCCR_USBDRCM | SCCR_PCICM)
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#endif
#if defined (CONFIG_MPC8360)
#define SCCR_RES	~(SCCR_ENCCM | SCCR_PCICM)
#endif
	u8 res0[0xF4];
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} clk83xx_t;
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/*
 * Power Management Control Module
 */
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typedef struct pmc83xx {
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	u32 pmccr;		/* PMC Configuration Register  */
#define PMCCR_SLPEN 0x00000001	/* System Low Power Enable  */
#define PMCCR_DLPEN 0x00000002	/* DDR SDRAM Low Power Enable  */
#if defined (CONFIG_MPC8360)
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#define PMCCR_SDLPEN 0x00000004 /* Secondary DDR SDRAM Low Power Enable	 */
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#define PMCCR_RES ~(PMCCR_SLPEN | PMCCR_DLPEN | PMCCR_SDLPEN)
#elif defined (CONFIG_MPC8349)
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#define PMCCR_RES    ~(PMCCR_SLPEN | PMCCR_DLPEN)
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#endif
	u32 pmcer;		/* PMC Event Register  */
#define PMCER_PMCI  0x00000001	/* PMC Interrupt  */
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#define PMCER_RES ~(PMCER_PMCI)
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	u32 pmcmr;		/* PMC Mask Register  */
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#define PMCMR_PMCIE 0x0001	/* PMC Interrupt Enable	 */
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#define PMCMR_RES ~(PMCMR_PMCIE)
	u8 res0[0xF4];
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} pmc83xx_t;
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#if defined (CONFIG_MPC8349)
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/*
 * general purpose I/O module
 */
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typedef struct gpio83xx {
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	u32 dir;		/* direction register */
	u32 odr;		/* open drain register */
	u32 dat;		/* data register */
	u32 ier;		/* interrupt event register */
	u32 imr;		/* interrupt mask register */
	u32 icr;		/* external interrupt control register */
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	u8 res0[0xE8];
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} gpio83xx_t;
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#endif

#if defined (CONFIG_MPC8360)
/*
 * QE Ports Interrupts Registers
 */
typedef struct qepi83xx {
	u8 res0[0xC];
	u32 qepier;		/* QE Ports Interrupt Event Register */
#define QEPIER_PA15 0x80000000
#define QEPIER_PA16 0x40000000
#define QEPIER_PA29 0x20000000
#define QEPIER_PA30 0x10000000
#define QEPIER_PB3  0x08000000
#define QEPIER_PB5  0x04000000
#define QEPIER_PB12 0x02000000
#define QEPIER_PB13 0x01000000
#define QEPIER_PB26 0x00800000
#define QEPIER_PB27 0x00400000
#define QEPIER_PC27 0x00200000
#define QEPIER_PC28 0x00100000
#define QEPIER_PC29 0x00080000
#define QEPIER_PD12 0x00040000
#define QEPIER_PD13 0x00020000
#define QEPIER_PD16 0x00010000
#define QEPIER_PD17 0x00008000
#define QEPIER_PD26 0x00004000
#define QEPIER_PD27 0x00002000
#define QEPIER_PE12 0x00001000
#define QEPIER_PE13 0x00000800
#define QEPIER_PE24 0x00000400
#define QEPIER_PE25 0x00000200
#define QEPIER_PE26 0x00000100
#define QEPIER_PE27 0x00000080
#define QEPIER_PE31 0x00000040
#define QEPIER_PF20 0x00000020
#define QEPIER_PG31 0x00000010
#define QEPIER_RES ~(QEPIER_PA15|QEPIER_PA16|QEPIER_PA29|QEPIER_PA30|QEPIER_PB3 \
		   |QEPIER_PB5|QEPIER_PB12|QEPIER_PB13|QEPIER_PB26|QEPIER_PB27 \
		   |QEPIER_PC27|QEPIER_PC28|QEPIER_PC29|QEPIER_PD12|QEPIER_PD13 \
		   |QEPIER_PD16|QEPIER_PD17|QEPIER_PD26|QEPIER_PD27|QEPIER_PE12 \
		   |QEPIER_PE13|QEPIER_PE24|QEPIER_PE25|QEPIER_PE26|QEPIER_PE27 \
		   |QEPIER_PE31|QEPIER_PF20|QEPIER_PG31)
	u32 qepimr;		/* QE Ports Interrupt Mask Register */
#define QEPIMR_PA15 0x80000000
#define QEPIMR_PA16 0x40000000
#define QEPIMR_PA29 0x20000000
#define QEPIMR_PA30 0x10000000
#define QEPIMR_PB3  0x08000000
#define QEPIMR_PB5  0x04000000
#define QEPIMR_PB12 0x02000000
#define QEPIMR_PB13 0x01000000
#define QEPIMR_PB26 0x00800000
#define QEPIMR_PB27 0x00400000
#define QEPIMR_PC27 0x00200000
#define QEPIMR_PC28 0x00100000
#define QEPIMR_PC29 0x00080000
#define QEPIMR_PD12 0x00040000
#define QEPIMR_PD13 0x00020000
#define QEPIMR_PD16 0x00010000
#define QEPIMR_PD17 0x00008000
#define QEPIMR_PD26 0x00004000
#define QEPIMR_PD27 0x00002000
#define QEPIMR_PE12 0x00001000
#define QEPIMR_PE13 0x00000800
#define QEPIMR_PE24 0x00000400
#define QEPIMR_PE25 0x00000200
#define QEPIMR_PE26 0x00000100
#define QEPIMR_PE27 0x00000080
#define QEPIMR_PE31 0x00000040
#define QEPIMR_PF20 0x00000020
#define QEPIMR_PG31 0x00000010
#define QEPIMR_RES ~(QEPIMR_PA15|QEPIMR_PA16|QEPIMR_PA29|QEPIMR_PA30|QEPIMR_PB3 \
		   |QEPIMR_PB5|QEPIMR_PB12|QEPIMR_PB13|QEPIMR_PB26|QEPIMR_PB27 \
		   |QEPIMR_PC27|QEPIMR_PC28|QEPIMR_PC29|QEPIMR_PD12|QEPIMR_PD13 \
		   |QEPIMR_PD16|QEPIMR_PD17|QEPIMR_PD26|QEPIMR_PD27|QEPIMR_PE12 \
		   |QEPIMR_PE13|QEPIMR_PE24|QEPIMR_PE25|QEPIMR_PE26|QEPIMR_PE27 \
		   |QEPIMR_PE31|QEPIMR_PF20|QEPIMR_PG31)
	u32 qepicr;		/* QE Ports Interrupt Control Register */
#define QEPICR_PA15 0x80000000
#define QEPICR_PA16 0x40000000
#define QEPICR_PA29 0x20000000
#define QEPICR_PA30 0x10000000
#define QEPICR_PB3  0x08000000
#define QEPICR_PB5  0x04000000
#define QEPICR_PB12 0x02000000
#define QEPICR_PB13 0x01000000
#define QEPICR_PB26 0x00800000
#define QEPICR_PB27 0x00400000
#define QEPICR_PC27 0x00200000
#define QEPICR_PC28 0x00100000
#define QEPICR_PC29 0x00080000
#define QEPICR_PD12 0x00040000
#define QEPICR_PD13 0x00020000
#define QEPICR_PD16 0x00010000
#define QEPICR_PD17 0x00008000
#define QEPICR_PD26 0x00004000
#define QEPICR_PD27 0x00002000
#define QEPICR_PE12 0x00001000
#define QEPICR_PE13 0x00000800
#define QEPICR_PE24 0x00000400
#define QEPICR_PE25 0x00000200
#define QEPICR_PE26 0x00000100
#define QEPICR_PE27 0x00000080
#define QEPICR_PE31 0x00000040
#define QEPICR_PF20 0x00000020
#define QEPICR_PG31 0x00000010
#define QEPICR_RES ~(QEPICR_PA15|QEPICR_PA16|QEPICR_PA29|QEPICR_PA30|QEPICR_PB3 \
		   |QEPICR_PB5|QEPICR_PB12|QEPICR_PB13|QEPICR_PB26|QEPICR_PB27 \
		   |QEPICR_PC27|QEPICR_PC28|QEPICR_PC29|QEPICR_PD12|QEPICR_PD13 \
		   |QEPICR_PD16|QEPICR_PD17|QEPICR_PD26|QEPICR_PD27|QEPICR_PE12 \
		   |QEPICR_PE13|QEPICR_PE24|QEPICR_PE25|QEPICR_PE26|QEPICR_PE27 \
		   |QEPICR_PE31|QEPICR_PF20|QEPICR_PG31)
	u8 res1[0xE8];
} qepi83xx_t;

/*
 * general purpose I/O module
 */
typedef struct gpio_n {
	u32 podr;		/* Open Drain Register */
	u32 pdat;		/* Data Register */
	u32 dir1;		/* direction register 1 */
	u32 dir2;		/* direction register 2 */
	u32 ppar1;		/* Pin Assignment Register 1 */
	u32 ppar2;		/* Pin Assignment Register 2 */
} gpio_n_t;

typedef struct gpio83xx {
	gpio_n_t ioport[0x7];
	u8 res0[0x358];
} gpio83xx_t;

/*
 * QE Secondary Bus Access Windows
 */

typedef struct qesba83xx {
	u32 lbmcsar;		/* Local bus memory controller start address */
#define LBMCSAR_SA	0x000FFFFF	/* 20 most-significant bits of the start address */
#define LBMCSAR_RES	~(LBMCSAR_SA)
	u32 sdmcsar;		/* Secondary DDR memory controller start address */
#define SDMCSAR_SA	0x000FFFFF	/* 20 most-significant bits of the start address */
#define SDMCSAR_RES	~(SDMCSAR_SA)
	u8 res0[0x38];
	u32 lbmcear;		/* Local bus memory controller end address */
#define LBMCEAR_EA	0x000FFFFF	/* 20 most-significant bits of the end address */
#define LBMCEAR_RES	~(LBMCEAR_EA)
	u32 sdmcear;		/* Secondary DDR memory controller end address */
#define SDMCEAR_EA	0x000FFFFF	/* 20 most-significant bits of the end address */
#define SDMCEAR_RES	~(SDMCEAR_EA)
	u8 res1[0x38];
	u32 lbmcar;		/* Local bus memory controller attributes  */
#define LBMCAR_WEN	0x00000001	/* Forward transactions to the QE local bus */
#define LBMCAR_RES	~(LBMCAR_WEN)
	u32 sdmcar;		/* Secondary DDR memory controller attributes */
#define SDMCAR_WEN	0x00000001	/* Forward transactions to the second DDR bus */
#define SDMCAR_RES	~(SDMCAR_WEN)
	u8 res2[0x778];
} qesba83xx_t;
#endif
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/*
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 * DDR Memory Controller Memory Map
 */
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typedef struct ddr_cs_bnds {
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	u32 csbnds;
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#define CSBNDS_SA 0x00FF0000
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#define CSBNDS_SA_SHIFT	   8
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#define CSBNDS_EA 0x000000FF
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#define CSBNDS_EA_SHIFT	  24
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	u8 res0[4];
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} ddr_cs_bnds_t;

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typedef struct ddr83xx {
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	ddr_cs_bnds_t csbnds[4];	    /**< Chip Select x Memory Bounds */
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	u8 res0[0x60];
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	u32 cs_config[4];	/**< Chip Select x Configuration */
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#define CSCONFIG_EN	    0x80000000
#define CSCONFIG_AP	    0x00800000
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#define CSCONFIG_ROW_BIT    0x00000700
#define CSCONFIG_ROW_BIT_12 0x00000000
#define CSCONFIG_ROW_BIT_13 0x00000100
#define CSCONFIG_ROW_BIT_14 0x00000200
#define CSCONFIG_COL_BIT    0x00000007
#define CSCONFIG_COL_BIT_8  0x00000000
#define CSCONFIG_COL_BIT_9  0x00000001
#define CSCONFIG_COL_BIT_10 0x00000002
#define CSCONFIG_COL_BIT_11 0x00000003
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	u8 res1[0x78];
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	u32 timing_cfg_1;	/**< SDRAM Timing Configuration 1 */
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#define TIMING_CFG1_PRETOACT 0x70000000
#define TIMING_CFG1_PRETOACT_SHIFT   28
#define TIMING_CFG1_ACTTOPRE 0x0F000000
#define TIMING_CFG1_ACTTOPRE_SHIFT   24
#define TIMING_CFG1_ACTTORW  0x00700000
#define TIMING_CFG1_ACTTORW_SHIFT    20
#define TIMING_CFG1_CASLAT   0x00070000
#define TIMING_CFG1_CASLAT_SHIFT     16
#define TIMING_CFG1_REFREC   0x0000F000
#define TIMING_CFG1_REFREC_SHIFT     12
#define TIMING_CFG1_WRREC    0x00000700
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#define TIMING_CFG1_WRREC_SHIFT	      8
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#define TIMING_CFG1_ACTTOACT 0x00000070
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#define TIMING_CFG1_ACTTOACT_SHIFT    4
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#define TIMING_CFG1_WRTORD   0x00000007
#define TIMING_CFG1_WRTORD_SHIFT      0
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#define TIMING_CFG1_CASLAT_20 0x00030000	/* CAS latency = 2.0 */
#define TIMING_CFG1_CASLAT_25 0x00040000	/* CAS latency = 2.5 */
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	u32 timing_cfg_2;	/**< SDRAM Timing Configuration 2 */
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#define TIMING_CFG2_CPO		  0x0F000000
#define TIMING_CFG2_CPO_SHIFT		  24
#define TIMING_CFG2_ACSM	  0x00080000
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#define TIMING_CFG2_WR_DATA_DELAY 0x00001C00
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#define TIMING_CFG2_WR_DATA_DELAY_SHIFT	  10
#define TIMING_CFG2_CPO_DEF	  0x00000000	/* default (= CASLAT + 1) */
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	u32 sdram_cfg;		/**< SDRAM Control Configuration */
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#define SDRAM_CFG_MEM_EN     0x80000000
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#define SDRAM_CFG_SREN	     0x40000000
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#define SDRAM_CFG_ECC_EN     0x20000000
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#define SDRAM_CFG_RD_EN	     0x10000000
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#define SDRAM_CFG_SDRAM_TYPE 0x03000000
#define SDRAM_CFG_SDRAM_TYPE_SHIFT   24
#define SDRAM_CFG_DYN_PWR    0x00200000
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#define SDRAM_CFG_32_BE	     0x00080000
#define SDRAM_CFG_8_BE	     0x00040000
#define SDRAM_CFG_NCAP	     0x00020000
#define SDRAM_CFG_2T_EN	     0x00008000
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#define SDRAM_CFG_SDRAM_TYPE_DDR 0x02000000
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	u8 res2[4];
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	u32 sdram_mode;		/**< SDRAM Mode Configuration */
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#define SDRAM_MODE_ESD 0xFFFF0000
#define SDRAM_MODE_ESD_SHIFT   16
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#define SDRAM_MODE_SD  0x0000FFFF
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#define SDRAM_MODE_SD_SHIFT	0
#define DDR_MODE_EXT_MODEREG	0x4000	/* select extended mode reg */
#define DDR_MODE_EXT_OPMODE	0x3FF8	/* operating mode, mask */
#define DDR_MODE_EXT_OP_NORMAL	0x0000	/* normal operation */
#define DDR_MODE_QFC		0x0004	/* QFC / compatibility, mask */
#define DDR_MODE_QFC_COMP	0x0000	/* compatible to older SDRAMs */
#define DDR_MODE_WEAK		0x0002	/* weak drivers */
#define DDR_MODE_DLL_DIS	0x0001	/* disable DLL */
#define DDR_MODE_CASLAT		0x0070	/* CAS latency, mask */
#define DDR_MODE_CASLAT_15	0x0010	/* CAS latency 1.5 */
#define DDR_MODE_CASLAT_20	0x0020	/* CAS latency 2 */
#define DDR_MODE_CASLAT_25	0x0060	/* CAS latency 2.5 */
#define DDR_MODE_CASLAT_30	0x0030	/* CAS latency 3 */
#define DDR_MODE_BTYPE_SEQ	0x0000	/* sequential burst */
#define DDR_MODE_BTYPE_ILVD	0x0008	/* interleaved burst */
#define DDR_MODE_BLEN_2		0x0001	/* burst length 2 */
#define DDR_MODE_BLEN_4		0x0002	/* burst length 4 */
#define DDR_REFINT_166MHZ_7US	1302	/* exact value for 7.8125 µs */
#define DDR_BSTOPRE	256	/* use 256 cycles as a starting point */
#define DDR_MODE_MODEREG	0x0000	/* select mode register */
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	u8 res3[8];
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	u32 sdram_interval;	/**< SDRAM Interval Configuration */
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#define SDRAM_INTERVAL_REFINT  0x3FFF0000
#define SDRAM_INTERVAL_REFINT_SHIFT    16
#define SDRAM_INTERVAL_BSTOPRE 0x00003FFF
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#define SDRAM_INTERVAL_BSTOPRE_SHIFT	0
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	u8 res9[8];
	u32 sdram_clk_cntl;
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#define DDR_SDRAM_CLK_CNTL_SS_EN		0x80000000
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#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_025	0x01000000
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#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05	0x02000000
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#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075	0x03000000
#define DDR_SDRAM_CLK_CNTL_CLK_ADJUST_1		0x04000000
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	u8 res4[0xCCC];
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	u32 data_err_inject_hi; /**< Memory Data Path Error Injection Mask High */
	u32 data_err_inject_lo; /**< Memory Data Path Error Injection Mask Low */
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	u32 ecc_err_inject;	/**< Memory Data Path Error Injection Mask ECC */