fec_mxc.c 34.5 KB
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/*
 * (C) Copyright 2009 Ilya Yanok, Emcraft Systems Ltd <yanok@emcraft.com>
 * (C) Copyright 2008,2009 Eric Jarrige <eric.jarrige@armadeus.org>
 * (C) Copyright 2008 Armadeus Systems nc
 * (C) Copyright 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
 * (C) Copyright 2007 Pengutronix, Juergen Beisert <j.beisert@pengutronix.de>
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 * Copyright (C) 2016 Freescale Semiconductor, Inc.
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 *
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 * SPDX-License-Identifier:	GPL-2.0+
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 */

#include <common.h>
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#include <dm.h>
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#include <malloc.h>
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#include <memalign.h>
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#include <miiphy.h>
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#include <net.h>
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#include <netdev.h>
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#include "fec_mxc.h"

#include <asm/io.h>
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#include <linux/errno.h>
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#include <linux/compiler.h>
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#include <asm/arch/clock.h>
#include <asm/arch/imx-regs.h>
#include <asm/imx-common/sys_proto.h>
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#include <asm/arch/sys_proto.h>
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DECLARE_GLOBAL_DATA_PTR;

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/*
 * Timeout the transfer after 5 mS. This is usually a bit more, since
 * the code in the tightloops this timeout is used in adds some overhead.
 */
#define FEC_XFER_TIMEOUT	5000

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/*
 * The standard 32-byte DMA alignment does not work on mx6solox, which requires
 * 64-byte alignment in the DMA RX FEC buffer.
 * Introduce the FEC_DMA_RX_MINALIGN which can cover mx6solox needs and also
 * satisfies the alignment on other SoCs (32-bytes)
 */
#define FEC_DMA_RX_MINALIGN	64

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#ifndef CONFIG_MII
#error "CONFIG_MII has to be defined!"
#endif

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#ifndef CONFIG_FEC_XCV_TYPE
#define CONFIG_FEC_XCV_TYPE MII100
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#endif

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/*
 * The i.MX28 operates with packets in big endian. We need to swap them before
 * sending and after receiving.
 */
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#ifdef CONFIG_MX28
#define CONFIG_FEC_MXC_SWAP_PACKET
#endif

#define RXDESC_PER_CACHELINE (ARCH_DMA_MINALIGN/sizeof(struct fec_bd))

/* Check various alignment issues at compile time */
#if ((ARCH_DMA_MINALIGN < 16) || (ARCH_DMA_MINALIGN % 16 != 0))
#error "ARCH_DMA_MINALIGN must be multiple of 16!"
#endif

#if ((PKTALIGN < ARCH_DMA_MINALIGN) || \
	(PKTALIGN % ARCH_DMA_MINALIGN != 0))
#error "PKTALIGN must be multiple of ARCH_DMA_MINALIGN!"
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#endif

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#undef DEBUG

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#ifdef CONFIG_FEC_MXC_SWAP_PACKET
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static void swap_packet(uint32_t *packet, int length)
{
	int i;

	for (i = 0; i < DIV_ROUND_UP(length, 4); i++)
		packet[i] = __swab32(packet[i]);
}
#endif

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/* MII-interface related functions */
static int fec_mdio_read(struct ethernet_regs *eth, uint8_t phyaddr,
		uint8_t regaddr)
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{
	uint32_t reg;		/* convenient holder for the PHY register */
	uint32_t phy;		/* convenient holder for the PHY */
	uint32_t start;
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	int val;
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	/*
	 * reading from any PHY's register is done by properly
	 * programming the FEC's MII data register.
	 */
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	writel(FEC_IEVENT_MII, &eth->ievent);
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	reg = regaddr << FEC_MII_DATA_RA_SHIFT;
	phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
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	writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_RD | FEC_MII_DATA_TA |
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			phy | reg, &eth->mii_data);
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	/* wait for the related interrupt */
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	start = get_timer(0);
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	while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {
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		if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
			printf("Read MDIO failed...\n");
			return -1;
		}
	}

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	/* clear mii interrupt bit */
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	writel(FEC_IEVENT_MII, &eth->ievent);
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	/* it's now safe to read the PHY's register */
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	val = (unsigned short)readl(&eth->mii_data);
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	debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
	      regaddr, val);
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	return val;
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}

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static void fec_mii_setspeed(struct ethernet_regs *eth)
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{
	/*
	 * Set MII_SPEED = (1/(mii_speed * 2)) * System Clock
	 * and do not drop the Preamble.
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	 *
	 * The i.MX28 and i.MX6 types have another field in the MSCR (aka
	 * MII_SPEED) register that defines the MDIO output hold time. Earlier
	 * versions are RAZ there, so just ignore the difference and write the
	 * register always.
	 * The minimal hold time according to IEE802.3 (clause 22) is 10 ns.
	 * HOLDTIME + 1 is the number of clk cycles the fec is holding the
	 * output.
	 * The HOLDTIME bitfield takes values between 0 and 7 (inclusive).
	 * Given that ceil(clkrate / 5000000) <= 64, the calculation for
	 * holdtime cannot result in a value greater than 3.
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	 */
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	u32 pclk = imx_get_fecclk();
	u32 speed = DIV_ROUND_UP(pclk, 5000000);
	u32 hold = DIV_ROUND_UP(pclk, 100000000) - 1;
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#ifdef FEC_QUIRK_ENET_MAC
	speed--;
#endif
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	writel(speed << 1 | hold << 8, &eth->mii_speed);
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	debug("%s: mii_speed %08x\n", __func__, readl(&eth->mii_speed));
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}
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static int fec_mdio_write(struct ethernet_regs *eth, uint8_t phyaddr,
		uint8_t regaddr, uint16_t data)
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{
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	uint32_t reg;		/* convenient holder for the PHY register */
	uint32_t phy;		/* convenient holder for the PHY */
	uint32_t start;

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	reg = regaddr << FEC_MII_DATA_RA_SHIFT;
	phy = phyaddr << FEC_MII_DATA_PA_SHIFT;
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	writel(FEC_MII_DATA_ST | FEC_MII_DATA_OP_WR |
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		FEC_MII_DATA_TA | phy | reg | data, &eth->mii_data);
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	/* wait for the MII interrupt */
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	start = get_timer(0);
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	while (!(readl(&eth->ievent) & FEC_IEVENT_MII)) {
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		if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) {
			printf("Write MDIO failed...\n");
			return -1;
		}
	}

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	/* clear MII interrupt bit */
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	writel(FEC_IEVENT_MII, &eth->ievent);
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	debug("%s: phy: %02x reg:%02x val:%#x\n", __func__, phyaddr,
	      regaddr, data);
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	return 0;
}

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static int fec_phy_read(struct mii_dev *bus, int phyaddr, int dev_addr,
			int regaddr)
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{
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	return fec_mdio_read(bus->priv, phyaddr, regaddr);
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}

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static int fec_phy_write(struct mii_dev *bus, int phyaddr, int dev_addr,
			 int regaddr, u16 data)
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{
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	return fec_mdio_write(bus->priv, phyaddr, regaddr, data);
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}

#ifndef CONFIG_PHYLIB
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static int miiphy_restart_aneg(struct eth_device *dev)
{
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	int ret = 0;
#if !defined(CONFIG_FEC_MXC_NO_ANEG)
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	struct fec_priv *fec = (struct fec_priv *)dev->priv;
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	struct ethernet_regs *eth = fec->bus->priv;
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	/*
	 * Wake up from sleep if necessary
	 * Reset PHY, then delay 300ns
	 */
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#ifdef CONFIG_MX27
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	fec_mdio_write(eth, fec->phy_id, MII_DCOUNTER, 0x00FF);
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#endif
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	fec_mdio_write(eth, fec->phy_id, MII_BMCR, BMCR_RESET);
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	udelay(1000);

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	/* Set the auto-negotiation advertisement register bits */
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	fec_mdio_write(eth, fec->phy_id, MII_ADVERTISE,
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		       LPA_100FULL | LPA_100HALF | LPA_10FULL |
		       LPA_10HALF | PHY_ANLPAR_PSB_802_3);
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	fec_mdio_write(eth, fec->phy_id, MII_BMCR,
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		       BMCR_ANENABLE | BMCR_ANRESTART);
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	if (fec->mii_postcall)
		ret = fec->mii_postcall(fec->phy_id);

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#endif
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	return ret;
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}

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#ifndef CONFIG_FEC_FIXED_SPEED
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static int miiphy_wait_aneg(struct eth_device *dev)
{
	uint32_t start;
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	int status;
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	struct fec_priv *fec = (struct fec_priv *)dev->priv;
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	struct ethernet_regs *eth = fec->bus->priv;
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	/* Wait for AN completion */
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	start = get_timer(0);
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	do {
		if (get_timer(start) > (CONFIG_SYS_HZ * 5)) {
			printf("%s: Autonegotiation timeout\n", dev->name);
			return -1;
		}

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		status = fec_mdio_read(eth, fec->phy_id, MII_BMSR);
		if (status < 0) {
			printf("%s: Autonegotiation failed. status: %d\n",
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			       dev->name, status);
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			return -1;
		}
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	} while (!(status & BMSR_LSTATUS));
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	return 0;
}
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#endif /* CONFIG_FEC_FIXED_SPEED */
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#endif

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static int fec_rx_task_enable(struct fec_priv *fec)
{
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	writel(FEC_R_DES_ACTIVE_RDAR, &fec->eth->r_des_active);
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	return 0;
}

static int fec_rx_task_disable(struct fec_priv *fec)
{
	return 0;
}

static int fec_tx_task_enable(struct fec_priv *fec)
{
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	writel(FEC_X_DES_ACTIVE_TDAR, &fec->eth->x_des_active);
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	return 0;
}

static int fec_tx_task_disable(struct fec_priv *fec)
{
	return 0;
}

/**
 * Initialize receive task's buffer descriptors
 * @param[in] fec all we know about the device yet
 * @param[in] count receive buffer count to be allocated
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 * @param[in] dsize desired size of each receive buffer
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 * @return 0 on success
 *
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 * Init all RX descriptors to default values.
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 */
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static void fec_rbd_init(struct fec_priv *fec, int count, int dsize)
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{
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	uint32_t size;
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	ulong data;
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	int i;

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	/*
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	 * Reload the RX descriptors with default values and wipe
	 * the RX buffers.
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	 */
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	size = roundup(dsize, ARCH_DMA_MINALIGN);
	for (i = 0; i < count; i++) {
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		data = fec->rbd_base[i].data_pointer;
		memset((void *)data, 0, dsize);
		flush_dcache_range(data, data + size);
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		fec->rbd_base[i].status = FEC_RBD_EMPTY;
		fec->rbd_base[i].data_length = 0;
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	}

	/* Mark the last RBD to close the ring. */
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	fec->rbd_base[i - 1].status = FEC_RBD_WRAP | FEC_RBD_EMPTY;
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	fec->rbd_index = 0;

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	flush_dcache_range((ulong)fec->rbd_base,
			   (ulong)fec->rbd_base + size);
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}

/**
 * Initialize transmit task's buffer descriptors
 * @param[in] fec all we know about the device yet
 *
 * Transmit buffers are created externally. We only have to init the BDs here.\n
 * Note: There is a race condition in the hardware. When only one BD is in
 * use it must be marked with the WRAP bit to use it for every transmitt.
 * This bit in combination with the READY bit results into double transmit
 * of each data buffer. It seems the state machine checks READY earlier then
 * resetting it after the first transfer.
 * Using two BDs solves this issue.
 */
static void fec_tbd_init(struct fec_priv *fec)
{
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	ulong addr = (ulong)fec->tbd_base;
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	unsigned size = roundup(2 * sizeof(struct fec_bd),
				ARCH_DMA_MINALIGN);
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	memset(fec->tbd_base, 0, size);
	fec->tbd_base[0].status = 0;
	fec->tbd_base[1].status = FEC_TBD_WRAP;
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	fec->tbd_index = 0;
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	flush_dcache_range(addr, addr + size);
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}

/**
 * Mark the given read buffer descriptor as free
 * @param[in] last 1 if this is the last buffer descriptor in the chain, else 0
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 * @param[in] prbd buffer descriptor to mark free again
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 */
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static void fec_rbd_clean(int last, struct fec_bd *prbd)
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{
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	unsigned short flags = FEC_RBD_EMPTY;
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	if (last)
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		flags |= FEC_RBD_WRAP;
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	writew(flags, &prbd->status);
	writew(0, &prbd->data_length);
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}

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static int fec_get_hwaddr(int dev_id, unsigned char *mac)
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{
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	imx_get_mac_from_fuse(dev_id, mac);
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	return !is_valid_ethaddr(mac);
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}

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#ifdef CONFIG_DM_ETH
static int fecmxc_set_hwaddr(struct udevice *dev)
#else
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static int fec_set_hwaddr(struct eth_device *dev)
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#endif
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{
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#ifdef CONFIG_DM_ETH
	struct fec_priv *fec = dev_get_priv(dev);
	struct eth_pdata *pdata = dev_get_platdata(dev);
	uchar *mac = pdata->enetaddr;
#else
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	uchar *mac = dev->enetaddr;
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	struct fec_priv *fec = (struct fec_priv *)dev->priv;
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#endif
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	writel(0, &fec->eth->iaddr1);
	writel(0, &fec->eth->iaddr2);
	writel(0, &fec->eth->gaddr1);
	writel(0, &fec->eth->gaddr2);

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	/* Set physical address */
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	writel((mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3],
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	       &fec->eth->paddr1);
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	writel((mac[4] << 24) + (mac[5] << 16) + 0x8808, &fec->eth->paddr2);

	return 0;
}

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/* Do initial configuration of the FEC registers */
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static void fec_reg_setup(struct fec_priv *fec)
{
	uint32_t rcntrl;

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	/* Set interrupt mask register */
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	writel(0x00000000, &fec->eth->imask);

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	/* Clear FEC-Lite interrupt event register(IEVENT) */
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	writel(0xffffffff, &fec->eth->ievent);

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	/* Set FEC-Lite receive control register(R_CNTRL): */
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	/* Start with frame length = 1518, common for all modes. */
	rcntrl = PKTSIZE << FEC_RCNTRL_MAX_FL_SHIFT;
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	if (fec->xcv_type != SEVENWIRE)		/* xMII modes */
		rcntrl |= FEC_RCNTRL_FCE | FEC_RCNTRL_MII_MODE;
	if (fec->xcv_type == RGMII)
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		rcntrl |= FEC_RCNTRL_RGMII;
	else if (fec->xcv_type == RMII)
		rcntrl |= FEC_RCNTRL_RMII;

	writel(rcntrl, &fec->eth->r_cntrl);
}

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/**
 * Start the FEC engine
 * @param[in] dev Our device to handle
 */
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#ifdef CONFIG_DM_ETH
static int fec_open(struct udevice *dev)
#else
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static int fec_open(struct eth_device *edev)
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#endif
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{
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#ifdef CONFIG_DM_ETH
	struct fec_priv *fec = dev_get_priv(dev);
#else
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	struct fec_priv *fec = (struct fec_priv *)edev->priv;
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#endif
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	int speed;
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	ulong addr, size;
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	int i;
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	debug("fec_open: fec_open(dev)\n");
	/* full-duplex, heartbeat disabled */
	writel(1 << 2, &fec->eth->x_cntrl);
	fec->rbd_index = 0;

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	/* Invalidate all descriptors */
	for (i = 0; i < FEC_RBD_NUM - 1; i++)
		fec_rbd_clean(0, &fec->rbd_base[i]);
	fec_rbd_clean(1, &fec->rbd_base[i]);

	/* Flush the descriptors into RAM */
	size = roundup(FEC_RBD_NUM * sizeof(struct fec_bd),
			ARCH_DMA_MINALIGN);
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	addr = (ulong)fec->rbd_base;
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	flush_dcache_range(addr, addr + size);

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#ifdef FEC_QUIRK_ENET_MAC
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	/* Enable ENET HW endian SWAP */
	writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_DBSWAP,
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	       &fec->eth->ecntrl);
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	/* Enable ENET store and forward mode */
	writel(readl(&fec->eth->x_wmrk) | FEC_X_WMRK_STRFWD,
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	       &fec->eth->x_wmrk);
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#endif
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	/* Enable FEC-Lite controller */
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	writel(readl(&fec->eth->ecntrl) | FEC_ECNTRL_ETHER_EN,
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	       &fec->eth->ecntrl);

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#if defined(CONFIG_MX25) || defined(CONFIG_MX53) || defined(CONFIG_MX6SL)
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	udelay(100);

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	/* setup the MII gasket for RMII mode */
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	/* disable the gasket */
	writew(0, &fec->eth->miigsk_enr);

	/* wait for the gasket to be disabled */
	while (readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY)
		udelay(2);

	/* configure gasket for RMII, 50 MHz, no loopback, and no echo */
	writew(MIIGSK_CFGR_IF_MODE_RMII, &fec->eth->miigsk_cfgr);

	/* re-enable the gasket */
	writew(MIIGSK_ENR_EN, &fec->eth->miigsk_enr);

	/* wait until MII gasket is ready */
	int max_loops = 10;
	while ((readw(&fec->eth->miigsk_enr) & MIIGSK_ENR_READY) == 0) {
		if (--max_loops <= 0) {
			printf("WAIT for MII Gasket ready timed out\n");
			break;
		}
	}
#endif
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#ifdef CONFIG_PHYLIB
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	{
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		/* Start up the PHY */
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		int ret = phy_startup(fec->phydev);

		if (ret) {
			printf("Could not initialize PHY %s\n",
			       fec->phydev->dev->name);
			return ret;
		}
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		speed = fec->phydev->speed;
	}
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#elif CONFIG_FEC_FIXED_SPEED
	speed = CONFIG_FEC_FIXED_SPEED;
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#else
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	miiphy_wait_aneg(edev);
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	speed = miiphy_speed(edev->name, fec->phy_id);
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	miiphy_duplex(edev->name, fec->phy_id);
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#endif
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#ifdef FEC_QUIRK_ENET_MAC
	{
		u32 ecr = readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_SPEED;
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		u32 rcr = readl(&fec->eth->r_cntrl) & ~FEC_RCNTRL_RMII_10T;
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		if (speed == _1000BASET)
			ecr |= FEC_ECNTRL_SPEED;
		else if (speed != _100BASET)
			rcr |= FEC_RCNTRL_RMII_10T;
		writel(ecr, &fec->eth->ecntrl);
		writel(rcr, &fec->eth->r_cntrl);
	}
#endif
	debug("%s:Speed=%i\n", __func__, speed);

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	/* Enable SmartDMA receive task */
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	fec_rx_task_enable(fec);

	udelay(100000);
	return 0;
}

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#ifdef CONFIG_DM_ETH
static int fecmxc_init(struct udevice *dev)
#else
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static int fec_init(struct eth_device *dev, bd_t *bd)
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#endif
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{
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#ifdef CONFIG_DM_ETH
	struct fec_priv *fec = dev_get_priv(dev);
#else
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	struct fec_priv *fec = (struct fec_priv *)dev->priv;
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#endif
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	uint8_t *mib_ptr = (uint8_t *)&fec->eth->rmon_t_drop;
	uint8_t *i;
	ulong addr;
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	/* Initialize MAC address */
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#ifdef CONFIG_DM_ETH
	fecmxc_set_hwaddr(dev);
#else
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	fec_set_hwaddr(dev);
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#endif
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	/* Setup transmit descriptors, there are two in total. */
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	fec_tbd_init(fec);
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	/* Setup receive descriptors. */
	fec_rbd_init(fec, FEC_RBD_NUM, FEC_MAX_PKT_SIZE);
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	fec_reg_setup(fec);
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	if (fec->xcv_type != SEVENWIRE)
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		fec_mii_setspeed(fec->bus->priv);
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	/* Set Opcode/Pause Duration Register */
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	writel(0x00010020, &fec->eth->op_pause);	/* FIXME 0xffff0020; */
	writel(0x2, &fec->eth->x_wmrk);
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	/* Set multicast address filter */
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	writel(0x00000000, &fec->eth->gaddr1);
	writel(0x00000000, &fec->eth->gaddr2);

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	/* Do not access reserved register for i.MX6UL/6ULL/i.MX8/i.MX8M */
	if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m()) {
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		/* clear MIB RAM */
		for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
			writel(0, i);
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		/* FIFO receive start register */
		writel(0x520, &fec->eth->r_fstart);
	}
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	/* size and address of each buffer */
	writel(FEC_MAX_PKT_SIZE, &fec->eth->emrbr);
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	addr = (ulong)fec->tbd_base;
	writel((uint32_t)addr, &fec->eth->etdsr);

	addr = (ulong)fec->rbd_base;
	writel((uint32_t)addr, &fec->eth->erdsr);
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#ifndef CONFIG_PHYLIB
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	if (fec->xcv_type != SEVENWIRE)
		miiphy_restart_aneg(dev);
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#endif
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	fec_open(dev);
	return 0;
}

/**
 * Halt the FEC engine
 * @param[in] dev Our device to handle
 */
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#ifdef CONFIG_DM_ETH
static void fecmxc_halt(struct udevice *dev)
#else
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static void fec_halt(struct eth_device *dev)
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#endif
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{
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#ifdef CONFIG_DM_ETH
	struct fec_priv *fec = dev_get_priv(dev);
#else
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	struct fec_priv *fec = (struct fec_priv *)dev->priv;
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#endif
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	int counter = 0xffff;

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	/* issue graceful stop command to the FEC transmitter if necessary */
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	writel(FEC_TCNTRL_GTS | readl(&fec->eth->x_cntrl),
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	       &fec->eth->x_cntrl);
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	debug("eth_halt: wait for stop regs\n");
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	/* wait for graceful stop to register */
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	while ((counter--) && (!(readl(&fec->eth->ievent) & FEC_IEVENT_GRA)))
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		udelay(1);
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	/* Disable SmartDMA tasks */
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	fec_tx_task_disable(fec);
	fec_rx_task_disable(fec);

	/*
	 * Disable the Ethernet Controller
	 * Note: this will also reset the BD index counter!
	 */
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	writel(readl(&fec->eth->ecntrl) & ~FEC_ECNTRL_ETHER_EN,
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	       &fec->eth->ecntrl);
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	fec->rbd_index = 0;
	fec->tbd_index = 0;
	debug("eth_halt: done\n");
}

/**
 * Transmit one frame
 * @param[in] dev Our ethernet device to handle
 * @param[in] packet Pointer to the data to be transmitted
 * @param[in] length Data count in bytes
 * @return 0 on success
 */
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#ifdef CONFIG_DM_ETH
static int fecmxc_send(struct udevice *dev, void *packet, int length)
#else
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static int fec_send(struct eth_device *dev, void *packet, int length)
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#endif
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{
	unsigned int status;
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	uint32_t size;
	ulong addr, end;
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	int timeout = FEC_XFER_TIMEOUT;
	int ret = 0;
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	/*
	 * This routine transmits one frame.  This routine only accepts
	 * 6-byte Ethernet addresses.
	 */
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#ifdef CONFIG_DM_ETH
	struct fec_priv *fec = dev_get_priv(dev);
#else
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	struct fec_priv *fec = (struct fec_priv *)dev->priv;
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#endif
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	/*
	 * Check for valid length of data.
	 */
	if ((length > 1500) || (length <= 0)) {
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		printf("Payload (%d) too large\n", length);
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		return -1;
	}

	/*
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	 * Setup the transmit buffer. We are always using the first buffer for
	 * transmission, the second will be empty and only used to stop the DMA
	 * engine. We also flush the packet to RAM here to avoid cache trouble.
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	 */
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#ifdef CONFIG_FEC_MXC_SWAP_PACKET
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	swap_packet((uint32_t *)packet, length);
#endif
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	addr = (ulong)packet;
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	end = roundup(addr + length, ARCH_DMA_MINALIGN);
	addr &= ~(ARCH_DMA_MINALIGN - 1);
	flush_dcache_range(addr, end);
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	writew(length, &fec->tbd_base[fec->tbd_index].data_length);
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	writel((uint32_t)addr, &fec->tbd_base[fec->tbd_index].data_pointer);
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	/*
	 * update BD's status now
	 * This block:
	 * - is always the last in a chain (means no chain)
	 * - should transmitt the CRC
	 * - might be the last BD in the list, so the address counter should
	 *   wrap (-> keep the WRAP flag)
	 */
	status = readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_WRAP;
	status |= FEC_TBD_LAST | FEC_TBD_TC | FEC_TBD_READY;
	writew(status, &fec->tbd_base[fec->tbd_index].status);

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	/*
	 * Flush data cache. This code flushes both TX descriptors to RAM.
	 * After this code, the descriptors will be safely in RAM and we
	 * can start DMA.
	 */
	size = roundup(2 * sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
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	addr = (ulong)fec->tbd_base;
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	flush_dcache_range(addr, addr + size);

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	/*
	 * Below we read the DMA descriptor's last four bytes back from the
	 * DRAM. This is important in order to make sure that all WRITE
	 * operations on the bus that were triggered by previous cache FLUSH
	 * have completed.
	 *
	 * Otherwise, on MX28, it is possible to observe a corruption of the
	 * DMA descriptors. Please refer to schematic "Figure 1-2" in MX28RM
	 * for the bus structure of MX28. The scenario is as follows:
	 *
	 * 1) ARM core triggers a series of WRITEs on the AHB_ARB2 bus going
	 *    to DRAM due to flush_dcache_range()
	 * 2) ARM core writes the FEC registers via AHB_ARB2
	 * 3) FEC DMA starts reading/writing from/to DRAM via AHB_ARB3
	 *
	 * Note that 2) does sometimes finish before 1) due to reordering of
	 * WRITE accesses on the AHB bus, therefore triggering 3) before the
	 * DMA descriptor is fully written into DRAM. This results in occasional
	 * corruption of the DMA descriptor.
	 */
	readl(addr + size - 4);

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	/* Enable SmartDMA transmit task */
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	fec_tx_task_enable(fec);

	/*
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	 * Wait until frame is sent. On each turn of the wait cycle, we must
	 * invalidate data cache to see what's really in RAM. Also, we need
	 * barrier here.
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	 */
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	while (--timeout) {
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		if (!(readl(&fec->eth->x_des_active) & FEC_X_DES_ACTIVE_TDAR))
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			break;
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	}
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	if (!timeout) {
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		ret = -EINVAL;
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		goto out;
	}

	/*
	 * The TDAR bit is cleared when the descriptors are all out from TX
	 * but on mx6solox we noticed that the READY bit is still not cleared
	 * right after TDAR.
	 * These are two distinct signals, and in IC simulation, we found that
	 * TDAR always gets cleared prior than the READY bit of last BD becomes
	 * cleared.
	 * In mx6solox, we use a later version of FEC IP. It looks like that
	 * this intrinsic behaviour of TDAR bit has changed in this newer FEC
	 * version.
	 *
	 * Fix this by polling the READY bit of BD after the TDAR polling,
	 * which covers the mx6solox case and does not harm the other SoCs.
	 */
	timeout = FEC_XFER_TIMEOUT;
	while (--timeout) {
		invalidate_dcache_range(addr, addr + size);
		if (!(readw(&fec->tbd_base[fec->tbd_index].status) &
		    FEC_TBD_READY))
			break;
	}
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	if (!timeout)
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		ret = -EINVAL;

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out:
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	debug("fec_send: status 0x%x index %d ret %i\n",
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	      readw(&fec->tbd_base[fec->tbd_index].status),
	      fec->tbd_index, ret);
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	/* for next transmission use the other buffer */
	if (fec->tbd_index)
		fec->tbd_index = 0;
	else
		fec->tbd_index = 1;

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	return ret;
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}

/**
 * Pull one frame from the card
 * @param[in] dev Our ethernet device to handle
 * @return Length of packet read
 */
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#ifdef CONFIG_DM_ETH
static int fecmxc_recv(struct udevice *dev, int flags, uchar **packetp)
#else
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static int fec_recv(struct eth_device *dev)
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#endif
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{
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#ifdef CONFIG_DM_ETH
	struct fec_priv *fec = dev_get_priv(dev);
#else
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	struct fec_priv *fec = (struct fec_priv *)dev->priv;
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#endif
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	struct fec_bd *rbd = &fec->rbd_base[fec->rbd_index];
	unsigned long ievent;
	int frame_length, len = 0;
	uint16_t bd_status;
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	ulong addr, size, end;
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	int i;
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#ifdef CONFIG_DM_ETH
	*packetp = memalign(ARCH_DMA_MINALIGN, FEC_MAX_PKT_SIZE);
	if (*packetp == 0) {
		printf("%s: error allocating packetp\n", __func__);
		return -ENOMEM;
	}
#else
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	ALLOC_CACHE_ALIGN_BUFFER(uchar, buff, FEC_MAX_PKT_SIZE);
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#endif
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	/* Check if any critical events have happened */
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	ievent = readl(&fec->eth->ievent);
	writel(ievent, &fec->eth->ievent);
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	debug("fec_recv: ievent 0x%lx\n", ievent);
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	if (ievent & FEC_IEVENT_BABR) {
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#ifdef CONFIG_DM_ETH
		fecmxc_halt(dev);
		fecmxc_init(dev);
#else
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		fec_halt(dev);
		fec_init(dev, fec->bd);
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#endif
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		printf("some error: 0x%08lx\n", ievent);
		return 0;
	}
	if (ievent & FEC_IEVENT_HBERR) {
		/* Heartbeat error */
		writel(0x00000001 | readl(&fec->eth->x_cntrl),
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		       &fec->eth->x_cntrl);
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	}
	if (ievent & FEC_IEVENT_GRA) {
		/* Graceful stop complete */
		if (readl(&fec->eth->x_cntrl) & 0x00000001) {
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#ifdef CONFIG_DM_ETH
			fecmxc_halt(dev);
#else
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			fec_halt(dev);
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#endif
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			writel(~0x00000001 & readl(&fec->eth->x_cntrl),
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			       &fec->eth->x_cntrl);
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#ifdef CONFIG_DM_ETH
			fecmxc_init(dev);
#else
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			fec_init(dev, fec->bd);
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#endif
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		}
	}

	/*
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	 * Read the buffer status. Before the status can be read, the data cache
	 * must be invalidated, because the data in RAM might have been changed
	 * by DMA. The descriptors are properly aligned to cachelines so there's
	 * no need to worry they'd overlap.
	 *
	 * WARNING: By invalidating the descriptor here, we also invalidate
	 * the descriptors surrounding this one. Therefore we can NOT change the
	 * contents of this descriptor nor the surrounding ones. The problem is
	 * that in order to mark the descriptor as processed, we need to change
	 * the descriptor. The solution is to mark the whole cache line when all
	 * descriptors in the cache line are processed.
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	 */
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	addr = (ulong)rbd;
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	addr &= ~(ARCH_DMA_MINALIGN - 1);
	size = roundup(sizeof(struct fec_bd), ARCH_DMA_MINALIGN);
	invalidate_dcache_range(addr, addr + size);

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	bd_status = readw(&rbd->status);
	debug("fec_recv: status 0x%x\n", bd_status);

	if (!(bd_status & FEC_RBD_EMPTY)) {
		if ((bd_status & FEC_RBD_LAST) && !(bd_status & FEC_RBD_ERR) &&
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		    ((readw(&rbd->data_length) - 4) > 14)) {
			/* Get buffer address and size */
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			addr = readl(&rbd->data_pointer);
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			frame_length = readw(&rbd->data_length) - 4;
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			/* Invalidate data cache over the buffer */
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			end = roundup(addr + frame_length, ARCH_DMA_MINALIGN);
			addr &= ~(ARCH_DMA_MINALIGN - 1);
			invalidate_dcache_range(addr, end);
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			/* Fill the buffer and pass it to upper layers */