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Simon Glass authored
It is possible that our PCI bus will provide the SPI controller, so change the init order to make this work. Signed-off-by: Simon Glass <sjg@chromium.org>
192868b0
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It is possible that our PCI bus will provide the SPI controller, so change
the init order to make this work.
Signed-off-by: Simon Glass <sjg@chromium.org>