For booting M4 running in DDR, we use fatload to load the image to DDR first.
The fatload will do a copy for block size unaligned data in the tail. Since the DDR
area is cachable, so this cause a memory coherence issue. Need to use dcache flush
command before booting the M4 core.

This patch enables the CONFIG_CMD_CACHE and add the dcache flush to M4 boot commands
no matter the M4 runs in DDR or TCM.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>