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  • Simon Glass's avatar
    x86: Add support for MTRRs · aff2523f
    Simon Glass authored
    
    
    Memory Type Range Registers are used to tell the CPU whether memory is
    cacheable and if so the cache write mode to use.
    
    Clean up the existing header file to follow style, and remove the unneeded
    code.
    
    These can speed up booting so should be supported. Add these to global_data
    so they can be requested while booting. We will apply the changes during
    relocation (in a later commit).
    
    Signed-off-by: default avatarSimon Glass <sjg@chromium.org>
    aff2523f