Commit 00dd3f6a authored by Masahiro Yamada's avatar Masahiro Yamada
Browse files

ARM: uniphier: remove UMC_INITCTL* and UMC_DRMR* settings



These settings were used only for the PH1-sLD3 and older SoCs.  The
PH1-LD4 and newer one just ignore them because their DDR-PHY take
care of such timing parameters instead.
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
parent 94b756f3
......@@ -53,38 +53,11 @@ static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
if (freq == 1333) {
writel(0x45990b11, dramcont + UMC_CMDCTLA);
writel(0x16958924, dramcont + UMC_CMDCTLB);
writel(0x5101046A, dramcont + UMC_INITCTLA);
if (size == 1)
writel(0x27028B0A, dramcont + UMC_INITCTLB);
else if (size == 2)
writel(0x38028B0A, dramcont + UMC_INITCTLB);
writel(0x000FF0FF, dramcont + UMC_INITCTLC);
writel(0x00000b51, dramcont + UMC_DRMMR0);
} else if (freq == 1600) {
writel(0x36BB0F17, dramcont + UMC_CMDCTLA);
writel(0x18C6AA24, dramcont + UMC_CMDCTLB);
writel(0x5101387F, dramcont + UMC_INITCTLA);
if (size == 1)
writel(0x2F030D3F, dramcont + UMC_INITCTLB);
else if (size == 2)
writel(0x43030D3F, dramcont + UMC_INITCTLB);
writel(0x00FF00FF, dramcont + UMC_INITCTLC);
writel(0x00000d71, dramcont + UMC_DRMMR0);
}
writel(0x00000006, dramcont + UMC_DRMMR1);
if (freq == 1333)
writel(0x00000290, dramcont + UMC_DRMMR2);
else if (freq == 1600)
writel(0x00000298, dramcont + UMC_DRMMR2);
writel(0x00000800, dramcont + UMC_DRMMR3);
if (freq == 1333) {
if (size == 1)
writel(0x00240512, dramcont + UMC_SPCCTLA);
......
......@@ -20,7 +20,6 @@ enum dram_size {
DRAM_SZ_NR,
};
static u32 umc_initctlb[DRAM_SZ_NR] = {0x43030d3f, 0x43030d3f, 0x7b030d3f};
static u32 umc_spcctla[DRAM_SZ_NR] = {0x002b0617, 0x003f0617, 0x00770617};
static void umc_start_ssif(void __iomem *ssif_base)
......@@ -88,13 +87,6 @@ static int umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
writel(0x66bb0f17, dramcont + UMC_CMDCTLA);
writel(0x18c6aa44, dramcont + UMC_CMDCTLB);
writel(0x5101387f, dramcont + UMC_INITCTLA);
writel(umc_initctlb[dram_size], dramcont + UMC_INITCTLB);
writel(0x00ff00ff, dramcont + UMC_INITCTLC);
writel(0x00000d71, dramcont + UMC_DRMMR0);
writel(0x00000006, dramcont + UMC_DRMMR1);
writel(0x00000298, dramcont + UMC_DRMMR2);
writel(0x00000000, dramcont + UMC_DRMMR3);
writel(umc_spcctla[dram_size], dramcont + UMC_SPCCTLA);
writel(0x00ff0008, dramcont + UMC_SPCCTLB);
writel(0x000c00ae, dramcont + UMC_RDATACTL_D0);
......
......@@ -58,24 +58,6 @@ static void umc_dramcont_init(void __iomem *dramcont, void __iomem *ca_base,
writel(0x16958924, dramcont + UMC_CMDCTLB);
#endif
writel(0x5101046A, dramcont + UMC_INITCTLA);
if (size == 1)
writel(0x27028B0A, dramcont + UMC_INITCTLB);
else if (size == 2)
writel(0x38028B0A, dramcont + UMC_INITCTLB);
writel(0x00FF00FF, dramcont + UMC_INITCTLC);
writel(0x00000b51, dramcont + UMC_DRMMR0);
writel(0x00000006, dramcont + UMC_DRMMR1);
writel(0x00000290, dramcont + UMC_DRMMR2);
#ifdef CONFIG_DDR_STANDARD
writel(0x00000000, dramcont + UMC_DRMMR3);
#else
writel(0x00000800, dramcont + UMC_DRMMR3);
#endif
if (size == 1)
writel(0x00240512, dramcont + UMC_SPCCTLA);
else if (size == 2)
......
......@@ -56,15 +56,8 @@
#define UMC_CMDCTLA 0x00000000
#define UMC_CMDCTLB 0x00000004
#define UMC_INITCTLA 0x00000008
#define UMC_INITCTLB 0x0000000C
#define UMC_INITCTLC 0x00000010
#define UMC_INITSET 0x00000014
#define UMC_INITSTAT 0x00000018
#define UMC_DRMMR0 0x0000001C
#define UMC_DRMMR1 0x00000020
#define UMC_DRMMR2 0x00000024
#define UMC_DRMMR3 0x00000028
#define UMC_SPCCTLA 0x00000030
#define UMC_SPCCTLB 0x00000034
#define UMC_SPCSETA 0x00000038
......
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