Commit 02c631e6 authored by Wolfgang Denk's avatar Wolfgang Denk

Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx

parents 8b0ab304 a3f5da1b
......@@ -36,6 +36,7 @@ Reinhard Arlt <reinhard.arlt@esd-electronics.com>
mecp5200 MPC5200
pf5200 MPC5200
caddy2 MPC8349
vme8349 MPC8349
CPCI750 PPC750FX/GX
......
......@@ -358,10 +358,12 @@ LIST_8260=" \
#########################################################################
LIST_83xx=" \
caddy2 \
kmeter1 \
MPC8313ERDB_33 \
MPC8313ERDB_NAND_66 \
MPC8315ERDB \
MPC8315ERDB_NAND \
MPC8323ERDB \
MPC832XEMDS \
MPC832XEMDS_ATM \
......
......@@ -2261,8 +2261,12 @@ MPC8313ERDB_NAND_66_config: unconfig
echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk ; \
fi ;
MPC8315ERDB_NAND_config \
MPC8315ERDB_config: unconfig
@$(MKCONFIG) -a MPC8315ERDB ppc mpc83xx mpc8315erdb freescale
@if [ "$(findstring _NAND_,$@)" ] ; then \
ln -sf mpc8313erdb nand_spl/board/freescale/mpc8315erdb ; \
fi ;
@$(MKCONFIG) -t $(@:_config=) MPC8315ERDB ppc mpc83xx mpc8315erdb freescale
MPC8323ERDB_config: unconfig
@$(MKCONFIG) -a MPC8323ERDB ppc mpc83xx mpc8323erdb freescale
......@@ -2396,8 +2400,9 @@ SIMPC8313_SP_config: unconfig
TQM834x_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc83xx tqm834x tqc
caddy2_config \
vme8349_config: unconfig
@$(MKCONFIG) $(@:_config=) ppc mpc83xx vme8349 esd
@$(MKCONFIG) -t $(@:_config=) vme8349 ppc mpc83xx vme8349 esd
#########################################################################
## MPC85xx Systems
......
......@@ -2,6 +2,9 @@
* pci.c -- esd VME8349 PCI board support.
* Copyright (c) 2006 Wind River Systems, Inc.
* Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
* Copyright (c) 2009 esd gmbh.
*
* Reinhard Arlt <reinhard.arlt@esd-electronics.com>
*
* Based on MPC8349 PCI support but w/o PIB related code.
*
......@@ -32,6 +35,7 @@
#include <pci.h>
#include <i2c.h>
#include <asm/fsl_i2c.h>
#include "vme8349pin.h"
DECLARE_GLOBAL_DATA_PTR;
......@@ -93,17 +97,22 @@ pci_init_board(void)
udelay(2000);
/*
* Assert/deassert PCI reset
* Assert/deassert VME reset
*/
setbits_be32(&immr->gpio[0].dat, 0x00800000);
setbits_be32(&immr->gpio[0].dir, 0x00800000);
setbits_be32(&immr->gpio[1].dir, 0x08800000);
clrsetbits_be32(&immr->gpio[1].dat,
GPIO2_TSI_POWERUP_RESET_N | GPIO2_TSI_PLL_RESET_N,
GPIO2_VME_RESET_N | GPIO2_L_RESET_EN_N);
setbits_be32(&immr->gpio[1].dir, GPIO2_TSI_PLL_RESET_N |
GPIO2_TSI_POWERUP_RESET_N |
GPIO2_VME_RESET_N |
GPIO2_L_RESET_EN_N);
clrbits_be32(&immr->gpio[1].dir, GPIO2_V_SCON);
udelay(200);
setbits_be32(&immr->gpio[1].dat, 0x08000000);
setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_PLL_RESET_N);
udelay(200);
setbits_be32(&immr->gpio[1].dat, 0x08800000);
setbits_be32(&immr->gpio[1].dat, GPIO2_TSI_POWERUP_RESET_N);
udelay(600000);
clrbits_be32(&immr->gpio[1].dat, 0x00100000);
clrbits_be32(&immr->gpio[1].dat, GPIO2_L_RESET_EN_N);
/* Configure PCI Local Access Windows */
pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
......@@ -114,6 +123,14 @@ pci_init_board(void)
udelay(2000);
if (monarch == 0)
if (monarch == 0) {
mpc83xx_pci_init(1, reg, 0);
} else {
/*
* Release PCI RST Output signal
*/
out_be32(&immr->pci_ctrl[0].gcr, 0);
udelay(2000);
out_be32(&immr->pci_ctrl[0].gcr, 1);
}
}
......@@ -38,63 +38,13 @@
#endif
#include <asm/io.h>
#include <asm/mmu.h>
#include <spd.h>
#include <spd_sdram.h>
#include <i2c.h>
#include <netdev.h>
void ddr_enable_ecc(unsigned int dram_size);
int fixed_sdram(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize = 0;
u32 ddr_size;
u32 ddr_size_log2;
msize = CONFIG_SYS_DDR_SIZE;
for (ddr_size = msize << 20, ddr_size_log2 = 0;
(ddr_size > 1);
ddr_size = ddr_size>>1, ddr_size_log2++) {
if (ddr_size & 1)
return -1;
}
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) &
LAWAR_SIZE);
#if (CONFIG_SYS_DDR_SIZE == 512)
im->ddr.csbnds[0].csbnds = 0x0000001f;
#else
#warning Currently any DDR size other than 512MiB is not supported
#endif
im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG | 0x00330000;
/* currently we use only one CS, so disable the other banks */
im->ddr.csbnds[1].csbnds = 0x00000000;
im->ddr.csbnds[2].csbnds = 0x00000000;
im->ddr.csbnds[3].csbnds = 0x00000000;
im->ddr.cs_config[1] = 0;
im->ddr.cs_config[2] = 0;
im->ddr.cs_config[3] = 0;
im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
sync();
udelay(200);
/* enable DDR controller */
im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
return msize;
}
phys_size_t initdram(int board_type)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
......@@ -103,10 +53,10 @@ phys_size_t initdram(int board_type)
if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
return -1;
/* DDR SDRAM - Main SODIMM */
/* DDR SDRAM - Main memory */
im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
msize = fixed_sdram();
msize = spd_sdram();
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
/*
......@@ -124,17 +74,148 @@ phys_size_t initdram(int board_type)
int checkboard(void)
{
puts("Board: esd VME8349\n");
#ifdef VME_CADDY2
puts("Board: esd VME-CADDY/2\n");
#else
puts("Board: esd VME-CPU/8349\n");
#endif
return 0;
}
#ifdef VME_CADDY2
int board_eth_init(bd_t *bis)
{
return pci_eth_init(bis);
}
#endif
#if defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
}
#endif
int misc_init_r()
{
immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
clrsetbits_be32(&im->lbus.lcrr, LBCR_LDIS, 0);
return 0;
}
/*
* Provide SPD values for spd_sdram(). Both boards (VME-CADDY/2
* and VME-CADDY/2) have different SDRAM configurations.
*/
#ifdef VME_CADDY2
#define SMALL_RAM 0xff
#define LARGE_RAM 0x00
#else
#define SMALL_RAM 0x00
#define LARGE_RAM 0xff
#endif
#define SPD_VAL(a, b) (((a) & SMALL_RAM) | ((b) & LARGE_RAM))
static spd_eeprom_t default_spd_eeprom = {
SPD_VAL(0x80, 0x80), /* 00 use 128 Bytes */
SPD_VAL(0x07, 0x07), /* 01 use 128 Bytes */
SPD_MEMTYPE_DDR2, /* 02 type is DDR2 */
SPD_VAL(0x0d, 0x0d), /* 03 rows: 13 */
SPD_VAL(0x09, 0x0a), /* 04 cols: 9 / 10 */
SPD_VAL(0x00, 0x00), /* 05 */
SPD_VAL(0x40, 0x40), /* 06 */
SPD_VAL(0x00, 0x00), /* 07 */
SPD_VAL(0x05, 0x05), /* 08 */
SPD_VAL(0x30, 0x30), /* 09 */
SPD_VAL(0x45, 0x45), /* 10 */
SPD_VAL(0x02, 0x02), /* 11 ecc used */
SPD_VAL(0x82, 0x82), /* 12 */
SPD_VAL(0x10, 0x10), /* 13 */
SPD_VAL(0x08, 0x08), /* 14 */
SPD_VAL(0x00, 0x00), /* 15 */
SPD_VAL(0x0c, 0x0c), /* 16 */
SPD_VAL(0x04, 0x08), /* 17 banks: 4 / 8 */
SPD_VAL(0x38, 0x38), /* 18 */
SPD_VAL(0x00, 0x00), /* 19 */
SPD_VAL(0x02, 0x02), /* 20 */
SPD_VAL(0x00, 0x00), /* 21 */
SPD_VAL(0x03, 0x03), /* 22 */
SPD_VAL(0x3d, 0x3d), /* 23 */
SPD_VAL(0x45, 0x45), /* 24 */
SPD_VAL(0x50, 0x50), /* 25 */
SPD_VAL(0x45, 0x45), /* 26 */
SPD_VAL(0x3c, 0x3c), /* 27 */
SPD_VAL(0x28, 0x28), /* 28 */
SPD_VAL(0x3c, 0x3c), /* 29 */
SPD_VAL(0x2d, 0x2d), /* 30 */
SPD_VAL(0x20, 0x80), /* 31 */
SPD_VAL(0x20, 0x20), /* 32 */
SPD_VAL(0x27, 0x27), /* 33 */
SPD_VAL(0x10, 0x10), /* 34 */
SPD_VAL(0x17, 0x17), /* 35 */
SPD_VAL(0x3c, 0x3c), /* 36 */
SPD_VAL(0x1e, 0x1e), /* 37 */
SPD_VAL(0x1e, 0x1e), /* 38 */
SPD_VAL(0x00, 0x00), /* 39 */
SPD_VAL(0x00, 0x06), /* 40 */
SPD_VAL(0x37, 0x37), /* 41 */
SPD_VAL(0x4b, 0x7f), /* 42 */
SPD_VAL(0x80, 0x80), /* 43 */
SPD_VAL(0x18, 0x18), /* 44 */
SPD_VAL(0x22, 0x22), /* 45 */
SPD_VAL(0x00, 0x00), /* 46 */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
SPD_VAL(0x10, 0x10), /* 62 */
SPD_VAL(0x7e, 0x1d), /* 63 */
{ 'e', 's', 'd', '-', 'g', 'm', 'b', 'h' },
SPD_VAL(0x00, 0x00), /* 72 */
#ifdef VME_CADDY2
{ "vme-caddy/2 ram " }
#else
{ "vme-cpu/2 ram " }
#endif
};
int vme8349_read_spd(uchar chip, uint addr, int alen, uchar *buffer, int len)
{
int old_bus = I2C_GET_BUS();
unsigned int l, sum;
int valid = 0;
I2C_SET_BUS(0);
if (i2c_read(chip, addr, alen, buffer, len) == 0)
if (memcmp(&buffer[64], &default_spd_eeprom.mid[0], 8) == 0) {
sum = 0;
for (l = 0; l < 63; l++)
sum = (sum + buffer[l]) & 0xff;
if (sum == buffer[63])
valid = 1;
else
printf("Invalid checksum in EEPROM %02x %02x\n",
sum, buffer[63]);
}
if (valid == 0) {
memcpy(buffer, (void *)&default_spd_eeprom, len);
sum = 0;
for (l = 0; l < 63; l++)
sum = (sum + buffer[l]) & 0xff;
if (sum != buffer[63])
printf("Invalid checksum in FLASH %02x %02x\n",
sum, buffer[63]);
buffer[63] = sum;
}
I2C_SET_BUS(old_bus);
return 0;
}
/*
* vme8349pin.h -- esd VME8349 MPC8349 I/O pin definition.
* Copyright (c) 2009 esd gmbh.
*
* Reinhard Arlt <reinhard.arlt@esd-electronics.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#ifndef __VME8349PIN_H__
#define __VME8349PIN_H__
#define GPIO2_V_SCON 0x80000000 /* In: from tsi148 1: is syscon */
#define GPIO2_VME_RESET_N 0x20000000 /* Out: to tsi148 */
#define GPIO2_TSI_PLL_RESET_N 0x08000000 /* Out: to tsi148 */
#define GPIO2_TSI_POWERUP_RESET_N 0x00800000 /* Out: to tsi148 */
#define GPIO2_L_RESET_EN_N 0x00100000 /* Out: 0:vme can assert cpu lrst*/
#endif /* of ifndef __VME8349PIN_H__ */
ifndef NAND_SPL
ifeq ($(CONFIG_MK_NAND), y)
TEXT_BASE = $(CONFIG_RAMBOOT_TEXT_BASE)
endif
endif
ifndef TEXT_BASE
TEXT_BASE = 0xFE000000
endif
......@@ -32,6 +32,8 @@
#include <mpc83xx.h>
#include <netdev.h>
#include <asm/io.h>
#include <ns16550.h>
#include <nand.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -45,6 +47,8 @@ int board_early_init_f(void)
return 0;
}
#ifndef CONFIG_NAND_SPL
static u8 read_board_info(void)
{
u8 val8;
......@@ -220,3 +224,41 @@ int board_eth_init(bd_t *bis)
cpu_eth_init(bis); /* Initialize TSECs first */
return pci_eth_init(bis);
}
#else /* CONFIG_NAND_SPL */
int checkboard(void)
{
puts("Board: Freescale MPC8315ERDB\n");
return 0;
}
void board_init_f(ulong bootflag)
{
board_early_init_f();
NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
puts("NAND boot... ");
init_timebase();
initdram(0);
relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
CONFIG_SYS_NAND_U_BOOT_RELOC);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
nand_boot();
}
void putc(char c)
{
if (gd->flags & GD_FLG_SILENT)
return;
if (c == '\n')
NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
}
#endif /* CONFIG_NAND_SPL */
......@@ -54,6 +54,7 @@ static void resume_from_sleep(void)
* This is useful for faster booting in configs where the RAM is unlikely
* to be changed, or for things like NAND booting where space is tight.
*/
#ifndef CONFIG_SYS_RAMBOOT
static long fixed_sdram(void)
{
volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
......@@ -68,7 +69,7 @@ static long fixed_sdram(void)
* Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
* or the DDR2 controller may fail to initialize correctly.
*/
udelay(50000);
__udelay(50000);
im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
......@@ -100,6 +101,12 @@ static long fixed_sdram(void)
return msize;
}
#else
static long fixed_sdram(void)
{
return CONFIG_SYS_DDR_SIZE * 1024 * 1024;
}
#endif /* CONFIG_SYS_RAMBOOT */
phys_size_t initdram(int board_type)
{
......
......@@ -69,6 +69,12 @@ void cpu_init_f (volatile immap_t * im)
#endif
#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
(ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
#endif
#ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */
(ACR_APARK << ACR_APARK_SHIFT) |
#endif
#ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */
(ACR_PARKM << ACR_PARKM_SHIFT) |
#endif
0;
__be32 acr_val =
......@@ -77,6 +83,12 @@ void cpu_init_f (volatile immap_t * im)
#endif
#ifdef CONFIG_SYS_ACR_RPTCNT /* Arbiter repeat count */
(CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT) |
#endif
#ifdef CONFIG_SYS_ACR_APARK /* Arbiter address parking mode */
(CONFIG_SYS_ACR_APARK << ACR_APARK_SHIFT) |
#endif
#ifdef CONFIG_SYS_ACR_PARKM /* Arbiter parking master */
(CONFIG_SYS_ACR_PARKM << ACR_PARKM_SHIFT) |
#endif
0;
__be32 spcr_mask =
......
......@@ -29,6 +29,7 @@
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <i2c.h>
#include <spd.h>
#include <asm/mmu.h>
......@@ -150,6 +151,14 @@ long int spd_sdram()
unsigned int ddrc_ecc_enable;
unsigned int pvr = get_pvr();
/*
* First disable the memory controller (could be enabled
* by the debugger)
*/
clrsetbits_be32(&ddr->sdram_cfg, SDRAM_CFG_MEM_EN, 0);
sync();
isync();
/* Read SPD parameters with I2C */
CONFIG_SYS_READ_SPD(SPD_EEPROM_ADDRESS, 0, 1, (uchar *) & spd, sizeof (spd));
#ifdef SPD_DEBUG
......
......@@ -15,6 +15,18 @@ Freescale MPC8315ERDB Board
4321 4321
(where the '*' indicates the position of the tab of the switch.)
To boot the image at the beginning of NAND flash, use these
DIP switch settings for S3 S4:
+------+ +------+
| * | | *** |
| *** | | * |
+------+ ON +------+ ON
4321 4321
(where the '*' indicates the position of the tab of the switch.)
When booting from NAND, use u-boot-nand.bin, not u-boot.bin.
2. Memory Map
The memory map looks like this:
......@@ -26,6 +38,9 @@ Freescale MPC8315ERDB Board
0xe060_0000 0xe060_7fff NAND FLASH (CS1) 32K
0xfe00_0000 0xfe7f_ffff NOR FLASH (CS0) 8M
When booting from NAND, NAND flash is CS0 and NOR flash
is CS1.
3. Definitions
3.1 Explanation of NEW definitions in:
......@@ -43,13 +58,15 @@ Freescale MPC8315ERDB Board
export CROSS_COMPILE=your-cross-compiler-prefix-
make distclean
make MPC8315ERDB_config
make MPC8315ERDB_config (or MPC8315ERDB_NAND_config for u-boot-nand.bin)
make all
5. Downloading and Flashing Images
5.1 Reflash U-boot Image using U-boot
NOR flash:
tftp 40000 u-boot.bin
protect off all
erase fe000000 fe1fffff
......@@ -60,6 +77,15 @@ Freescale MPC8315ERDB Board
You have to supply the correct byte count with 'xxxx'
from the TFTP result log.
NAND flash:
=>tftpboot $loadaddr <filename>
=>nand erase 0 0x80000
=>nand write $loadaddr 0 0x80000
...where 0x80000 is the filesize rounded up to
the next 0x20000 increment.
5.2 Downloading and Booting Linux Kernel
Ensure that all networking-related environment variables are set
......@@ -76,5 +102,4 @@ Freescale MPC8315ERDB Board
6 Notes
Booting from NAND flash is not yet supported.
The console baudrate for MPC8315ERDB is 115200bps.
......@@ -25,6 +25,11 @@
#ifndef __CONFIG_H
#define __CONFIG_H
#ifdef CONFIG_MK_NAND
#define CONFIG_NAND_U_BOOT 1
#define CONFIG_RAMBOOT_TEXT_BASE 0x00100000
#endif
/*
* High Level Configuration Options
*/
......@@ -51,20 +56,29 @@
HRCWL_SVCOD_DIV_2 |\
HRCWL_CSB_TO_CLKIN_2X1 |\
HRCWL_CORE_TO_CSB_3X1)
#define CONFIG_SYS_HRCW_HIGH (\
#define CONFIG_SYS_HRCW_HIGH_BASE (\
HRCWH_PCI_HOST |\
HRCWH_PCI1_ARBITER_ENABLE |\
HRCWH_CORE_ENABLE |\
HRCWH_FROM_0X00000100 |\
HRCWH_BOOTSEQ_DISABLE |\
HRCWH_SW_WATCHDOG_DISABLE |\
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_RL_EXT_LEGACY |\
HRCWH_TSEC1M_IN_RGMII |\
HRCWH_TSEC2M_IN_RGMII |\
HRCWH_BIG_ENDIAN |\
HRCWH_LALE_NORMAL)
#ifdef CONFIG_NAND_SPL
#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
HRCWH_FROM_0XFFF00100 |\
HRCWH_ROM_LOC_NAND_SP_8BIT |\
HRCWH_RL_EXT_NAND)
#else
#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE |\
HRCWH_FROM_0X00000100 |\
HRCWH_ROM_LOC_LOCAL_16BIT |\
HRCWH_RL_EXT_LEGACY)
#endif
/*
* System IO Config
*/
......@@ -79,6 +93,10 @@
*/
#define CONFIG_SYS_IMMR 0xE0000000
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
#endif
/*
* Arbiter Setup
*/
......@@ -161,12 +179,6 @@
*/
#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef CONFIG_SYS_RAMBOOT
#endif
#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
......@@ -200,10 +212,10 @@
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */
#define CONFIG_SYS_BR0_PRELIM ( CONFIG_SYS_FLASH_BASE /* Flash Base address */ \
#define CONFIG_SYS_NOR_BR_PRELIM (CONFIG_SYS_FLASH_BASE \
| (2 << BR_PS_SHIFT) /* 16 bit port size */ \
| BR_V ) /* valid */
#define CONFIG_SYS_OR0_PRELIM ( (~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
#define CONFIG_SYS_NOR_OR_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
| OR_UPM_XAM \
| OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \
......@@ -223,18 +235,31 @@
/*
* NAND Flash on the Local Bus
*/
#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
#ifdef CONFIG_NAND_SPL
#define CONFIG_SYS_NAND_BASE 0xFFF00000
#else
#define CONFIG_SYS_NAND_BASE 0xE0600000
#endif
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_MTD_NAND_VERIFY_WRITE 1
#define CONFIG_CMD_NAND 1
#define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BLOCK_SIZE 16384
#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
#define CONFIG_SYS_NAND_U_BOOT_OFFS 16384
#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_NAND_BASE \
#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V ) /* valid */
#define CONFIG_SYS_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \
#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFF8000 /* length 32K */ \
| OR_FCM_CSCT \
| OR_FCM_CST \
| OR_FCM_CHT \
......@@ -243,9 +268,31 @@
| OR_FCM_EHTR )
/* 0xFFFF8396 */
#ifdef CONFIG_NAND_U_BOOT
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NOR_BR_PRELIM
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NOR_OR_PRELIM
#else
#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NOR_BR_PRELIM
#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NOR_OR_PRELIM
#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM
#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM
#endif
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR1_PRELIM
#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR1_PRELIM
#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE && \
!defined(CONFIG_NAND_SPL)
#define CONFIG_SYS_RAMBOOT
#else
#undef CONFIG_SYS_RAMBOOT
#endif
/*
* Serial Port
*/
...