Commit 054197ba authored by Martha M Stan's avatar Martha M Stan Committed by Wolfgang Denk
Browse files

mpc512x: Streamlined fixed_sdram() init sequence.


Signed-off-by: default avatarMartha M Stan <mmarx@silicontkx.com>

Minor cleanup:

Re-ordered default_mddrc_config[] to have matching indices.

This allows to use the same index "N" for source and target fields;
before, we had code like this

	out_be32(&im->mddrc.ddr_time_config2, mddrc_config[3]);

which always looked like a copy & paste error because 2 != 3.

Also, use NULL when meaning a null pointer.
Signed-off-by: default avatarWolfgang Denk <wd@denx.de>
parent 5e498dfa
......@@ -101,7 +101,7 @@ int board_early_init_f(void)
phys_size_t initdram (int board_type)
{
return fixed_sdram();
return fixed_sdram(NULL, NULL, 0);
}
int misc_init_r(void)
......
......@@ -135,7 +135,7 @@ int board_early_init_f(void)
phys_size_t initdram(int board_type)
{
return get_ram_size(0, fixed_sdram());
return get_ram_size(0, fixed_sdram(NULL, NULL, 0));
}
int misc_init_r(void)
......
......@@ -137,7 +137,7 @@ phys_size_t initdram(int board_type)
{
u32 msize = 0;
msize = fixed_sdram();
msize = fixed_sdram(NULL, NULL, 0);
return msize;
}
......
......@@ -25,18 +25,70 @@
#include <asm/io.h>
#include <asm/mpc512x.h>
/*
* MDDRC Config Runtime Settings in order of the 4 MDDRC cfg registers
*/
u32 default_mddrc_config[4] = {
CONFIG_SYS_MDDRC_TIME_CFG0, /* time_config0 */
CONFIG_SYS_MDDRC_TIME_CFG1, /* time_config1 */
CONFIG_SYS_MDDRC_TIME_CFG2, /* time_config2 */
CONFIG_SYS_MDDRC_SYS_CFG, /* sys_config */
};
u32 default_init_seq[] = {
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_PCHG_ALL,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_RFSH,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_RFSH,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_MICRON_INIT_DEV_OP,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_EM2,
CONFIG_SYS_DDRCMD_NOP,
CONFIG_SYS_DDRCMD_PCHG_ALL,
CONFIG_SYS_DDRCMD_EM2,
CONFIG_SYS_DDRCMD_EM3,
CONFIG_SYS_DDRCMD_EN_DLL,
CONFIG_SYS_MICRON_INIT_DEV_OP,
CONFIG_SYS_DDRCMD_PCHG_ALL,
CONFIG_SYS_DDRCMD_RFSH,
CONFIG_SYS_MICRON_INIT_DEV_OP,
CONFIG_SYS_DDRCMD_OCD_DEFAULT,
CONFIG_SYS_DDRCMD_PCHG_ALL,
CONFIG_SYS_DDRCMD_NOP
};
/*
* fixed sdram init:
* The board doesn't use memory modules that have serial presence
* detect or similar mechanism for discovery of the DRAM settings
*/
long int fixed_sdram(void)
long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_seq, int seq_sz)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
u32 msize_log2 = __ilog2(msize);
u32 i;
/* take default settings and init sequence if necessary */
if (mddrc_config == NULL)
mddrc_config = default_mddrc_config;
if (dram_init_seq == NULL) {
dram_init_seq = default_init_seq;
seq_sz = sizeof(default_init_seq)/sizeof(u32);
}
/* Initialize IO Control */
out_be32(&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR);
......@@ -45,8 +97,8 @@ long int fixed_sdram(void)
out_be32(&im->sysconf.ddrlaw.ar, msize_log2 - 1);
sync_law(&im->sysconf.ddrlaw.ar);
/* Enable DDR */
out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_EN);
/* DDR Enable */
out_be32(&im->mddrc.ddr_sys_config, MDDRC_SYS_CFG_EN);
/* Initialize DDR Priority Manager */
out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
......@@ -73,41 +125,23 @@ long int fixed_sdram(void)
out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU);
out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL);
/* Initialize MDDRC */
out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG);
out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0);
out_be32(&im->mddrc.ddr_time_config1, CONFIG_SYS_MDDRC_TIME_CFG1);
out_be32(&im->mddrc.ddr_time_config2, CONFIG_SYS_MDDRC_TIME_CFG2);
/* Initialize DDR */
for (i = 0; i < 10; i++)
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
/*
* Initialize MDDRC
* put MDDRC in CMD mode and
* set the max time between refreshes to 0 during init process
*/
out_be32(&im->mddrc.ddr_sys_config, mddrc_config[3] | MDDRC_SYS_CFG_CMD_MASK);
out_be32(&im->mddrc.ddr_time_config0, mddrc_config[0] & MDDRC_REFRESH_ZERO_MASK);
out_be32(&im->mddrc.ddr_time_config1, mddrc_config[1]);
out_be32(&im->mddrc.ddr_time_config2, mddrc_config[2]);
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3);
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL);
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT);
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
/* Initialize DDR with either default or supplied init sequence */
for (i = 0; i < seq_sz; i++)
out_be32(&im->mddrc.ddr_command, dram_init_seq[i]);
/* Start MDDRC */
out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0_RUN);
out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_RUN);
out_be32(&im->mddrc.ddr_time_config0, mddrc_config[0]);
out_be32(&im->mddrc.ddr_sys_config, mddrc_config[3]);
return msize;
}
......@@ -341,6 +341,10 @@ typedef struct ddr512x {
u32 res2[0x3AD];
} ddr512x_t;
/* MDDRC SYS CFG and Timing CFG0 Registers */
#define MDDRC_SYS_CFG_EN 0xF0000000
#define MDDRC_SYS_CFG_CMD_MASK 0x10000000
#define MDDRC_REFRESH_ZERO_MASK 0x0000FFFF
/*
* DMA/Messaging Unit
......
......@@ -50,7 +50,7 @@ static inline void sync_law(volatile void *addr)
/*
* Prototypes
*/
extern long int fixed_sdram(void);
extern long int fixed_sdram(u32 *mddrc_config, u32 *dram_init_seq, int seq_sz);
extern int mpc5121_diu_init(void);
extern void ide_set_reset(int idereset);
......
......@@ -126,7 +126,7 @@
#define CONFIG_SYS_MDDRC_SYS_CFG ( (1 << 31) | /* RST_B */ \
(1 << 30) | /* CKE */ \
(1 << 29) | /* CLK_ON */ \
(1 << 28) | /* CMD_MODE */ \
(0 << 28) | /* CMD_MODE */ \
(4 << 25) | /* DRAM_ROW_SELECT */ \
(3 << 21) | /* DRAM_BANK_SELECT */ \
(0 << 18) | /* SELF_REF_EN */ \
......@@ -143,16 +143,12 @@
(0 << 0) /* FIFO_UV_EN */ \
)
#define CONFIG_SYS_MDDRC_SYS_CFG_RUN (CONFIG_SYS_MDDRC_SYS_CFG & ~(1 << 28))
#define CONFIG_SYS_MDDRC_TIME_CFG0 0x030C3D2E
#define CONFIG_SYS_MDDRC_TIME_CFG1 0x55D81189
#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34790863
#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000
#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E
#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x030C3D2E
#define CONFIG_SYS_MICRON_NOP 0x01380000
#define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400
#define CONFIG_SYS_DDRCMD_NOP 0x01380000
#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
#define CONFIG_SYS_MICRON_EMR ( (1 << 24) | /* CMD_REQ */ \
(0 << 22) | /* DRAM_CS */ \
(0 << 21) | /* DRAM_RAS */ \
......@@ -172,7 +168,7 @@
)
#define CONFIG_SYS_MICRON_EMR2 0x01020000
#define CONFIG_SYS_MICRON_EMR3 0x01030000
#define CONFIG_SYS_MICRON_RFSH 0x01080000
#define CONFIG_SYS_DDRCMD_RFSH 0x01080000
#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
#define CONFIG_SYS_MICRON_EMR_OCD ( (1 << 24) | /* CMD_REQ */ \
(0 << 22) | /* DRAM_CS */ \
......@@ -196,10 +192,10 @@
* Backward compatible definitions,
* so we do not have to change cpu/mpc512x/fixed_sdram.c
*/
#define CONFIG_SYS_MICRON_EM2 (CONFIG_SYS_MICRON_EMR2)
#define CONFIG_SYS_MICRON_EM3 (CONFIG_SYS_MICRON_EMR3)
#define CONFIG_SYS_MICRON_EN_DLL (CONFIG_SYS_MICRON_EMR)
#define CONFIG_SYS_MICRON_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD)
#define CONFIG_SYS_DDRCMD_EM2 (CONFIG_SYS_MICRON_EMR2)
#define CONFIG_SYS_DDRCMD_EM3 (CONFIG_SYS_MICRON_EMR3)
#define CONFIG_SYS_DDRCMD_EN_DLL (CONFIG_SYS_MICRON_EMR)
#define CONFIG_SYS_DDRCMD_OCD_DEFAULT (CONFIG_SYS_MICRON_EMR_OCD)
/* DDR Priority Manager Configuration */
#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
......
......@@ -111,22 +111,19 @@
* [09:05] DRAM tRP:
* [04:00] DRAM tRPA
*/
#define CONFIG_SYS_MDDRC_SYS_CFG 0xFA804A00
#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xEA804A00
#define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A00
#define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E
#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168
#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864
#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000
#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E
#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x06183D2E
#define CONFIG_SYS_MICRON_NOP 0x01380000
#define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400
#define CONFIG_SYS_MICRON_EM2 0x01020000
#define CONFIG_SYS_MICRON_EM3 0x01030000
#define CONFIG_SYS_MICRON_EN_DLL 0x01010000
#define CONFIG_SYS_MICRON_RFSH 0x01080000
#define CONFIG_SYS_DDRCMD_NOP 0x01380000
#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
#define CONFIG_SYS_DDRCMD_EM2 0x01020000
#define CONFIG_SYS_DDRCMD_EM3 0x01030000
#define CONFIG_SYS_DDRCMD_EN_DLL 0x01010000
#define CONFIG_SYS_DDRCMD_RFSH 0x01080000
#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
#define CONFIG_SYS_MICRON_OCD_DEFAULT 0x01010780
#define CONFIG_SYS_DDRCMD_OCD_DEFAULT 0x01010780
/* DDR Priority Manager Configuration */
#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
......
......@@ -131,28 +131,24 @@
* [04:00] DRAM tRPA
*/
#ifdef CONFIG_MPC5121ADS_REV2
#define CONFIG_SYS_MDDRC_SYS_CFG 0xF8604A00
#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xE8604A00
#define CONFIG_SYS_MDDRC_SYS_CFG 0xE8604A00
#define CONFIG_SYS_MDDRC_TIME_CFG1 0x54EC1168
#define CONFIG_SYS_MDDRC_TIME_CFG2 0x35210864
#else
#define CONFIG_SYS_MDDRC_SYS_CFG 0xFA804A00
#define CONFIG_SYS_MDDRC_SYS_CFG_RUN 0xEA804A00
#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168
#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864
#define CONFIG_SYS_MDDRC_SYS_CFG 0xEA804A00
#define CONFIG_SYS_MDDRC_TIME_CFG1 0x68EC1168
#define CONFIG_SYS_MDDRC_TIME_CFG2 0x34310864
#endif
#define CONFIG_SYS_MDDRC_SYS_CFG_EN 0xF0000000
#define CONFIG_SYS_MDDRC_TIME_CFG0 0x00003D2E
#define CONFIG_SYS_MDDRC_TIME_CFG0_RUN 0x06183D2E
#define CONFIG_SYS_MICRON_NOP 0x01380000
#define CONFIG_SYS_MICRON_PCHG_ALL 0x01100400
#define CONFIG_SYS_MICRON_EM2 0x01020000
#define CONFIG_SYS_MICRON_EM3 0x01030000
#define CONFIG_SYS_MICRON_EN_DLL 0x01010000
#define CONFIG_SYS_MICRON_RFSH 0x01080000
#define CONFIG_SYS_MDDRC_TIME_CFG0 0x06183D2E
#define CONFIG_SYS_DDRCMD_NOP 0x01380000
#define CONFIG_SYS_DDRCMD_PCHG_ALL 0x01100400
#define CONFIG_SYS_DDRCMD_EM2 0x01020000
#define CONFIG_SYS_DDRCMD_EM3 0x01030000
#define CONFIG_SYS_DDRCMD_EN_DLL 0x01010000
#define CONFIG_SYS_DDRCMD_RFSH 0x01080000
#define CONFIG_SYS_MICRON_INIT_DEV_OP 0x01000432
#define CONFIG_SYS_MICRON_OCD_DEFAULT 0x01010780
#define CONFIG_SYS_DDRCMD_OCD_DEFAULT 0x01010780
/* DDR Priority Manager Configuration */
#define CONFIG_SYS_MDDRCGRP_PM_CFG1 0x00077777
......
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