Commit 080408fd authored by Wolfgang Grandegger's avatar Wolfgang Grandegger Committed by Andy Fleming
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MPC85xx: TQM8548: use cache for AG and BE variants



This patch makes accesses to the system memory cachable by removing the
caching-inhibited and guarded flags from the relevant TLB entries for
the TQM8548_BE and TQM8548_AG modules. FYI, the Freescale MPC85* boards
are configured similarly.

This results in a big averall performace improvement. TFTP downloads,
NAND Flash accesses, kernel boots, etc. are much faster.
Signed-off-by: default avatarWolfgang Grandegger <wg@grandegger.com>
parent dc5f55d6
......@@ -128,12 +128,12 @@ struct fsl_e_tlb_entry tlb_table[] = {
* Without SPD EEPROM configured DDR, this must be setup manually.
*/
SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 7, BOOKE_PAGESZ_1G, 1),
SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
MAS3_SX | MAS3_SW | MAS3_SR, 0,
0, 8, BOOKE_PAGESZ_1G, 1),
#else
/*
......
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