Commit 082acfd4 authored by wdenk's avatar wdenk
Browse files

Coding Style cleanup

parent 652a10c0
......@@ -226,8 +226,8 @@ Denis Peter <d.peter@mpl.ch>
PIP405 PPC4xx
Daniel Poirot <dan.poirot@windriver.com>
sbc8240 MPC8240
sbc405 PPC405GP
sbc8240 MPC8240
sbc405 PPC405GP
Stefan Roese <stefan.roese@esd-electronics.com>
......@@ -387,7 +387,7 @@ Rishi Bhattacharya <rishi@ti.com>
omap5912osk ARM926EJS
Richard Woodruff <r-woodruff2@ti.com>
omap2420h4 ARM1136EJS
David Mller <d.mueller@elsoft.ch>
......
......@@ -38,7 +38,7 @@ make all
To support the Platform better,I added LCD panel(NL6448BC20-08) function.
For the convenience of debug, CONFIG_PERBOOT was supported. So you just
perss ENTER if you want to get a serial console in boot downcounting.
Then you can switch to LCD and serial console freely just typing
Then you can switch to LCD and serial console freely just typing
'run lcd' or 'run ser'. They are only vaild when CONFIG_LCD was enabled.
To get a LCD support u-boot,you can do the following:
......@@ -93,18 +93,18 @@ In the beginning, you could just need very simple defult environment variable se
like[include/configs/RPXlite.h] :
#define CONFIG_BOOTCOMMAND \
"bootp; " \
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
"bootm"
"bootp; " \
"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
"bootm"
This is enough for kernel NFS test. But as debug process goes on, you would expect
This is enough for kernel NFS test. But as debug process goes on, you would expect
to save some time on environment variable setting and u-boot/kernel updating.
So the default environment variable setting would become more complicated. Just like
the one I did in include/configs/RPXlite_DW.h.
Two u-boot commands, ku and uu, should be careful to use. They were designed to update
kernel and u-boot image file respectively. You must tftp your image to default address
kernel and u-boot image file respectively. You must tftp your image to default address
'100000' and then use them correctly. Yeah, you can create your own command to do this
job. :-) The example u-boot image updating process could be :
......
......@@ -20,7 +20,6 @@ TEXT_BASE = 0x80e80000
# Used with full SRAM boot.
# This is either with a GP system or a signed boot image.
# easiest, and safest way to go if you can.
# Comment out //CONFIG_PARTIAL_SRAM for this one.
# Comment out CONFIG_PARTIAL_SRAM for this one.
#
#TEXT_BASE = 0x40280000
......@@ -284,10 +284,10 @@ void gpmc_init(void)
__raw_writel(0x0, GPMC_CONFIG7_0); /* disable current map */
sdelay(1000);
__raw_writel(H4_24XX_GPMC_CONFIG1_0|mux|mtype|mwidth, GPMC_CONFIG1_0);
//__raw_writel(H4_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0);
/* __raw_writel(H4_24XX_GPMC_CONFIG2_0, GPMC_CONFIG2_0); */
__raw_writel(H4_24XX_GPMC_CONFIG3_0, GPMC_CONFIG3_0);
__raw_writel(H4_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_0);
//__raw_writel(H4_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0);
/* __raw_writel(H4_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_0); */
__raw_writel(H4_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_0);/* enable new mapping */
sdelay(2000);
......@@ -303,4 +303,3 @@ void gpmc_init(void)
__raw_writel(H4_24XX_GPMC_CONFIG7_1, GPMC_CONFIG7_1); /* enable mapping */
sdelay(2000);
}
......@@ -333,11 +333,11 @@ void muxSetupI2C1(void)
/* I2C1 Clock pin configuration, PIN = M19 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SCL;
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* I2C1 Data pin configuration, PIN = L15 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_I2C1_SDA;
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* Pull-up required on data line */
/* external pull-up already present. */
......@@ -379,91 +379,91 @@ void muxSetupLCD(void)
/* LCD_D0 pin configuration, PIN = Y7 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D0;
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_D1 pin configuration, PIN = P10 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D1;
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_D2 pin configuration, PIN = V8 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D2;
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_D3 pin configuration, PIN = Y8 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D3;
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_D4 pin configuration, PIN = W8 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D4;
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_D5 pin configuration, PIN = R10 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D5;
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_D6 pin configuration, PIN = Y9 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D6;
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_D7 pin configuration, PIN = V9 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D7;
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_D8 pin configuration, PIN = W9 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D8;
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_D9 pin configuration, PIN = P11 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D9;
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_D10 pin configuration, PIN = V10 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D10;
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_D11 pin configuration, PIN = Y10 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D11;
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_D12 pin configuration, PIN = W10 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D12;
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_D13 pin configuration, PIN = R11 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D13;
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_D14 pin configuration, PIN = V11 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D14;
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_D15 pin configuration, PIN = W11 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D15;
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_D16 pin configuration, PIN = P12 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D16;
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_D17 pin configuration, PIN = R12 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_D17;
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_PCLK pin configuration, PIN = W6 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_PCLK;
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_VSYNC pin configuration, PIN = V7 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_VSYNC;
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_HSYNC pin configuration, PIN = Y6 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_HSYNC;
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* LCD_ACBIAS pin configuration, PIN = W7 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_DSS_ACBIAS;
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
}
/****************************************
......@@ -477,63 +477,63 @@ void muxSetupCamera(void)
/* CAMERA_RSTZ pin configuration, PIN = Y16 */
/* CAM_RST is connected through the I2C IO expander.*/
/* MuxConfigReg = (volatile unsigned char *), CONTROL_PADCONF_SYS_NRESWARM*/
/* *MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled */
/* *MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* CAMERA_XCLK pin configuration, PIN = U3 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_XCLK;
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* CAMERA_LCLK pin configuration, PIN = V5 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_LCLK;
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* CAMERA_VSYNC pin configuration, PIN = U2 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_VS,
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* CAMERA_HSYNC pin configuration, PIN = T3 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_HS,
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* CAMERA_DAT0 pin configuration, PIN = T4 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D0,
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* CAMERA_DAT1 pin configuration, PIN = V2 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D1,
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* CAMERA_DAT2 pin configuration, PIN = V3 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D2,
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* CAMERA_DAT3 pin configuration, PIN = U4 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D3,
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* CAMERA_DAT4 pin configuration, PIN = W2 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D4,
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* CAMERA_DAT5 pin configuration, PIN = V4 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D5,
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* CAMERA_DAT6 pin configuration, PIN = W3 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D6,
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* CAMERA_DAT7 pin configuration, PIN = Y2 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D7,
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* CAMERA_DAT8 pin configuration, PIN = Y4 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D8,
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* CAMERA_DAT9 pin configuration, PIN = V6 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_CAM_D9,
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
}
/****************************************
......@@ -546,70 +546,70 @@ void muxSetupMMCSD(void)
/* SDMMC_CLKI pin configuration, PIN = H15 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKI,
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* SDMMC_CLKO pin configuration, PIN = G19 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CLKO,
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* SDMMC_CMD pin configuration, PIN = H18 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD,
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
// External pull-ups are present.
// *MuxConfigReg |= 0x18 ; // PullUDEnable=Enabled, PullTypeSel=PU
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* External pull-ups are present. */
/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
/* SDMMC_DAT0 pin configuration, PIN = F20 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT0,
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
// External pull-ups are present.
// *MuxConfigReg |= 0x18 ; // PullUDEnable=Enabled, PullTypeSel=PU
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* External pull-ups are present. */
/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
/* SDMMC_DAT1 pin configuration, PIN = H14 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT1,
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
// External pull-ups are present.
// *MuxConfigReg |= 0x18 ; // PullUDEnable=Enabled, PullTypeSel=PU
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* External pull-ups are present. */
/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
/* SDMMC_DAT2 pin configuration, PIN = E19 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT2,
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
// External pull-ups are present.
// *MuxConfigReg |= 0x18 ; // PullUDEnable=Enabled, PullTypeSel=PU
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* External pull-ups are present. */
/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
/* SDMMC_DAT3 pin configuration, PIN = D19 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT3,
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
// External pull-ups are present.
// *MuxConfigReg |= 0x18 ; // PullUDEnable=Enabled, PullTypeSel=PU
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* External pull-ups are present. */
/* *MuxConfigReg |= 0x18 ; #/ PullUDEnable=Enabled, PullTypeSel=PU */
/* SDMMC_DDIR0 pin configuration, PIN = F19 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR0,
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* SDMMC_DDIR1 pin configuration, PIN = E20 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR1,
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* SDMMC_DDIR2 pin configuration, PIN = F18 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR2,
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* SDMMC_DDIR3 pin configuration, PIN = E18 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_DAT_DIR3,
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* SDMMC_CDIR pin configuration, PIN = G18 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MMC_CMD_DIR,
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* MMC_CD pin configuration, PIN = B3 ---2420IP ONLY---*/
/* MMC_CD for 2422IP=K1 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A14,
*MuxConfigReg = 0x03 ; // Mode = 3, PUPD=Disabled
*MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
/* MMC_WP pin configuration, PIN = B4 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SDRC_A13,
*MuxConfigReg = 0x03 ; // Mode = 3, PUPD=Disabled
*MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
}
/******************************************
......@@ -622,23 +622,23 @@ void muxSetupTouchScreen(void)
/* SPI1_CLK pin configuration, PIN = U18 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_CLK,
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* SPI1_MOSI pin configuration, PIN = V20 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SIMO,
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* SPI1_MISO pin configuration, PIN = T18 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_SOMI,
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* SPI1_nCS0 pin configuration, PIN = U19 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_SPI1_NCS0,
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
/* PEN_IRQ pin configuration, PIN = P20 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_MCBSP1_FSR,
*MuxConfigReg = 0x03 ; // Mode = 3, PUPD=Disabled
*MuxConfigReg = 0x03 ; /* Mode = 3, PUPD=Disabled */
}
/****************************************
......@@ -651,7 +651,7 @@ void muxSetupHDQ(void)
/* HDQ_SIO pin configuration, PIN = N18 */
MuxConfigReg = (volatile unsigned char *)CONTROL_PADCONF_HDQ_SIO,
*MuxConfigReg = 0x00 ; // Mode = 0, PUPD=Disabled
*MuxConfigReg = 0x00 ; /* Mode = 0, PUPD=Disabled */
}
/***************************************************************
......@@ -830,5 +830,3 @@ void update_mux(u32 btype,u32 mtype)
}
}
}
......@@ -15,7 +15,7 @@
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
......@@ -41,109 +41,109 @@ _TEXT_BASE:
*************************************************************************/
.global cpy_clk_code
cpy_clk_code:
/* Copy DPLL code into SRAM */
adr r0, go_to_speed /* get addr of clock setting code */
mov r2, #384 /* r2 size to copy (div by 32 bytes) */
mov r1, r1 /* r1 <- dest address (passed in) */
add r2, r2, r0 /* r2 <- source end address */
/* Copy DPLL code into SRAM */
adr r0, go_to_speed /* get addr of clock setting code */
mov r2, #384 /* r2 size to copy (div by 32 bytes) */
mov r1, r1 /* r1 <- dest address (passed in) */
add r2, r2, r0 /* r2 <- source end address */
next2:
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
bne next2
mov pc, lr /* back to caller */
ldmia r0!, {r3-r10} /* copy from source address [r0] */
stmia r1!, {r3-r10} /* copy to target address [r1] */
cmp r0, r2 /* until source end address [r2] */
bne next2
mov pc, lr /* back to caller */
/* ****************************************************************************
/* ****************************************************************************
* go_to_speed: -Moves to bypass, -Commits clock dividers, -puts dpll at speed
* -executed from SRAM.
* -executed from SRAM.
* R0 = PRCM_CLKCFG_CTRL - addr of valid reg
* R1 = CM_CLKEN_PLL - addr dpll ctlr reg
* R2 = dpll value
* R3 = CM_IDLEST_CKGEN - addr dpll lock wait
******************************************************************************/
******************************************************************************/
.global go_to_speed
go_to_speed:
sub sp, sp, #0x4 /* get some stack space */
str r4, [sp] /* save r4's value */
/* move into fast relock bypass */
ldr r8, pll_ctl_add
mov r4, #0x2
str r4, [r8]
ldr r4, pll_stat
sub sp, sp, #0x4 /* get some stack space */
str r4, [sp] /* save r4's value */
/* move into fast relock bypass */
ldr r8, pll_ctl_add
mov r4, #0x2
str r4, [r8]
ldr r4, pll_stat
block:
ldr r8, [r4] /* wait for bypass to take effect */
and r8, r8, #0x3
cmp r8, #0x1
bne block
ldr r8, [r4] /* wait for bypass to take effect */
and r8, r8, #0x3
cmp r8, #0x1
bne block
/* set new dpll dividers _after_ in bypass */
ldr r4, pll_div_add
ldr r8, pll_div_val
str r8, [r4]
/* now prepare GPMC (flash) for new dpll speed */
ldr r4, pll_div_add
ldr r8, pll_div_val
str r8, [r4]
/* now prepare GPMC (flash) for new dpll speed */
/* flash needs to be stable when we jump back to it */
ldr r4, cfg3_0_addr
ldr r8, cfg3_0_val
str r8, [r4]
ldr r4, cfg4_0_addr
ldr r8, cfg4_0_val
str r8, [r4]
ldr r4, cfg1_0_addr
ldr r8, [r4]
orr r8, r8, #0x3 /* up gpmc divider */
str r8, [r4]
/* setup to 2x loop though code. The first loop pre-loads the
* icache, the 2nd commits the prcm config, and locks the dpll
*/
mov r4, #0x1000 /* spin spin spin */
mov r8, #0x4 /* first pass condition & set registers */
cmp r8, #0x4
ldr r4, cfg3_0_addr
ldr r8, cfg3_0_val
str r8, [r4]
ldr r4, cfg4_0_addr
ldr r8, cfg4_0_val
str r8, [r4]
ldr r4, cfg1_0_addr
ldr r8, [r4]
orr r8, r8, #0x3 /* up gpmc divider */
str r8, [r4]
/* setup to 2x loop though code. The first loop pre-loads the
* icache, the 2nd commits the prcm config, and locks the dpll
*/
mov r4, #0x1000 /* spin spin spin */
mov r8, #0x4 /* first pass condition & set registers */
cmp r8, #0x4
2:
ldrne r8, [r3] /* DPLL lock check */
and r8, r8, #0x7
cmp r8, #0x2
beq 4f
ldrne r8, [r3] /* DPLL lock check */
and r8, r8, #0x7
cmp r8, #0x2
beq 4f
3:
subeq r8, r8, #0x1
streq r8, [r0] /* commit dividers (2nd time) */
nop
subeq r8, r8, #0x1
streq r8, [r0] /* commit dividers (2nd time) */
nop
lloop1:
sub r4, r4, #0x1 /* Loop currently necessary else bad jumps */
nop
cmp r4, #0x0
bne lloop1
mov r4, #0x40000
cmp r8, #0x1
nop
streq r2, [r1] /* lock dpll (2nd time) */
nop
sub r4, r4, #0x1 /* Loop currently necessary else bad jumps */
nop
cmp r4, #0x0
bne lloop1
mov r4, #0x40000
cmp r8, #0x1
nop
streq r2, [r1] /* lock dpll (2nd time) */
nop
lloop2:
sub r4, r4, #0x1 /* loop currently necessary else bad jumps */
nop
cmp r4, #0x0
bne lloop2
mov r4, #0x40000
cmp r8, #0x1
nop
ldreq r8, [r3] /* get lock condition for dpll */
cmp r8, #0x4 /* first time though? */
bne 2b
moveq r8, #0x2 /* set to dpll check condition. */
beq 3b /* if condition not true branch */
4:
ldr r4, [sp]
add sp, sp, #0x4 /* return stack space */