Commit 0a16ea59 authored by Albert ARIBAUD's avatar Albert ARIBAUD Committed by Prafulla Wadaskar

mv88e61xx: refactor PHY and SWITCH level-code

Signed-off-by: default avatarAlbert ARIBAUD <albert.u.boot@aribaud.net>
parent 136846d7
This diff is collapsed.
......@@ -28,35 +28,50 @@
#include <miiphy.h>
#define MV88E61XX_CPU_PORT 0x5
#define MV88E61XX_MAX_PORTS_NUM 0x6
#define MV88E61XX_PHY_TIMEOUT 100000
#define MV88E61XX_PRT_STS_REG 0x1
/* port dev-addr (= port + 0x10) */
#define MV88E61XX_PRT_OFST 0x10
/* port registers */
#define MV88E61XX_PCS_CTRL_REG 0x1
#define MV88E61XX_PRT_CTRL_REG 0x4
#define MV88E61XX_PRT_VMAP_REG 0x6
#define MV88E61XX_PRT_VID_REG 0x7
#define MV88E61XX_RGMII_TIMECTRL_REG 0x1A
#define MV88E61XX_PRT_OFST 0x10
/* global registers dev-addr */
#define MV88E61XX_GLBREG_DEVADR 0x1B
/* global registers */
#define MV88E61XX_SGSR 0x00
#define MV88E61XX_SGCR 0x04
/* global 2 registers dev-addr */
#define MV88E61XX_GLB2REG_DEVADR 0x1C
/* global 2 registers */
#define MV88E61XX_PHY_CMD 0x18
#define MV88E61XX_PHY_DATA 0x19
#define MV88E61XX_RGMII_TIMECTRL_REG 0x1A
#define MV88E61XX_GLB2REG_DEVADR 0x1C
/* global 2 phy commands */
#define MV88E61XX_PHY_WRITE_CMD 0x9400
#define MV88E61XX_PHY_READ_CMD 0x9800
#define MV88E61XX_BUSY_OFST 15
#define MV88E61XX_MODE_OFST 12
#define MV88E61XX_OP_OFST 10
#define MV88E61XX_OP_OFST 10
#define MV88E61XX_ADDR_OFST 5
#ifdef CONFIG_MV88E61XX_MULTICHIP_ADRMODE
static int mv88e61xx_busychk_multic(char *name, u32 devaddr);
static void mv88e61xx_wr_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 data);
static void mv88e61xx_rd_phy(char *name, u32 phy_adr, u32 reg_ofs, u16 * data);
#define WR_PHY mv88e61xx_wr_phy
#define RD_PHY mv88e61xx_rd_phy
static void mv88e61xx_switch_write(char *name, u32 phy_adr,
u32 reg_ofs, u16 data);
static void mv88e61xx_switch_read(char *name, u32 phy_adr,
u32 reg_ofs, u16 *data);
#define wr_switch_reg mv88e61xx_switch_write
#define rd_switch_reg mv88e61xx_switch_read
#else
#define WR_PHY miiphy_write
#define RD_PHY miiphy_read
/* switch appears a s simple PHY and can thus use miiphy */
#define wr_switch_reg miiphy_write
#define rd_switch_reg miiphy_read
#endif /* CONFIG_MV88E61XX_MULTICHIP_ADRMODE */
#endif /* _MV88E61XX_H */
......@@ -163,10 +163,9 @@ static inline int pci_eth_init(bd_t *bis)
* the stuct and enums here are used to specify switch configuration params
*/
#if defined(CONFIG_MV88E61XX_SWITCH)
enum mv88e61xx_cfg_vlan {
MV88E61XX_VLANCFG_DEFAULT,
MV88E61XX_VLANCFG_ROUTER
};
/* constants for any 88E61xx switch */
#define MV88E61XX_MAX_PORTS_NUM 6
enum mv88e61xx_cfg_mdip {
MV88E61XX_MDIP_NOCHANGE,
......@@ -192,7 +191,7 @@ enum mv88e61xx_cfg_prtstt {
struct mv88e61xx_config {
char *name;
enum mv88e61xx_cfg_vlan vlancfg;
u8 vlancfg[MV88E61XX_MAX_PORTS_NUM];
enum mv88e61xx_cfg_rgmiid rgmii_delay;
enum mv88e61xx_cfg_prtstt portstate;
enum mv88e61xx_cfg_ledinit led_init;
......@@ -201,6 +200,18 @@ struct mv88e61xx_config {
u8 cpuport;
};
/*
* Common mappings for Internal VLANs
* These mappings consider that all ports are useable; the driver
* will mask inexistent/unused ports.
*/
/* Switch mode : routes any port to any port */
#define MV88E61XX_VLANCFG_SWITCH { 0x3F, 0x3F, 0x3F, 0x3F, 0x3F, 0x3F }
/* Router mode: routes only CPU port 5 to/from non-CPU ports 0-4 */
#define MV88E61XX_VLANCFG_ROUTER { 0x20, 0x20, 0x20, 0x20, 0x20, 0x1F }
int mv88e61xx_switch_initialize(struct mv88e61xx_config *swconfig);
#endif /* CONFIG_MV88E61XX_SWITCH */
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment