Commit 0aee53ba authored by Chander Kashyap's avatar Chander Kashyap Committed by Albert ARIBAUD
Browse files

EXYNOS: Add SMDK5250 board support



SMDK5250 board is based on Samsungs EXYNOS5250 SoC.
Signed-off-by: default avatarChander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: default avatarMinkyu Kang <mk7.kang@samsung.com>
parent 37bb6d89
......@@ -717,6 +717,7 @@ Chander Kashyap <k.chander@samsung.com>
origen ARM ARMV7 (EXYNOS4210 SoC)
SMDKV310 ARM ARMV7 (EXYNOS4210 SoC)
SMDK5250 ARM ARMV7 (EXYNOS5250 SoC)
Heungjun Kim <riverful.kim@samsung.com>
......
#
# Copyright (C) 2012 Samsung Electronics
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
SOBJS := lowlevel_init.o
COBJS := clock_init.o
COBJS += dmc_init.o
COBJS += tzpc_init.o
COBJS += smdk5250.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS) $(SOBJS))
ALL := $(obj).depend $(LIB)
all: $(ALL)
$(LIB): $(OBJS)
$(call cmd_link_o_target, $(OBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
/*
* Clock setup for SMDK5250 board based on EXYNOS5
*
* Copyright (C) 2012 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <version.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
#include <asm/arch/cpu.h>
#include <asm/arch/gpio.h>
#include "setup.h"
void system_clock_init()
{
struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
/*
* MUX_APLL_SEL[0]: FINPLL = 0
* MUX_CPU_SEL[6]: MOUTAPLL = 0
* MUX_HPM_SEL[20]: MOUTAPLL = 0
*/
writel(0x0, &clk->src_cpu);
/* MUX_MPLL_SEL[8]: FINPLL = 0 */
writel(0x0, &clk->src_core1);
/*
* VPLLSRC_SEL[0]: FINPLL = 0
* MUX_{CPLL[8]}|{EPLL[12]}|{VPLL[16]}_SEL: FINPLL = 0
*/
writel(0x0, &clk->src_top2);
/* MUX_BPLL_SEL[0]: FINPLL = 0 */
writel(0x0, &clk->src_cdrex);
/* MUX_ACLK_* Clock Selection */
writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
/* MUX_ACLK_* Clock Selection */
writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
/* MUX_ACLK_* Clock Selection */
writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
/* MUX_PWI_SEL[19:16]: SCLKMPLL = 6 */
writel(CLK_SRC_CORE0_VAL, &clk->src_core0);
/* MUX_ATCLK_LEX[0]: ACLK_200 = 0 */
writel(CLK_SRC_LEX_VAL, &clk->src_lex);
/* UART [0-5]: SCLKMPLL = 6 */
writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
/* Set Clock Ratios */
writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
/* Set COPY and HPM Ratio */
writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
/* CORED_RATIO, COREP_RATIO */
writel(CLK_DIV_CORE0_VAL, &clk->div_core0);
/* PWI_RATIO[11:8], DVSEM_RATIO[22:16], DPM_RATIO[24:20] */
writel(CLK_DIV_CORE1_VAL, &clk->div_core1);
/* ACLK_*_RATIO */
writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
/* ACLK_*_RATIO */
writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
/* CDREX Ratio */
writel(CLK_DIV_CDREX_INIT_VAL, &clk->div_cdrex);
/* MCLK_EFPHY_RATIO[3:0] */
writel(CLK_DIV_CDREX2_VAL, &clk->div_cdrex2);
/* {PCLK[4:6]|ATCLK[10:8]}_RATIO */
writel(CLK_DIV_LEX_VAL, &clk->div_lex);
/* PCLK_R0X_RATIO[3:0] */
writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
/* PCLK_R1X_RATIO[3:0] */
writel(CLK_DIV_R1X_VAL, &clk->div_r1x);
/* SATA[24]: SCLKMPLL=0, MMC[0-4]: SCLKMPLL = 6 */
writel(CLK_SRC_FSYS_VAL, &clk->src_fsys);
/* UART[0-4] */
writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
/* PWM_RATIO[3:0] */
writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
/* SATA_RATIO, USB_DRD_RATIO */
writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
/* MMC[0-1] */
writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
/* MMC[2-3] */
writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
/* MMC[4] */
writel(CLK_DIV_FSYS3_VAL, &clk->div_fsys3);
/* ACLK|PLCK_ACP_RATIO */
writel(CLK_DIV_ACP_VAL, &clk->div_acp);
/* ISPDIV0_RATIO, ISPDIV1_RATIO */
writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
/* MCUISPDIV0_RATIO, MCUISPDIV1_RATIO */
writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
/* MPWMDIV_RATIO */
writel(CLK_DIV_ISP2_VAL, &clk->div_isp2);
/* PLL locktime */
writel(APLL_LOCK_VAL, &clk->apll_lock);
writel(MPLL_LOCK_VAL, &clk->mpll_lock);
writel(BPLL_LOCK_VAL, &clk->bpll_lock);
writel(CPLL_LOCK_VAL, &clk->cpll_lock);
writel(EPLL_LOCK_VAL, &clk->epll_lock);
writel(VPLL_LOCK_VAL, &clk->vpll_lock);
sdelay(0x10000);
/* Set APLL */
writel(APLL_CON1_VAL, &clk->apll_con1);
writel(APLL_CON0_VAL, &clk->apll_con0);
sdelay(0x30000);
/* Set MPLL */
writel(MPLL_CON1_VAL, &clk->mpll_con1);
writel(MPLL_CON0_VAL, &clk->mpll_con0);
sdelay(0x30000);
writel(BPLL_CON1_VAL, &clk->bpll_con1);
writel(BPLL_CON0_VAL, &clk->bpll_con0);
sdelay(0x30000);
/* Set CPLL */
writel(CPLL_CON1_VAL, &clk->cpll_con1);
writel(CPLL_CON0_VAL, &clk->cpll_con0);
sdelay(0x30000);
/* Set EPLL */
writel(EPLL_CON2_VAL, &clk->epll_con2);
writel(EPLL_CON1_VAL, &clk->epll_con1);
writel(EPLL_CON0_VAL, &clk->epll_con0);
sdelay(0x30000);
/* Set VPLL */
writel(VPLL_CON2_VAL, &clk->vpll_con2);
writel(VPLL_CON1_VAL, &clk->vpll_con1);
writel(VPLL_CON0_VAL, &clk->vpll_con0);
sdelay(0x30000);
/* Set MPLL */
/* After Initiallising th PLL select the sources accordingly */
/* MUX_APLL_SEL[0]: MOUTAPLLFOUT = 1 */
writel(CLK_SRC_CPU_VAL, &clk->src_cpu);
/* MUX_MPLL_SEL[8]: MOUTMPLLFOUT = 1 */
writel(CLK_SRC_CORE1_VAL, &clk->src_core1);
/* MUX_BPLL_SEL[0]: FOUTBPLL = 1*/
writel(CLK_SRC_CDREX_INIT_VAL, &clk->src_cdrex);
/*
* VPLLSRC_SEL[0]: FINPLL = 0
* MUX_{CPLL[8]}|{EPLL[12]}|{VPLL[16]}_SEL: MOUT{CPLL|EPLL|VPLL} = 1
* MUX_{MPLL[20]}|{BPLL[24]}_USER_SEL: FOUT{MPLL|BPLL} = 1
*/
writel(CLK_SRC_TOP2_VAL, &clk->src_top2);
}
/*
* Memory setup for SMDK5250 board based on EXYNOS5
*
* Copyright (C) 2012 Samsung Electronics
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <config.h>
#include <asm/io.h>
#include <asm/arch/dmc.h>
#include <asm/arch/clock.h>
#include <asm/arch/cpu.h>
#include "setup.h"
/* APLL : 1GHz */
/* MCLK_CDREX: MCLK_CDREX_533*/
/* LPDDR support: LPDDR2 */
static void reset_phy_ctrl(void);
static void config_zq(struct exynos5_phy_control *,
struct exynos5_phy_control *);
static void update_reset_dll(struct exynos5_dmc *);
static void config_cdrex(void);
static void config_mrs(struct exynos5_dmc *);
static void sec_sdram_phy_init(struct exynos5_dmc *);
static void config_prech(struct exynos5_dmc *);
static void config_rdlvl(struct exynos5_dmc *,
struct exynos5_phy_control *,
struct exynos5_phy_control *);
static void config_memory(struct exynos5_dmc *);
static void config_offsets(unsigned int,
struct exynos5_phy_control *,
struct exynos5_phy_control *);
static void reset_phy_ctrl(void)
{
struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
writel(PHY_RESET_VAL, &clk->lpddr3phy_ctrl);
sdelay(0x10000);
}
static void config_zq(struct exynos5_phy_control *phy0_ctrl,
struct exynos5_phy_control *phy1_ctrl)
{
unsigned long val = 0;
/*
* ZQ Calibration:
* Select Driver Strength,
* long calibration for manual calibration
*/
val = PHY_CON16_RESET_VAL;
SET_ZQ_MODE_DDS_VAL(val);
SET_ZQ_MODE_TERM_VAL(val);
val |= ZQ_CLK_DIV_EN;
writel(val, &phy0_ctrl->phy_con16);
writel(val, &phy1_ctrl->phy_con16);
/* Disable termination */
val |= ZQ_MODE_NOTERM;
writel(val, &phy0_ctrl->phy_con16);
writel(val, &phy1_ctrl->phy_con16);
/* ZQ_MANUAL_START: Enable */
val |= ZQ_MANUAL_STR;
writel(val, &phy0_ctrl->phy_con16);
writel(val, &phy1_ctrl->phy_con16);
sdelay(0x10000);
/* ZQ_MANUAL_START: Disable */
val &= ~ZQ_MANUAL_STR;
writel(val, &phy0_ctrl->phy_con16);
writel(val, &phy1_ctrl->phy_con16);
}
static void update_reset_dll(struct exynos5_dmc *dmc)
{
unsigned long val;
/*
* Update DLL Information:
* Force DLL Resyncronization
*/
val = readl(&dmc->phycontrol0);
val |= FP_RSYNC;
writel(val, &dmc->phycontrol0);
/* Reset Force DLL Resyncronization */
val = readl(&dmc->phycontrol0);
val &= ~FP_RSYNC;
writel(val, &dmc->phycontrol0);
}
static void config_mrs(struct exynos5_dmc *dmc)
{
unsigned long channel, chip, mask = 0, val;
for (channel = 0; channel < CONFIG_DMC_CHANNELS; channel++) {
SET_CMD_CHANNEL(mask, channel);
for (chip = 0; chip < CONFIG_CHIPS_PER_CHANNEL; chip++) {
/*
* NOP CMD:
* Assert and hold CKE to logic high level
*/
SET_CMD_CHIP(mask, chip);
val = DIRECT_CMD_NOP | mask;
writel(val, &dmc->directcmd);
sdelay(0x10000);
/* EMRS, MRS Cmds(Mode Reg Settings) Using Direct Cmd */
val = DIRECT_CMD_MRS1 | mask;
writel(val, &dmc->directcmd);
sdelay(0x10000);
val = DIRECT_CMD_MRS2 | mask;
writel(val, &dmc->directcmd);
sdelay(0x10000);
/* MCLK_CDREX_533 */
val = DIRECT_CMD_MRS3 | mask;
writel(val, &dmc->directcmd);
sdelay(0x10000);
val = DIRECT_CMD_MRS4 | mask;
writel(val, &dmc->directcmd);
sdelay(0x10000);
}
}
}
static void config_prech(struct exynos5_dmc *dmc)
{
unsigned long channel, chip, mask = 0, val;
for (channel = 0; channel < CONFIG_DMC_CHANNELS; channel++) {
SET_CMD_CHANNEL(mask, channel);
for (chip = 0; chip < CONFIG_CHIPS_PER_CHANNEL; chip++) {
SET_CMD_CHIP(mask, chip);
/* PALL (all banks precharge) CMD */
val = DIRECT_CMD_PALL | mask;
writel(val, &dmc->directcmd);
sdelay(0x10000);
}
}
}
static void sec_sdram_phy_init(struct exynos5_dmc *dmc)
{
unsigned long val;
val = readl(&dmc->concontrol);
val |= DFI_INIT_START;
writel(val, &dmc->concontrol);
sdelay(0x10000);
val = readl(&dmc->concontrol);
val &= ~DFI_INIT_START;
writel(val, &dmc->concontrol);
}
static void config_offsets(unsigned int state,
struct exynos5_phy_control *phy0_ctrl,
struct exynos5_phy_control *phy1_ctrl)
{
unsigned long val;
/* Set Offsets to read DQS */
val = (state == SET) ? SET_DQS_OFFSET_VAL : RESET_DQS_OFFSET_VAL;
writel(val, &phy0_ctrl->phy_con4);
writel(val, &phy1_ctrl->phy_con4);
/* Set Offsets to read DQ */
val = (state == SET) ? SET_DQ_OFFSET_VAL : RESET_DQ_OFFSET_VAL;
writel(val, &phy0_ctrl->phy_con6);
writel(val, &phy1_ctrl->phy_con6);
/* Debug Offset */
val = (state == SET) ? SET_DEBUG_OFFSET_VAL : RESET_DEBUG_OFFSET_VAL;
writel(val, &phy0_ctrl->phy_con10);
writel(val, &phy1_ctrl->phy_con10);
}
static void config_cdrex(void)
{
struct exynos5_clock *clk = (struct exynos5_clock *)EXYNOS5_CLOCK_BASE;
writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex);
writel(CLK_SRC_CDREX_VAL, &clk->src_cdrex);
sdelay(0x30000);
}
static void config_ctrl_dll_on(unsigned int state,
unsigned int ctrl_force_val,
struct exynos5_phy_control *phy0_ctrl,
struct exynos5_phy_control *phy1_ctrl)
{
unsigned long val;
val = readl(&phy0_ctrl->phy_con12);
CONFIG_CTRL_DLL_ON(val, state);
SET_CTRL_FORCE_VAL(val, ctrl_force_val);
writel(val, &phy0_ctrl->phy_con12);
val = readl(&phy1_ctrl->phy_con12);
CONFIG_CTRL_DLL_ON(val, state);
SET_CTRL_FORCE_VAL(val, ctrl_force_val);
writel(val, &phy1_ctrl->phy_con12);
}
static void config_ctrl_start(unsigned int state,
struct exynos5_phy_control *phy0_ctrl,
struct exynos5_phy_control *phy1_ctrl)
{
unsigned long val;
val = readl(&phy0_ctrl->phy_con12);
CONFIG_CTRL_START(val, state);
writel(val, &phy0_ctrl->phy_con12);
val = readl(&phy1_ctrl->phy_con12);
CONFIG_CTRL_START(val, state);
writel(val, &phy1_ctrl->phy_con12);
}
#if defined(CONFIG_RD_LVL)
static void config_rdlvl(struct exynos5_dmc *dmc,
struct exynos5_phy_control *phy0_ctrl,
struct exynos5_phy_control *phy1_ctrl)
{
unsigned long val;
/* Disable CTRL_DLL_ON and set ctrl_force */
config_ctrl_dll_on(RESET, 0x2D, phy0_ctrl, phy1_ctrl);
/*
* Set ctrl_gateadj, ctrl_readadj
* ctrl_gateduradj, rdlvl_pass_adj
* rdlvl_rddataPadj
*/
val = SET_RDLVL_RDDATAPADJ;
writel(val, &phy0_ctrl->phy_con1);
writel(val, &phy1_ctrl->phy_con1);
/* LPDDR2 Address */
writel(LPDDR2_ADDR, &phy0_ctrl->phy_con22);
writel(LPDDR2_ADDR, &phy1_ctrl->phy_con22);
/* Enable Byte Read Leveling set ctrl_ddr_mode */
val = readl(&phy0_ctrl->phy_con0);
val |= BYTE_RDLVL_EN;
writel(val, &phy0_ctrl->phy_con0);
val = readl(&phy1_ctrl->phy_con0);
val |= BYTE_RDLVL_EN;
writel(val, &phy1_ctrl->phy_con0);
/* rdlvl_en: Use levelling offset instead ctrl_shiftc */
val = PHY_CON2_RESET_VAL | RDLVL_EN;
writel(val, &phy0_ctrl->phy_con2);
writel(val, &phy1_ctrl->phy_con2);
sdelay(0x10000);
/* Enable Data Eye Training */
val = readl(&dmc->rdlvl_config);
val |= CTRL_RDLVL_DATA_EN;
writel(val, &dmc->rdlvl_config);
sdelay(0x10000);
/* Disable Data Eye Training */
val = readl(&dmc->rdlvl_config);
val &= ~CTRL_RDLVL_DATA_EN;
writel(val, &dmc->rdlvl_config);
/* RdDeSkew_clear: Clear */
val = readl(&phy0_ctrl->phy_con2);
val |= RDDSKEW_CLEAR;
writel(val, &phy0_ctrl->phy_con2);
val = readl(&phy1_ctrl->phy_con2);
val |= RDDSKEW_CLEAR;
writel(val, &phy1_ctrl->phy_con2);
/* Enable CTRL_DLL_ON */
config_ctrl_dll_on(SET, 0x0, phy0_ctrl, phy1_ctrl);
update_reset_dll(dmc);
sdelay(0x10000);
/* ctrl_atgte: ctrl_gate_p*, ctrl_read_p* generated by PHY */
val = readl(&phy0_ctrl->phy_con0);
val &= ~CTRL_ATGATE;
writel(val, &phy0_ctrl->phy_con0);
val = readl(&phy1_ctrl->phy_con0);
val &= ~CTRL_ATGATE;
writel(val, &phy1_ctrl->phy_con0);
}
#endif
static void config_memory(struct exynos5_dmc *dmc)
{
/*
* Memory Configuration Chip 0
* Address Mapping: Interleaved
* Number of Column address Bits: 10 bits
* Number of Rows Address Bits: 14
* Number of Banks: 8
*/
writel(DMC_MEMCONFIG0_VAL, &dmc->memconfig0);
/*
* Memory Configuration Chip 1
* Address Mapping: Interleaved
* Number of Column address Bits: 10 bits
* Number of Rows Address Bits: 14
* Number of Banks: 8
*/
writel(DMC_MEMCONFIG1_VAL, &dmc->memconfig1);
/*
* Chip0: AXI
* AXI Base Address: 0x40000000
* AXI Base Address Mask: 0x780
*/
writel(DMC_MEMBASECONFIG0_VAL, &dmc->membaseconfig0);
/*
* Chip1: AXI
* AXI Base Address: 0x80000000
* AXI Base Address Mask: 0x780
*/
writel(DMC_MEMBASECONFIG1_VAL, &dmc->membaseconfig1);
}
void mem_ctrl_init()
{
struct exynos5_phy_control *phy0_ctrl, *phy1_ctrl;
struct exynos5_dmc *dmc;
unsigned long val;
phy0_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY0_BASE;
phy1_ctrl = (struct exynos5_phy_control *)EXYNOS5_DMC_PHY1_BASE;
dmc = (struct exynos5_dmc *)EXYNOS5_DMC_CTRL_BASE;
/* Reset PHY Controllor: PHY_RESET[0] */
reset_phy_ctrl();