Commit 0cb61d7d authored by wdenk's avatar wdenk

Patch by Raghu Krishnaprasad, 7 Aug 2003:

add support for Adder II MPC852T module
parent 6f21347d
......@@ -2,6 +2,9 @@
Changes for U-Boot 0.4.7:
======================================================================
* Patch by Raghu Krishnaprasad, 7 Aug 2003:
add support for Adder II MPC852T module
* Patch by George G. Davis, 19 Aug 2003:
fix TI Innovator/OMAP1510 pin configs
......
......@@ -31,20 +31,21 @@ LIST_5xxx=" \
#########################################################################
LIST_8xx=" \
ADS860 AMX860 c2mon CCM \
cogent_mpc8xx ESTEEM192E ETX094 ELPT860 \
FADS823 FADS850SAR FADS860T FLAGADM \
FPS850L GEN860T GEN860T_SC GENIETV \
GTH hermes IAD210 ICU862_100MHz \
IP860 IVML24 IVML24_128 IVML24_256 \
IVMS8 IVMS8_128 IVMS8_256 KUP4K \
LANTEC lwmon MBX MBX860T \
MHPC MPC86xADS MVS1 NETVIA \
NETVIA_V2 NX823 pcu_e R360MPI \
RBC823 rmu RPXClassic RPXlite \
RRvision SM850 SPD823TS svm_sc8xx \
SXNI855T TOP860 TQM823L TQM823L_LCD \
TQM850L TQM855L TQM860L v37 \
AdderII ADS860 AMX860 c2mon \
CCM cogent_mpc8xx ESTEEM192E ETX094 \
ELPT860 FADS823 FADS850SAR FADS860T \
FLAGADM FPS850L GEN860T GEN860T_SC \
GENIETV GTH hermes IAD210 \
ICU862_100MHz IP860 IVML24 IVML24_128 \
IVML24_256 IVMS8 IVMS8_128 IVMS8_256 \
KUP4K LANTEC lwmon MBX \
MBX860T MHPC MPC86xADS MVS1 \
NETVIA NETVIA_V2 NX823 pcu_e \
R360MPI RBC823 rmu RPXClassic \
RPXlite RRvision SM850 SPD823TS \
svm_sc8xx SXNI855T TOP860 TQM823L \
TQM823L_LCD TQM850L TQM855L TQM860L \
v37 \
"
#########################################################################
......
......@@ -210,6 +210,9 @@ IceCube_5100_config: unconfig
## MPC8xx Systems
#########################################################################
AdderII_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx adderII
ADS860_config: unconfig
@./mkconfig $(@:_config=) ppc mpc8xx fads
......
#
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS = $(BOARD).o flash.o
$(LIB): .depend $(OBJS)
$(AR) crv $@ $(OBJS)
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
sinclude .depend
#########################################################################
/*
* (C) Copyright 2000-2003
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <config.h>
#include <mpc8xx.h>
/*
* Check Board Identity:
*/
int checkboard( void )
{
puts("Board: ");
puts("AdderII(MPC852T)\n" );
return 0;
}
#if defined( CONFIG_SDRAM_50MHZ )
/******************************************************************************
** for chip Samsung K4S643232F - T70
** this table is for 32-50MHz operation
*******************************************************************************/
#define SDRAM_MPTPRVALUE 0x0200
#define SDRAM_MAMRVALUE0 0x00802114 /* refresh at 32MHz */
#define SDRAM_MAMRVALUE1 0x00802118
#define SDRAM_OR1VALUE 0xff800e00
#define SDRAM_BR1VALUE 0x00000081
#define SDRAM_MARVALUE 94
#define SDRAM_MCRVALUE0 0x80808105
#define SDRAM_MCRVALUE1 0x80808130
const uint sdram_table[] = {
/* single read (offset 0x00 in upm ram) */
0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xe0bbbc00,
0x10f77c44, 0xf3fffc07, 0xfffffc04, 0xfffffc04,
/* burst read (offset 0x08 in upm ram) */
0x1f07fc24, 0xe0aefc04, 0x10adfc04, 0xf0affc00,
0xf0affc00, 0xf0affc00, 0xf0affc00, 0x10a77c44,
0xf7bffc47, 0xfffffc35, 0xfffffc34, 0xfffffc35,
0xfffffc35, 0x1ff77c35, 0xfffffc34, 0x1fb57c35,
/* single write (offset 0x18 in upm ram) */
0x1f27fc24, 0xe0aebc04, 0x00b93c00, 0x13f77c47,
0xfffdfc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
/* burst write (offset 0x20 in upm ram) */
0x1f07fc24, 0xeeaebc00, 0x10ad7c00, 0xf0affc00,
0xf0affc00, 0xe0abbc00, 0x1fb77c47, 0xfffffc04,
0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
/* refresh (offset 0x30 in upm ram) */
0x1ff5fca4, 0xfffffc04, 0xfffffc04, 0xfffffc04,
0xfffffc84, 0xfffffc07, 0xfffffc04, 0xfffffc04,
0xfffffc04, 0xfffffc04, 0xfffffc04, 0xfffffc04,
/* exception (offset 0x3C in upm ram) */
0xfffffc27, 0xfffffc04, 0xfffffc04, 0xfffffc04,
};
#else
#error SDRAM not correctly configured
#endif
int _initsdram (uint base, uint noMbytes)
{
volatile immap_t *immap = (immap_t *) CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
if (noMbytes != 8) {
return -1;
}
upmconfig (UPMA, (uint *) sdram_table,
sizeof (sdram_table) / sizeof (uint));
memctl->memc_mptpr = SDRAM_MPTPRVALUE;
/* Configure the refresh (mostly). This needs to be
* based upon processor clock speed and optimized to provide
* the highest level of performance. For multiple banks,
* this time has to be divided by the number of banks.
* Although it is not clear anywhere, it appears the
* refresh steps through the chip selects for this UPM
* on each refresh cycle.
* We have to be careful changing
* UPM registers after we ask it to run these commands.
*/
memctl->memc_mamr = (SDRAM_MAMRVALUE0 | (SDRAM_MARVALUE << 24));
memctl->memc_mar = 0x0;
udelay (200);
/* Now run the precharge/nop/mrs commands.
*/
memctl->memc_mcr = 0x80002115;
udelay (200);
/* Run 8 refresh cycles */
memctl->memc_mcr = 0x80002380;
udelay (200);
memctl->memc_mar = 0x88;
udelay (200);
memctl->memc_mcr = 0x80002116;
udelay (200);
memctl->memc_or1 = SDRAM_OR1VALUE;
memctl->memc_br1 = SDRAM_BR1VALUE | base;
return 0;
}
void _sdramdisable( void )
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8xx_t *memctl = &immap->im_memctl;
memctl->memc_br1 = 0x00000000;
/* maybe we should turn off upma here or something */
}
int initsdram (uint base, uint * noMbytes)
{
uint m = 8;
*noMbytes = m;
if (!_initsdram (base, m)) {
return 0;
} else {
_sdramdisable ();
return -1;
}
}
long int initdram (int board_type)
{
/* AdderII: has 8MB SDRAM */
uint sdramsz;
uint m = 0;
if (!initsdram (0x00000000, &sdramsz)) {
m += sdramsz;
} else {
return -1;
}
return (m << 20);
}
int testdram (void)
{
/* TODO: XXX XXX XXX not an actual SDRAM test */
printf ("Test: 8MB SDRAM\n");
return (0);
}
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/****************************************************************************
* FLASH Memory Map as used by FADS Monitor:
*
* Start Address Length
* +-----------------------+ 0xFE00_0000 Start of Flash -----------------
* | MON8xx code | 0xFE00_0100 Reset Vector
* +-----------------------+ 0xFE0?_????
* | (unused) |
* +-----------------------+
* | |
* +-----------------------+
* | |
* +-----------------------+
* | |
* +-----------------------+
* | |
* +=======================+
* | |
* | ... |
*****************************************************************************/
#
# (C) Copyright 2000
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# AdderII board ( Analogue-Micro )
#
TEXT_BASE = 0xFE000000
This diff is collapsed.
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/mpc8xx/start.o (.text)
/*
cpu/mpc8xx/start.o (.text)
common/dlmalloc.o (.text)
lib_ppc/ppcstring.o (.text)
lib_generic/vsprintf.o (.text)
lib_generic/crc32.o (.text)
lib_generic/zlib.o (.text)
. = env_offset;
common/environment.o(.text)
*/
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x0FFF) & 0xFFFFF000;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
. = ALIGN(256 * 1024);
.ppcenv :
{
common/environment.o (.ppcenv)
}
_end = . ;
PROVIDE (end = .);
}
#
# (C) Copyright 2000
# (C) Copyright 2000-2003
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
......
......@@ -98,6 +98,7 @@ static int check_CPU (long clock, uint pvr, uint immr)
case 0x00310065: mid = "SR"; suf = "C1"; m = 1; break;
case 0x05010000: suf = "D3"; m = 1; break;
case 0x05020000: suf = "D4"; m = 1; break;
case 0x08000003: suf = ""; m = 1; break;
/* this value is not documented anywhere */
case 0x40000000: pre = 'P'; suf = "D"; m = 1; break;
#endif
......
......@@ -132,7 +132,8 @@ void cpu_init_f (volatile immap_t * immr)
* I owe him a free beer. - wd]
*/
#if defined(CONFIG_GTH) || \
#if defined(CONFIG_ADDERII) || \
defined(CONFIG_GTH) || \
defined(CONFIG_HERMES) || \
defined(CONFIG_ICU862) || \
defined(CONFIG_IP860) || \
......
/******************************************************************************
* A collection of structures, addresses, and values associated with
* the Motorola 850T AdderIIF board. Copied from the FADS stuff.
* Magnus Damm added defines for 8xxrom and extended bd_info.
* Helmut Buchsbaum added bitvalues for BCSRx
*
* Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
*******************************************************************************
* 2003-JUL: The AdderII is using the following physical memorymap:
*******************************************************************************
* FA200000 -> FA20FFFF : IMAP internal in the cpu
* FE000000 -> FE400000 : flash connected to CS0, setup by 8xxrom
* 00000000 -> 00800000 : sdram setup by 8xxrom
*******************************************************************************/
#ifndef __CONFIG_H
#define __CONFIG_H
#include <mpc8xx_irq.h>
#define CONFIG_MPC860 1
#define CONFIG_MPC860T 1
#define CONFIG_ADDERII 1
/* CPU Clock speed */
#define MPC8XX_FACT 12 /* Multilpy by 12 */
#define MPC8XX_XIN 4000000 /* 4MHz */
#define MPC8XX_HZ ( MPC8XX_FACT * MPC8XX_XIN )
#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
#define CONFIG_SDRAM_50MHZ 1
/* Default Serial Console, baudrate */
#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
#define CONFIG_BAUDRATE 38400
#define CONFIG_LOADS_ECHO 1
/* FEC Ethernet controller configurations */
#define CONFIG_FEC_ETH 1
#define CONFIG_NET_MULTI 1
#define FEC_ENET 1
/* Interrupt level assignments.
*/
#define FEC_INTERRUPT SIU_LEVEL3 /* FEC interrupt */
/* Older kernels need clock in MHz newer in Hz */
#define CONFIG_CLOCKS_IN_MHZ 1
/* Monitor Functions */
#define CONFIG_COMMANDS ( CFG_CMD_FLASH | \
CFG_CMD_MEMORY| \
CFG_CMD_NET | \
CFG_CMD_ENV | \
CFG_CMD_PING | \
CFG_CMD_SDRAM )
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>
/* Configuration Settings */
#define CFG_PROMPT "=>" /* Monitor Command Prompt */
#if ( CONFIG_COMMANDS & CFG_CMD_KGDB )
#define CFG_CBSIZE 1024 /* Console I/P buffer size */
#else
#define CFG_CBSIZE 256
#endif
#define CFG_PBSIZE ( CFG_CBSIZE + sizeof( CFG_PROMPT ) + 16 )
/* Print buffer size */
#define CFG_MAXARGS 16 /* Max number of cmd args */
#define CFG_BARGSIZE CFG_CBSIZE /* Boot args buffer size */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CFG_MEMTEST_START 0x00100000 /* Mem test works on */
#define CFG_MEMTEST_END 0x00800000 /* 1 ... 8MB in SDRAM */
#define CFG_LOAD_ADDR 0x00100000
#define CFG_HZ 1000
/******************************************************************************
** Low level configuration settings.
** ( adderss mappings, register init values, etc. )
** You should know what you are doing if you make changes here.
******************************************************************************/
/* Start address for the final memory configuration set up by startup code
** Please note that CFG_SDRAM_BASE must start at 0
*/
#define CFG_SDRAM_BASE 0x00000000
#define CFG_FLASH_BASE 0xFE000000
#define CFG_FLASH_SIZE (( uint ) ( 4 * 1024 * 1024 )) /* 4MB */
#define CFG_MONITOR_BASE CFG_FLASH_BASE
#define CFG_MONITOR_LEN ( 256 << 10 ) /* 256 KByte */
#define CFG_MALLOC_LEN ( 384 << 10 ) /* 384 KByte SDRAM rsvd */
/* malloc() usage */
/**
** For booting Linux, the board info and command line data
** have to be in the first 8 MB of memory, since this is
** the maximum mapped by the Linux kernel during initialization.
**/
#define CFG_BOOTMAPSZ ( 8 << 20 ) /* Initial Memory map for Linux */
/******************************************************************************
** Flash Organization
******************************************************************************/
#define CFG_MAX_FLASH_BANKS 1 /* Max no of flash mem banks */
#define CFG_MAX_FLASH_SECT 71 /* Max no of sec on 1 chip */
#define CFG_FLASH_ERASE_TOUT 120000 /* Erase flash timeout (ms) */
#define CFG_FLASH_WRITE_TOUT 500 /* Write flash timeout (ms) */
/******************************************************************************
** U-BOOT Environment variables in Flash
******************************************************************************/
#define CFG_ENV_IS_IN_FLASH 1
#define CFG_ENV_OFFSET 0x00040000
#define CFG_ENV_SIZE 0x10000 /* 64KBytes env space */
#define CFG_ENV_SECT_SIZE 0x10000
/******************************************************************************
** Cache Configuration
******************************************************************************/
#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
#if ( CONFIG_COMMANDS & CFG_CMD_KGDB )
#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
#endif
/******************************************************************************
** Internal memory mapped register
******************************************************************************/
#define CFG_IMMR 0xFA200000
#define CFG_IMMR_SIZE (( uint) ( 62 * 1024 )) /* 64 KByte res */
/* Definitions for initial stack pointer and data area ( in DPRAM ) */
#define CFG_INIT_RAM_ADDR CFG_IMMR
#define CFG_INIT_RAM_END 0x2F00 /* end of used area in DPRAM */
#define CFG_GBL_DATA_SIZE 64
#define CFG_GBL_DATA_OFFSET ( CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE )
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
/* SIU Module Configuration Register */
#define CFG_SIUMCR ( SIUMCR_AEME | SIUMCR_MLRC01 | SIUMCR_DBGC10 )
/******************************************************************************
** SYPCR - System protection and control
** SYPCR - can be written only once after reset
******************************************************************************/
#if defined( CONFIG_WATCHDOG )
#define CFG_SYPCR ( SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \
SYPCR_SWF | SYPCR_SWE | SYPCR_SWRI | \
SYPCR_SWP )
#else
#define CFG_SYPCR ( SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | \
SYPCR_SWF | SYPCR_SWP )
#endif
/* TBSCR - Time Base Status and Control Register */
#define CFG_TBSCR ( TBSCR_REFA | TBSCR_REFB | TBSCR_TBE )
/* PISCR - Periodic Interrupt Status and Control */
#define CFG_PISCR ( PISCR_PS | PISCR_PITF )
/* PLPRCR - PLL, Low-Power, and Reset Control Register */
#define CFG_PLPRCR ((( MPC8XX_FACT - 1 ) << PLPRCR_MF_SHIFT ) | \
PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST )
/* SCCR - System Clock and reset Control Register */
#define SCCR_MASK SCCR_EBDF11
#define CFG_SCCR ( SCCR_TBS | SCCR_COM00 | SCCR_DFSYNC00 | \
SCCR_DFBRG00 | SCCR_DFNL000| SCCR_DFNH000 | \
SCCR_DFLCD000 | SCCR_DFALCD00 )
#define CFG_DER 0
/******************************************************************************
** Because of the way the 860 starts up and assigns CS0 the
** entire address space, we have to set the memory controller
** differently. Normally, you write the option register
** first, and then enable the chip select by writing the
** base register. For CS0, you must write the base register
** first, followed by the option register.
******************************************************************************/
/**
** Memory Controller Definitions
** BR0/1/2... and OR0/1/2...
*/
/* For AdderII BR0 FLASH */
#define CFG_REMAP_OR_AM 0xFF800000 /* OR addr mask */
#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
/* Flash Timings: ACS = 11, TRLX = 1, CSNT = 0, SCY = 7 */
#define CFG_OR_TIMING_FLASH ( OR_ACS_DIV2 | OR_BI | OR_SCY_7_CLK | OR_TRLX )
#define CFG_OR0_REMAP ( CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH )
#define CFG_OR0_PRELIM CFG_OR0_REMAP
#define CFG_BR0_PRELIM (( CFG_FLASH_BASE & BR_BA_MSK ) | \
BR_PS_16 | BR_V )
/* For AdderII BR1 SDRAM */
#define CFG_PRELIM_OR1_AM 0xFF800000
#define CFG_OR1_REMAP ( CFG_PRELIM_OR1_AM | OR_CSNT_SAM | OR_ACS_DIV2 )