Commit 0f8ec145 authored by Ye.Li's avatar Ye.Li Committed by Stefano Babic
Browse files

imx: mx6sl: Set the preclk clock source to OSC 24Mhz



For MX6SL, uses the OSC 24Mhz as the preclk source in CCM. Align the
preclk setting with kernel.
Signed-off-by: default avatarYe.Li <B37916@freescale.com>
parent e68661a3
......@@ -239,6 +239,18 @@ static void clear_mmdc_ch_mask(void)
writel(0, &mxc_ccm->ccdr);
}
#ifdef CONFIG_MX6SL
static void set_preclk_from_osc(void)
{
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
u32 reg;
reg = readl(&mxc_ccm->cscmr1);
reg |= MXC_CCM_CSCMR1_PER_CLK_SEL_MASK;
writel(reg, &mxc_ccm->cscmr1);
}
#endif
int arch_cpu_init(void)
{
init_aips();
......@@ -254,6 +266,11 @@ int arch_cpu_init(void)
if (mxc_get_clock(MXC_ARM_CLK) == 396000000)
set_ahb_rate(132000000);
/* Set perclk to source from OSC 24MHz */
#if defined(CONFIG_MX6SL)
set_preclk_from_osc();
#endif
imx_set_wdog_powerdown(false); /* Disable PDE bit of WMCR register */
#ifdef CONFIG_APBH_DMA
......
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