Commit 0fcb9f07 authored by Tom Rini's avatar Tom Rini

Merge branch 'master' of git://git.denx.de/u-boot-atmel

parents 2ef98d33 a0d0d86f
......@@ -270,6 +270,9 @@ dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \
k2e-evm.dtb \
k2g-evm.dtb
dtb-$(CONFIG_TARGET_SAMA5D2_XPLAINED) += \
at91-sama5d2_xplained.dtb
targets += $(dtb-y)
# Add any required device tree compiler flags here
......
/dts-v1/;
#include "sama5d2.dtsi"
#include "sama5d2-pinfunc.h"
/ {
model = "Atmel SAMA5D2 Xplained";
compatible = "atmel,sama5d2-xplained", "atmel,sama5d2", "atmel,sama5";
chosen {
stdout-path = &uart1;
};
ahb {
usb1: ohci@00400000 {
num-ports = <3>;
atmel,vbus-gpio = <&pioA 42 0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_default>;
status = "okay";
};
usb2: ehci@00500000 {
status = "okay";
};
sdmmc0: sdio-host@a0000000 {
bus-width = <8>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc0_cmd_dat_default &pinctrl_sdmmc0_ck_cd_default>;
status = "okay";
};
sdmmc1: sdio-host@b0000000 {
bus-width = <4>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sdmmc1_cmd_dat_default &pinctrl_sdmmc1_ck_cd_default>;
status = "okay"; /* conflict with qspi0 */
};
apb {
qspi0: spi@f0020000 {
status = "okay";
flash@0 {
compatible = "atmel,sama5d2-qspi-flash";
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi0_default>;
spi-max-frequency = <83000000>;
partition@00000000 {
label = "boot";
reg = <0x00000000 0x00c00000>;
};
partition@00c00000 {
label = "rootfs";
reg = <0x00c00000 0x00000000>;
};
};
};
spi0: spi@f8000000 {
cs-gpios = <&pioA 17 0>, <0>, <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0_default>;
status = "okay";
spi_flash@0 {
compatible = "spi-flash";
reg = <0>;
spi-max-frequency = <50000000>;
};
};
macb0: ethernet@f8008000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_macb0_rmii &pinctrl_macb0_phy_irq>;
phy-mode = "rmii";
status = "okay";
ethernet-phy@1 {
reg = <0x1>;
};
};
uart1: serial@f8020000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1_default>;
status = "okay";
};
i2c1: i2c@fc028000 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1_default>;
status = "okay";
};
pioA: gpio@fc038000 {
pinctrl {
pinctrl_i2c1_default: i2c1_default {
pinmux = <PIN_PD4__TWD1>,
<PIN_PD5__TWCK1>;
bias-disable;
};
pinctrl_macb0_phy_irq: macb0_phy_irq {
pinmux = <PIN_PC9__GPIO>;
bias-disable;
};
pinctrl_macb0_rmii: macb0_rmii {
pinmux = <PIN_PB14__GTXCK>,
<PIN_PB15__GTXEN>,
<PIN_PB16__GRXDV>,
<PIN_PB17__GRXER>,
<PIN_PB18__GRX0>,
<PIN_PB19__GRX1>,
<PIN_PB20__GTX0>,
<PIN_PB21__GTX1>,
<PIN_PB22__GMDC>,
<PIN_PB23__GMDIO>;
bias-disable;
};
pinctrl_qspi0_default: qspi0_default {
pinmux = <PIN_PA22__QSPI0_SCK>,
<PIN_PA23__QSPI0_CS>,
<PIN_PA24__QSPI0_IO0>,
<PIN_PA25__QSPI0_IO1>,
<PIN_PA26__QSPI0_IO2>,
<PIN_PA27__QSPI0_IO3>;
bias-disable;
};
pinctrl_sdmmc0_cmd_dat_default: sdmmc0_cmd_dat_default {
pinmux = <PIN_PA1__SDMMC0_CMD>,
<PIN_PA2__SDMMC0_DAT0>,
<PIN_PA3__SDMMC0_DAT1>,
<PIN_PA4__SDMMC0_DAT2>,
<PIN_PA5__SDMMC0_DAT3>,
<PIN_PA6__SDMMC0_DAT4>,
<PIN_PA7__SDMMC0_DAT5>,
<PIN_PA8__SDMMC0_DAT6>,
<PIN_PA9__SDMMC0_DAT7>;
bias-pull-up;
};
pinctrl_sdmmc0_ck_cd_default: sdmmc0_ck_cd_default {
pinmux = <PIN_PA0__SDMMC0_CK>,
<PIN_PA10__SDMMC0_RSTN>,
<PIN_PA11__SDMMC0_VDDSEL>,
<PIN_PA13__SDMMC0_CD>;
bias-disable;
};
pinctrl_sdmmc1_cmd_dat_default: sdmmc1_cmd_dat_default {
pinmux = <PIN_PA28__SDMMC1_CMD>,
<PIN_PA18__SDMMC1_DAT0>,
<PIN_PA19__SDMMC1_DAT1>,
<PIN_PA20__SDMMC1_DAT2>,
<PIN_PA21__SDMMC1_DAT3>;
bias-pull-up;
};
pinctrl_sdmmc1_ck_cd_default: sdmmc1_ck_cd_default {
pinmux = <PIN_PA22__SDMMC1_CK>,
<PIN_PA30__SDMMC1_CD>;
bias-disable;
};
pinctrl_spi0_default: spi0_default {
pinmux = <PIN_PA14__SPI0_SPCK>,
<PIN_PA15__SPI0_MOSI>,
<PIN_PA16__SPI0_MISO>;
bias-disable;
};
pinctrl_uart1_default: uart1_default {
pinmux = <PIN_PD2__URXD1>,
<PIN_PD3__UTXD1>;
bias-disable;
};
pinctrl_usb_default: usb_default {
pinmux = <PIN_PB10__GPIO>;
bias-disable;
};
pinctrl_usba_vbus: usba_vbus {
pinmux = <PIN_PA31__GPIO>;
bias-disable;
};
};
};
};
};
};
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......@@ -149,6 +149,9 @@ typedef struct at91_pmc {
#define AT91_PMC_PCR_PID_MASK (0x3f)
#define AT91_PMC_PCR_GCKCSS (0x7 << 8)
#define AT91_PMC_PCR_GCKCSS_MASK 0x07
#define AT91_PMC_PCR_GCKCSS_OFFSET 8
#define AT91_PMC_PCR_GCKCSS_(x) ((x & 0x07) << 8)
#define AT91_PMC_PCR_GCKCSS_SLOW_CLK (0x0 << 8)
#define AT91_PMC_PCR_GCKCSS_MAIN_CLK (0x1 << 8)
#define AT91_PMC_PCR_GCKCSS_PLLA_CLK (0x2 << 8)
......@@ -158,8 +161,9 @@ typedef struct at91_pmc {
#define AT91_PMC_PCR_CMD_WRITE (0x1 << 12)
#define AT91_PMC_PCR_DIV (0x3 << 16)
#define AT91_PMC_PCR_GCKDIV (0xff << 20)
#define AT91_PMC_PCR_GCKDIV_(x) (((x) & 0xff) << 20)
#define AT91_PMC_PCR_GCKDIV_OFFSET 20
#define AT91_PMC_PCR_GCKDIV_MASK 0xff
#define AT91_PMC_PCR_GCKDIV_OFFSET 20
#define AT91_PMC_PCR_GCKDIV_(x) ((x & 0xff) << 20)
#define AT91_PMC_PCR_EN (0x1 << 28)
#define AT91_PMC_PCR_GCKEN (0x1 << 29)
......@@ -243,8 +247,9 @@ typedef struct at91_pmc {
#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
#define AT91_PMC_MOSCSELS BIT(16) /* Main Oscillator Selection Status */
#define AT91_PMC_MOSCRCS BIT(17) /* 12 MHz RC Oscillator Status */
#define AT91_PMC_GCKRDY (1 << 24)
#define AT91_PMC_PROTKEY 0x504d4301 /* Activation Code */
/* PLL Charge Pump Current Register (PMC_PLLICPR) */
......
......@@ -29,6 +29,41 @@ struct atmel_pio4_port {
#endif
/*
* PIO Configuration Register Fields
*/
#define ATMEL_PIO_CFGR_FUNC_MASK GENMASK(2, 0)
#define ATMEL_PIO_CFGR_FUNC_GPIO (0x0 << 0)
#define ATMEL_PIO_CFGR_FUNC_PERIPH_A (0x1 << 0)
#define ATMEL_PIO_CFGR_FUNC_PERIPH_B (0x2 << 0)
#define ATMEL_PIO_CFGR_FUNC_PERIPH_C (0x3 << 0)
#define ATMEL_PIO_CFGR_FUNC_PERIPH_D (0x4 << 0)
#define ATMEL_PIO_CFGR_FUNC_PERIPH_E (0x5 << 0)
#define ATMEL_PIO_CFGR_FUNC_PERIPH_F (0x6 << 0)
#define ATMEL_PIO_CFGR_FUNC_PERIPH_G (0x7 << 0)
#define ATMEL_PIO_DIR_MASK BIT(8)
#define ATMEL_PIO_PUEN_MASK BIT(9)
#define ATMEL_PIO_PDEN_MASK BIT(10)
#define ATMEL_PIO_IFEN_MASK BIT(12)
#define ATMEL_PIO_IFSCEN_MASK BIT(13)
#define ATMEL_PIO_OPD_MASK BIT(14)
#define ATMEL_PIO_SCHMITT_MASK BIT(15)
#define ATMEL_PIO_CFGR_EVTSEL_MASK GENMASK(26, 24)
#define ATMEL_PIO_CFGR_EVTSEL_FALLING (0 << 24)
#define ATMEL_PIO_CFGR_EVTSEL_RISING (1 << 24)
#define ATMEL_PIO_CFGR_EVTSEL_BOTH (2 << 24)
#define ATMEL_PIO_CFGR_EVTSEL_LOW (3 << 24)
#define ATMEL_PIO_CFGR_EVTSEL_HIGH (4 << 24)
#define ATMEL_PIO_NPINS_PER_BANK 32
#define ATMEL_PIO_BANK(pin_id) (pin_id / ATMEL_PIO_NPINS_PER_BANK)
#define ATMEL_PIO_LINE(pin_id) (pin_id % ATMEL_PIO_NPINS_PER_BANK)
#define ATMEL_PIO_BANK_OFFSET 0x40
#define ATMEL_GET_PIN_NO(pinfunc) ((pinfunc) & 0xff)
#define ATMEL_GET_PIN_FUNC(pinfunc) ((pinfunc >> 16) & 0xf)
#define ATMEL_GET_PIN_IOSET(pinfunc) ((pinfunc >> 20) & 0xf)
#define AT91_PIO_PORTA 0x0
#define AT91_PIO_PORTB 0x1
#define AT91_PIO_PORTC 0x2
......
I2C for Atmel platforms
Required properties :
- compatible : Must be "atmel,at91rm9200-i2c", "atmel,at91sam9261-i2c",
"atmel,at91sam9260-i2c", "atmel,at91sam9g20-i2c", "atmel,at91sam9g10-i2c",
"atmel,at91sam9x5-i2c", "atmel,sama5d4-i2c" or "atmel,sama5d2-i2c".
- reg: physical base address of the controller and length of memory mapped
region.
- #address-cells = <1>;
- #size-cells = <0>;
- clocks: phandles to input clocks.
Optional properties:
- clock-frequency: Desired I2C bus frequency in Hz, default value is 100000.
- Child nodes conforming to i2c bus binding.
Examples :
i2c0: i2c@f8028000 {
compatible = "atmel,sama5d2-i2c";
reg = <0xf8028000 0x100>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&twi0_clk>;
clock-frequency = <100000>;
};
* Atmel PIO4 Controller
The Atmel PIO4 controller is used to select the function of a pin and to
configure it.
Required properties:
- compatible: "atmel,sama5d2-pinctrl".
- reg: base address and length of the PIO controller.
Please refer to pinctrl-bindings.txt in this directory for details of the
common pinctrl bindings used by client devices.
Subnode format
Each node (or subnode) will list the pins it needs and how to configured these
pins.
node {
pinmux = <PIN_NUMBER_PINMUX>;
GENERIC_PINCONFIG;
};
Required properties:
- pinmux: integer array. Each integer represents a pin number plus mux and
ioset settings. Use the macros from boot/dts/<soc>-pinfunc.h file to get the
right representation of the pin.
Optional properties:
- GENERIC_PINCONFIG: generic pinconfig options to use, bias-disable,
bias-pull-down, bias-pull-up, drive-open-drain, input-schmitt-enable,
input-debounce.
Example:
#include <sama5d2-pinfunc.h>
...
{
spi0: spi@f8000000 {
cs-gpios = <&pioA 17 0>, <0>, <0>, <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi0_default>;
status = "okay";
spi_flash@0 {
compatible = "spi-flash";
reg = <0>;
spi-max-frequency = <50000000>;
};
};
...
pioA: pinctrl@fc038000 {
compatible = "atmel,sama5d2-pinctrl";
reg = <0xfc038000 0x600>;
pinctrl_spi0_default: spi0_default {
pinmux = <PIN_PA14__SPI0_SPCK>,
<PIN_PA15__SPI0_MOSI>,
<PIN_PA16__SPI0_MISO>;
bias-disable;
};
...
};
};
...
......@@ -23,5 +23,6 @@ config SPL_CLK
source "drivers/clk/tegra/Kconfig"
source "drivers/clk/uniphier/Kconfig"
source "drivers/clk/exynos/Kconfig"
source "drivers/clk/at91/Kconfig"
endmenu
......@@ -14,3 +14,4 @@ obj-$(CONFIG_MACH_PIC32) += clk_pic32.o
obj-y += tegra/
obj-$(CONFIG_CLK_UNIPHIER) += uniphier/
obj-$(CONFIG_CLK_EXYNOS) += exynos/
obj-$(CONFIG_CLK_AT91) += at91/
config CLK_AT91
bool "AT91 clock drivers"
depends on CLK
help
This option is used to enable the AT91 clock driver.
The driver supports the AT91 clock generator, including
the oscillators and PLLs, such as main clock, slow clock,
PLLA, UTMI PLL. Clocks can also be a source clock of other
clocks a tree structure, such as master clock, usb device
clock, matrix clock and generic clock.
Devices can use a common clock API to request a particular
clock, enable it and get its rate.
config AT91_UTMI
bool "Support UTMI PLL Clock"
depends on CLK_AT91
help
This option is used to enable the AT91 UTMI PLL clock
driver. It is the clock provider of USB, and UPLLCK is the
output of 480 MHz UTMI PLL, The souce clock of the UTMI
PLL is the main clock, so the main clock must select the
fast crystal oscillator to meet the frequency accuracy
required by USB.
config AT91_H32MX
bool "Support H32MX 32-bit Matrix Clock"
depends on CLK_AT91
help
This option is used to enable the AT91 H32MX matrixes
clock driver. There are H64MX and H32MX matrixes clocks,
H64MX 64-bit matrix clocks are MCK. The H32MX 32-bit
matrix clock is to be configured as MCK if MCK does not
exceed 83 MHz, else it is to be configured as MCK/2.
config AT91_GENERIC_CLK
bool "Support Generic Clock"
depends on CLK_AT91
help
This option is used to enable the AT91 generic clock
driver. Some peripherals may need a second clock source
that may be different from the system clock. This second
clock is the generic clock (GCLK) and is managed by
the PMC via PMC_PCR register.
#
# Makefile for at91 specific clk
#
obj-y += pmc.o sckc.o
obj-y += clk-slow.o clk-main.o clk-plla.o clk-master.o
obj-y += clk-system.o clk-peripheral.o
obj-$(CONFIG_AT91_UTMI) += clk-utmi.o
obj-$(CONFIG_AT91_H32MX) += clk-h32mx.o
obj-$(CONFIG_AT91_GENERIC_CLK) += clk-generated.o
/*
* Copyright (C) 2016 Atmel Corporation
* Wenyou.Yang <wenyou.yang@atmel.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <clk-uclass.h>
#include <dm/device.h>
#include <linux/io.h>
#include <mach/at91_pmc.h>
#include "pmc.h"
DECLARE_GLOBAL_DATA_PTR;
#define GENERATED_SOURCE_MAX 6
#define GENERATED_MAX_DIV 255
struct generated_clk_priv {
u32 num_parents;
};
static ulong generated_clk_get_rate(struct clk *clk)
{
struct pmc_platdata *plat = dev_get_platdata(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
struct clk parent;
u32 tmp, gckdiv;
u8 parent_id;
int ret;
writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
tmp = readl(&pmc->pcr);
parent_id = (tmp >> AT91_PMC_PCR_GCKCSS_OFFSET) &
AT91_PMC_PCR_GCKCSS_MASK;
gckdiv = (tmp >> AT91_PMC_PCR_GCKDIV_OFFSET) & AT91_PMC_PCR_GCKDIV_MASK;
ret = clk_get_by_index(clk->dev, parent_id, &parent);
if (ret)
return 0;
return clk_get_rate(&parent) / (gckdiv + 1);
}
static ulong generated_clk_set_rate(struct clk *clk, ulong rate)
{
struct pmc_platdata *plat = dev_get_platdata(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
struct generated_clk_priv *priv = dev_get_priv(clk->dev);
struct clk parent, best_parent;
ulong tmp_rate, best_rate = rate, parent_rate;
int tmp_diff, best_diff = -1;
u32 div, best_div = 0;
u8 best_parent_id = 0;
u8 i;
u32 tmp;
int ret;
for (i = 0; i < priv->num_parents; i++) {
ret = clk_get_by_index(clk->dev, i, &parent);
if (ret)
return ret;
parent_rate = clk_get_rate(&parent);
if (IS_ERR_VALUE(parent_rate))
return parent_rate;
for (div = 1; div < GENERATED_MAX_DIV + 2; div++) {
tmp_rate = DIV_ROUND_CLOSEST(parent_rate, div);
if (rate < tmp_rate)
continue;
tmp_diff = rate - tmp_rate;
if (best_diff < 0 || best_diff > tmp_diff) {
best_rate = tmp_rate;
best_diff = tmp_diff;
best_div = div - 1;
best_parent = parent;
best_parent_id = i;
}
if (!best_diff || tmp_rate < rate)
break;
}
if (!best_diff)
break;
}
debug("GCK: best parent: %s, best_rate = %ld, best_div = %d\n",
best_parent.dev->name, best_rate, best_div);
ret = clk_enable(&best_parent);
if (ret)
return ret;
writel(clk->id & AT91_PMC_PCR_PID_MASK, &pmc->pcr);
tmp = readl(&pmc->pcr);
tmp &= ~(AT91_PMC_PCR_GCKDIV | AT91_PMC_PCR_GCKCSS);
tmp |= AT91_PMC_PCR_GCKCSS_(best_parent_id) |
AT91_PMC_PCR_CMD_WRITE |
AT91_PMC_PCR_GCKDIV_(best_div) |
AT91_PMC_PCR_GCKEN;
writel(tmp, &pmc->pcr);
while (!(readl(&pmc->sr) & AT91_PMC_GCKRDY))
;
return 0;
}
static struct clk_ops generated_clk_ops = {
.get_rate = generated_clk_get_rate,
.set_rate = generated_clk_set_rate,
};
static int generated_clk_ofdata_to_platdata(struct udevice *dev)
{
struct generated_clk_priv *priv = dev_get_priv(dev);
u32 cells[GENERATED_SOURCE_MAX];
u32 num_parents;
num_parents = fdtdec_get_int_array_count(gd->fdt_blob, dev->of_offset,
"clocks", cells,
GENERATED_SOURCE_MAX);
if (!num_parents)
return -1;
priv->num_parents = num_parents;
return 0;
}
static int generated_clk_bind(struct udevice *dev)
{
return at91_pmc_clk_node_bind(dev);
}
static int generated_clk_probe(struct udevice *dev)
{
return at91_pmc_core_probe(dev);
}
static const struct udevice_id generated_clk_match[] = {
{ .compatible = "atmel,sama5d2-clk-generated" },
{}
};
U_BOOT_DRIVER(generated_clk) = {
.name = "generated-clk",
.id = UCLASS_CLK,
.of_match = generated_clk_match,
.bind = generated_clk_bind,
.probe = generated_clk_probe,
.ofdata_to_platdata = generated_clk_ofdata_to_platdata,
.priv_auto_alloc_size = sizeof(struct generated_clk_priv),
.platdata_auto_alloc_size = sizeof(struct pmc_platdata),
.ops = &generated_clk_ops,
};
/*
* Copyright (C) 2016 Atmel Corporation
* Wenyou.Yang <wenyou.yang@atmel.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <clk-uclass.h>
#include <dm/device.h>
#include <dm/util.h>
#include <linux/io.h>
#include <mach/at91_pmc.h>
#include "pmc.h"
DECLARE_GLOBAL_DATA_PTR;
#define H32MX_MAX_FREQ 90000000
static ulong sama5d4_h32mx_clk_get_rate(struct clk *clk)
{
struct pmc_platdata *plat = dev_get_platdata(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
ulong rate = gd->arch.mck_rate_hz;
if (readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV)
rate /= 2;
if (rate > H32MX_MAX_FREQ)
dm_warn("H32MX clock is too fast\n");
return rate;
}
static struct clk_ops sama5d4_h32mx_clk_ops = {
.get_rate = sama5d4_h32mx_clk_get_rate,
};
static int sama5d4_h32mx_clk_probe(struct udevice *dev)
{
return at91_pmc_core_probe(dev);
}
static const struct udevice_id sama5d4_h32mx_clk_match[] = {
{ .compatible = "atmel,sama5d4-clk-h32mx" },
{}
};
U_BOOT_DRIVER(sama5d4_h32mx_clk) = {
.name = "sama5d4-h32mx-clk",
.id = UCLASS_CLK,
.of_match = sama5d4_h32mx_clk_match,
.probe = sama5d4_h32mx_clk_probe,
.platdata_auto_alloc_size = sizeof(struct pmc_platdata),
.ops = &sama5d4_h32mx_clk_ops,
};
/*
* Copyright (C) 2016 Atmel Corporation
* Wenyou.Yang <wenyou.yang@atmel.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <clk-uclass.h>
#include <dm/device.h>
#include <linux/io.h>
#include <mach/at91_pmc.h>
#include "pmc.h"
DECLARE_GLOBAL_DATA_PTR;
static int main_osc_clk_enable(struct clk *clk)
{
struct pmc_platdata *plat = dev_get_platdata(clk->dev);
struct at91_pmc *pmc = plat->reg_base;
if (readl(&pmc->sr) & AT91_PMC_MOSCSELS)
return 0;
return -EINVAL;
}
static ulong main_osc_clk_get_rate(struct clk *clk)
{
return gd->arch.main_clk_rate_hz;
}
static struct clk_ops main_osc_clk_ops = {
.enable = main_osc_clk_enable,
.get_rate = main_osc_clk_get_rate,
};
static int main_osc_clk_probe(struct udevice *dev)
{