Commit 11d3ede4 authored by Masahiro Yamada's avatar Masahiro Yamada
Browse files

ARM: uniphier: fix warnings reported by aarch64 compiler



The UniPhier SoC family has not supported ARMv8 yet, but these would
cause warnings if they were compiled with a 64bit compiler.  Before
adding the ARMv8 support really, fix them now.

Because UniPhier SoCs do not support Large Physical Address Extension,
casting "phys_addr_t" into "unsigned long" would carry the address
as is.
Signed-off-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
parent fe5ea57b
...@@ -32,7 +32,7 @@ int dram_init(void) ...@@ -32,7 +32,7 @@ int dram_init(void)
gd->ram_size = fdt32_to_cpu(*(val + 1)); gd->ram_size = fdt32_to_cpu(*(val + 1));
debug("DRAM size = %08lx\n", gd->ram_size); debug("DRAM size = %08lx\n", (unsigned long)gd->ram_size);
return 0; return 0;
} }
...@@ -54,6 +54,7 @@ void dram_init_banksize(void) ...@@ -54,6 +54,7 @@ void dram_init_banksize(void)
gd->bd->bi_dram[i].size = fdt32_to_cpu(*val++); gd->bd->bi_dram[i].size = fdt32_to_cpu(*val++);
debug("DRAM bank %d: start = %08lx, size = %08lx\n", debug("DRAM bank %d: start = %08lx, size = %08lx\n",
i, gd->bd->bi_dram[i].start, gd->bd->bi_dram[i].size); i, (unsigned long)gd->bd->bi_dram[i].start,
(unsigned long)gd->bd->bi_dram[i].size);
} }
} }
...@@ -142,7 +142,8 @@ static void detect_num_flash_banks(void) ...@@ -142,7 +142,8 @@ static void detect_num_flash_banks(void)
memory_bank; memory_bank;
debug("flash bank found: base = 0x%lx, size = 0x%lx\n", debug("flash bank found: base = 0x%lx, size = 0x%lx\n",
memory_bank->base, memory_bank->size); (unsigned long)memory_bank->base,
(unsigned long)memory_bank->size);
cfi_flash_num_flash_banks++; cfi_flash_num_flash_banks++;
} }
} }
......
...@@ -105,7 +105,7 @@ static inline void sg_set_pinsel(unsigned pin, unsigned muxval, ...@@ -105,7 +105,7 @@ static inline void sg_set_pinsel(unsigned pin, unsigned muxval,
unsigned mux_bits, unsigned reg_stride) unsigned mux_bits, unsigned reg_stride)
{ {
unsigned shift = pin * mux_bits % 32; unsigned shift = pin * mux_bits % 32;
unsigned reg = SG_PINCTRL_BASE + pin * mux_bits / 32 * reg_stride; unsigned long reg = SG_PINCTRL_BASE + pin * mux_bits / 32 * reg_stride;
u32 mask = (1U << mux_bits) - 1; u32 mask = (1U << mux_bits) - 1;
u32 tmp; u32 tmp;
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment