Commit 11e2b043 authored by Lokesh Vutla's avatar Lokesh Vutla Committed by Tom Rini

ARM: AM57xx: Update EMIF registers

There are certain EMIF timing failures seen on the some x15 boards. Updating
the EMIF settings to get rid of these timing failures.
Reviewed-by: default avatarTom Rini <trini@konsulko.com>
Signed-off-by: default avatarLokesh Vutla <lokeshvutla@ti.com>
parent 2f6ed3b8
......@@ -64,22 +64,22 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
.sdram_config_init = 0x61851b32,
.sdram_config = 0x61851b32,
.sdram_config2 = 0x00000000,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xceef266b,
.sdram_tim2 = 0x328f7fda,
.sdram_tim3 = 0x027f88a8,
.sdram_tim1 = 0xcccf36ab,
.sdram_tim2 = 0x308f7fda,
.sdram_tim3 = 0x409f88a8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190b,
.zq_config = 0x5007190b,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400b,
.emif_ddr_phy_ctlr_1 = 0x0e24400b,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00740074,
.emif_ddr_ext_phy_ctrl_3 = 0x00780078,
.emif_ddr_ext_phy_ctrl_4 = 0x007c007c,
.emif_ddr_ext_phy_ctrl_5 = 0x007b007b,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
.emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
......@@ -89,39 +89,35 @@ static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = {
/* Ext phy ctrl regs 1-35 */
static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
0x10040100,
0x00740074,
0x00780078,
0x007c007c,
0x007b007b,
0x00800080,
0x00360036,
0x00910091,
0x00950095,
0x009B009B,
0x009E009E,
0x00980098,
0x00340034,
0x00360036,
0x00350035,
0x00350035,
0x01ff01ff,
0x01ff01ff,
0x01ff01ff,
0x01ff01ff,
0x01ff01ff,
0x00430043,
0x003e003e,
0x004a004a,
0x00470047,
0x00400040,
0x00340034,
0x00310031,
0x00340034,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x00480048,
0x004A004A,
0x00520052,
0x00550055,
0x00500050,
0x00000000,
0x00600020,
0x40011080,
0x08102040,
0x00400040,
0x00400040,
0x00400040,
0x00400040,
0x00400040,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
......@@ -132,22 +128,22 @@ static const u32 beagle_x15_emif1_ddr3_ext_phy_ctrl_const_regs[] = {
static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
.sdram_config_init = 0x61851b32,
.sdram_config = 0x61851b32,
.sdram_config2 = 0x00000000,
.sdram_config2 = 0x08000000,
.ref_ctrl = 0x000040F1,
.ref_ctrl_final = 0x00001035,
.sdram_tim1 = 0xceef266b,
.sdram_tim2 = 0x328f7fda,
.sdram_tim3 = 0x027f88a8,
.sdram_tim1 = 0xcccf36ab,
.sdram_tim2 = 0x308f7fda,
.sdram_tim3 = 0x409f88a8,
.read_idle_ctrl = 0x00050000,
.zq_config = 0x0007190b,
.zq_config = 0x5007190b,
.temp_alert_config = 0x00000000,
.emif_ddr_phy_ctlr_1_init = 0x0024400b,
.emif_ddr_phy_ctlr_1 = 0x0e24400b,
.emif_ddr_ext_phy_ctrl_1 = 0x10040100,
.emif_ddr_ext_phy_ctrl_2 = 0x00820082,
.emif_ddr_ext_phy_ctrl_3 = 0x008b008b,
.emif_ddr_ext_phy_ctrl_4 = 0x00800080,
.emif_ddr_ext_phy_ctrl_5 = 0x007e007e,
.emif_ddr_ext_phy_ctrl_2 = 0x00910091,
.emif_ddr_ext_phy_ctrl_3 = 0x00950095,
.emif_ddr_ext_phy_ctrl_4 = 0x009b009b,
.emif_ddr_ext_phy_ctrl_5 = 0x009e009e,
.emif_rd_wr_lvl_rmp_win = 0x00000000,
.emif_rd_wr_lvl_rmp_ctl = 0x80000000,
.emif_rd_wr_lvl_ctl = 0x00000000,
......@@ -156,37 +152,35 @@ static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = {
static const u32 beagle_x15_emif2_ddr3_ext_phy_ctrl_const_regs[] = {
0x10040100,
0x00820082,
0x008b008b,
0x00800080,
0x007e007e,
0x00800080,
0x00370037,
0x00390039,
0x00360036,
0x00370037,
0x00910091,
0x00950095,
0x009B009B,
0x009E009E,
0x00980098,
0x00340034,
0x00350035,
0x01ff01ff,
0x01ff01ff,
0x01ff01ff,
0x01ff01ff,
0x01ff01ff,
0x00540054,
0x00540054,
0x004e004e,
0x004c004c,
0x00400040,
0x00340034,
0x00310031,
0x00340034,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x007F007F,
0x00480048,
0x004A004A,
0x00520052,
0x00550055,
0x00500050,
0x00000000,
0x00600020,
0x40011080,
0x08102040,
0x00400040,
0x00400040,
0x00400040,
0x00400040,
0x00400040,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
0x0,
......
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