Commit 16f21704 authored by wdenk's avatar wdenk
Browse files

Initial revision

parent 354bc6fe
/*
* (C) Copyright 2001, 2002
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* (C) Copyright 2002
* Frank Panno <fpanno@delphintech.com>, Delphin Technology AG
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <ioports.h>
#include <mpc8260.h>
#include "ep8260.h"
/*
* I/O Port configuration table
*
* if conf is 1, then that port pin will be configured at boot time
* according to the five values podr/pdir/ppar/psor/pdat for that entry
*/
const iop_conf_t iop_conf_tab[4][32] = {
/* Port A configuration */
{ /* conf ppar psor pdir podr pdat */
/* PA31 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA30 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA29 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA28 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA27 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA26 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA25 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA24 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA23 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA22 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA21 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA20 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA19 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA18 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA17 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA16 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA15 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA14 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA13 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA12 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA11 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA10 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PA9 */ { 0, 1, 0, 1, 0, 0 }, /* */
/* PA8 */ { 0, 1, 0, 0, 0, 0 }, /* */
/* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */
/* PA6 */ { 0, 0, 0, 1, 0, 0 }, /* PA6 */
/* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */
/* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */
/* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */
/* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */
/* PA1 */ { 0, 0, 0, 1, 0, 0 }, /* PA1 */
/* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */
},
/* Port B configuration */
{ /* conf ppar psor pdir podr pdat */
/* PB31 */ { 0, 1, 0, 1, 0, 0 }, /* */
/* PB30 */ { 0, 1, 0, 0, 0, 0 }, /* */
/* PB29 */ { 0, 1, 1, 1, 0, 0 }, /* */
/* PB28 */ { 0, 1, 0, 0, 0, 0 }, /* */
/* PB27 */ { 0, 1, 0, 0, 0, 0 }, /* */
/* PB26 */ { 0, 1, 0, 0, 0, 0 }, /* */
/* PB25 */ { 0, 1, 0, 1, 0, 0 }, /* */
/* PB24 */ { 0, 1, 0, 1, 0, 0 }, /* */
/* PB23 */ { 0, 1, 0, 1, 0, 0 }, /* */
/* PB22 */ { 0, 1, 0, 1, 0, 0 }, /* */
/* PB21 */ { 0, 1, 0, 0, 0, 0 }, /* */
/* PB20 */ { 0, 1, 0, 0, 0, 0 }, /* */
/* PB19 */ { 0, 1, 0, 0, 0, 0 }, /* */
/* PB18 */ { 0, 1, 0, 0, 0, 0 }, /* */
/* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_DV */
/* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RX_ER */
/* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_ER */
/* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TX_EN */
/* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII COL */
/* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CRS */
/* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[3] */
/* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[2] */
/* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[1] */
/* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII RxD[0] */
/* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* PB7 */
/* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[1] */
/* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[2] */
/* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[3] */
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
},
/* Port C */
{ /* conf ppar psor pdir podr pdat */
/* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */
/* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */
/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* */
/* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */
/* PC27 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3 MII TxD[0] */
/* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */
/* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */
/* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */
/* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* */
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* */
/* PC21 */ { 0, 1, 0, 0, 0, 0 }, /* */
/* PC20 */ { 0, 1, 0, 0, 0, 0 }, /* */
/* PC19 */ { 0, 1, 0, 0, 0, 0 }, /* */
/* PC18 */ { 0, 1, 0, 0, 0, 0 }, /* */
/* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CLK15 */
/* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3 MII CLK16 */
/* PC15 */ { 0, 0, 0, 1, 0, 0 }, /* PC15 */
/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* */
/* PC13 */ { 0, 0, 0, 1, 0, 0 }, /* PC13 */
/* PC12 */ { 0, 0, 0, 1, 0, 0 }, /* PC12 */
/* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* PC11 */
/* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PC9 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */
/* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */
/* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */
/* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */
/* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */
/* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */
/* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* */
/* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* */
/* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* */
},
/* Port D */
{ /* conf ppar psor pdir podr pdat */
/* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* */
/* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* */
/* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* */
/* PD28 */ { 0, 0, 0, 1, 0, 0 }, /* PD28 */
/* PD27 */ { 0, 0, 0, 1, 0, 0 }, /* PD27 */
/* PD26 */ { 0, 0, 0, 1, 0, 0 }, /* PD26 */
/* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */
/* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */
/* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */
/* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */
/* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */
/* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */
/* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
/* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* */
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* */
/* PD15 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SDA */
/* PD14 */ { 1, 1, 1, 0, 1, 0 }, /* I2C SCL */
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
/* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
/* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
/* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */
/* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */
/* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */
/* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
}
};
/* ------------------------------------------------------------------------- */
/*
* Setup CS4 to enable the Board Control/Status registers.
* Otherwise the smcs won't work.
*/
int board_pre_init (void)
{
volatile t_ep_regs *regs = (t_ep_regs*)CFG_REGS_BASE;
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
memctl->memc_br4 = CFG_BR4_PRELIM;
memctl->memc_or4 = CFG_OR4_PRELIM;
regs->bcsr1 = 0x62; /* to enable terminal on SMC1 */
regs->bcsr2 = 0x30; /* enable NVRAM and writing FLASH */
return 0;
}
void
reset_phy(void)
{
volatile t_ep_regs *regs = (t_ep_regs*)CFG_REGS_BASE;
regs->bcsr4 = 0xC0;
}
/*
* Check Board Identity:
* I don' know, how the next board revisions will be coded.
* Thats why its a static interpretation ...
*/
int
checkboard(void)
{
volatile t_ep_regs *regs = (t_ep_regs*)CFG_REGS_BASE;
uint major=0, minor=0;
switch (regs->bcsr0) {
case 0x02: major = 1; break;
case 0x03: major = 1; minor = 1; break;
default: break;
}
printf ("Board: Embedded Planet EP8260, Revision %d.%d\n",
major, minor);
return 0;
}
/* ------------------------------------------------------------------------- */
long int
initdram(int board_type)
{
volatile immap_t *immap = (immap_t *)CFG_IMMR;
volatile memctl8260_t *memctl = &immap->im_memctl;
volatile uchar c = 0;
volatile uchar *ramaddr = (uchar *)(CFG_SDRAM_BASE) + 0x110;
/*
ulong psdmr = CFG_PSDMR;
#ifdef CFG_LSDRAM
ulong lsdmr = CFG_LSDMR;
#endif
*/
long size = CFG_SDRAM0_SIZE;
int i;
/*
* Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
*
* "At system reset, initialization software must set up the
* programmable parameters in the memory controller banks registers
* (ORx, BRx, P/LSDMR). After all memory parameters are configured,
* system software should execute the following initialization sequence
* for each SDRAM device.
*
* 1. Issue a PRECHARGE-ALL-BANKS command
* 2. Issue eight CBR REFRESH commands
* 3. Issue a MODE-SET command to initialize the mode register
*
* The initial commands are executed by setting P/LSDMR[OP] and
* accessing the SDRAM with a single-byte transaction."
*
* The appropriate BRx/ORx registers have already been set when we
* get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
*/
memctl->memc_psrt = CFG_PSRT;
memctl->memc_mptpr = CFG_MPTPR;
memctl->memc_psdmr = (ulong) CFG_PSDMR | PSDMR_OP_PREA;
*ramaddr = c;
memctl->memc_psdmr = (ulong) CFG_PSDMR | PSDMR_OP_CBRR;
for (i = 0; i < 8; i++)
*ramaddr = c;
memctl->memc_psdmr = (ulong) CFG_PSDMR | PSDMR_OP_MRW;
*ramaddr = c;
memctl->memc_psdmr = (ulong) CFG_PSDMR | PSDMR_OP_NORM | PSDMR_RFEN;
*ramaddr = c;
#ifndef CFG_RAMBOOT
#ifdef CFG_LSDRAM
size += CFG_SDRAM1_SIZE;
ramaddr = (uchar *)(CFG_SDRAM1_BASE) + 0x8c;
memctl->memc_lsrt = CFG_LSRT;
memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_PREA;
*ramaddr = c;
memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_CBRR;
for (i = 0; i < 8; i++)
*ramaddr = c;
memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_MRW;
*ramaddr = c;
memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_NORM | PSDMR_RFEN;
*ramaddr = c;
#endif /* CFG_LSDRAM */
#endif /* CFG_RAMBOOT */
return (size * 1024 * 1024);
}
/*
* (C) Copyright 2001
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <i2c.h>
#include "eric.h"
#include <asm/processor.h>
#define IBM405GP_GPIO0_OR 0xef600700 /* GPIO Output */
#define IBM405GP_GPIO0_TCR 0xef600704 /* GPIO Three-State Control */
#define IBM405GP_GPIO0_ODR 0xef600718 /* GPIO Open Drain */
#define IBM405GP_GPIO0_IR 0xef60071c /* GPIO Input */
int board_pre_init (void)
{
/*-------------------------------------------------------------------------+
| Interrupt controller setup for the ERIC board.
| Note: IRQ 0-15 405GP internally generated; active high; level sensitive
| IRQ 16 405GP internally generated; active low; level sensitive
| IRQ 17-24 RESERVED
| IRQ 25 (EXT IRQ 0) FLASH; active low; level sensitive
| IRQ 26 (EXT IRQ 1) PHY ; active low; level sensitive
| IRQ 27 (EXT IRQ 2) HOST FAIL, active low; level sensitive
| indicates NO Power or HOST RESET active
| check GPIO7 (HOST RESET#) and GPIO8 (NO Power#)
| for real IRQ source
| IRQ 28 (EXT IRQ 3) HOST; active high; level sensitive
| IRQ 29 (EXT IRQ 4) PCI INTC#; active low; level sensitive
| IRQ 30 (EXT IRQ 5) PCI INTB#; active low; level sensitive
| IRQ 31 (EXT IRQ 6) PCI INTA#; active low; level sensitive
| -> IRQ6 Pin is NOW GPIO23 and can be activateted by setting
| IBM405GP_GPIO0_TCR Bit 0 = 1 (driving the output as defined in IBM405GP_GPIO0_OR,
| else tristate)
| Note for ERIC board:
| An interrupt taken for the HOST (IRQ 28) indicates that
| the HOST wrote a "1" to one of the following locations
| - VGA CRT_GPIO0 (if R1216 is loaded)
| - VGA CRT_GPIO1 (if R1217 is loaded)
|
+-------------------------------------------------------------------------*/
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (uicer, 0x00000000); /* disable all ints */
mtdcr (uiccr, 0x00000000); /* set all SMI to be non-critical */
mtdcr (uicpr, 0xFFFFFF88); /* set int polarities; IRQ3 to 1 */
mtdcr (uictr, 0x10000000); /* set int trigger levels, UART0 is EDGE */
mtdcr (uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority */
mtdcr (uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr (cntrl0, 0x00002000); /* set IRQ6 as GPIO23 to generate an interrupt request to the PCP2PCI bridge */
out32 (IBM405GP_GPIO0_OR, 0x60000000); /*fixme is SMB_INT high or low active??; IRQ6 is GPIO23 output */
out32 (IBM405GP_GPIO0_TCR, 0x7E400000);
return 0;
}
/* ------------------------------------------------------------------------- */
/*
* Check Board Identity:
*/
int checkboard (void)
{
unsigned char *s = getenv ("serial#");
unsigned char *e;
puts ("Board: ");
if (!s || strncmp (s, "ERIC", 9)) {
puts ("### No HW ID - assuming ERIC");
} else {
for (e = s; *e; ++e) {
if (*e == ' ')
break;
}
for (; s < e; ++s) {
putc (*s);
}
}
putc ('\n');
return (0);
}
/* ------------------------------------------------------------------------- */
/* ------------------------------------------------------------------------- */
/* ------------------------------------------------------------------------- */
/*
initdram(int board_type) reads EEPROM via I2c. EEPROM contains all of
the necessary info for SDRAM controller configuration
*/
/* ------------------------------------------------------------------------- */
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
{
#ifndef CONFIG_ERIC
int i;
unsigned char datain[128];
int TotalSize;
#endif
#ifdef CONFIG_ERIC
/*
* we have no EEPROM on ERIC
* so let init.S do the init job for SDRAM
* and simply return 32MByte here
*/
return (CFG_SDRAM_SIZE * 1024 * 1024);
#else
/* Read Serial Presence Detect Information */
for (i = 0; i < 128; i++)
datain[i] = 127;
i2c_send (SPD_EEPROM_ADDRESS, 0, 1, datain, 128);
printf ("\nReading DIMM...\n");
#if 0
for (i = 0; i < 128; i++) {
printf ("%d=0x%x ", i, datain[i]);
if (((i + 1) % 10) == 0)
printf ("\n");
}
printf ("\n");
#endif
/*****************************/
/* Retrieve interesting data */
/*****************************/
/* size of a SDRAM bank */
/* Number of bytes per side / number of banks per side */
if (datain[31] == 0x08)
TotalSize = 32;
else if (datain[31] == 0x10)
TotalSize = 64;
else {
printf ("IIC READ ERROR!!!\n");
TotalSize = 32;
}
/* single-sided DIMM or double-sided DIMM? */
if (datain[5] != 1) {
/* double-sided DIMM => SDRAM banks 0..3 are valid */
printf ("double-sided DIMM\n");
TotalSize *= 2;
}
/* else single-sided DIMM => SDRAM bank 0 and bank 2 are valid */
else {
printf ("single-sided DIMM\n");
}
/* return size in Mb unit => *(1024*1024) */
return (TotalSize * 1024 * 1024);
#endif
}
/* ------------------------------------------------------------------------- */
int testdram (void)
{
/* TODO: XXX XXX XXX */
printf ("test: xxx MB - ok\n");
return (0);
}
/* ------------------------------------------------------------------------- */
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include "adciop.h"
/* ------------------------------------------------------------------------- */
#define _NOT_USED_ 0xFFFFFFFF
/* ------------------------------------------------------------------------- */
int board_pre_init (void)
{
/*
* Set port pin in escc2 to keep living, and configure user led output
*/
*(unsigned char *) 0x2000033e = 0x77; /* ESCC2: PCR bit3=pwr on, bit7=led out */
*(unsigned char *) 0x2000033c = 0x88; /* ESCC2: PVR pwr on, led off */
/*
* Init pci regs
*/
*(unsigned long *) 0x50000304 = 0x02900007; /* enable mem/io/master bits */
*(unsigned long *) 0x500001b4 = 0x00000000; /* disable pci interrupt output enable */
*(unsigned long *) 0x50000354 = 0x00c05800; /* disable emun interrupt output enable */
*(unsigned long *) 0x50000344 = 0x00000000; /* disable pme interrupt output enable */
*(unsigned long *) 0x50000310 = 0x00000000; /* pcibar0 */
*(unsigned long *) 0x50000314 = 0x00000000; /* pcibar1 */
*(unsigned long *) 0x50000318 = 0x00000000; /* pcibar2 */
return 0;
}
/*
* Check Board Identity:
*/
int checkboard (void)
{
unsigned char str[64];
int i = getenv_r ("serial#", str, sizeof (str));
puts ("Board: ");
if (!i || strncmp (str, "ADCIOP", 6)) {
puts ("### No HW ID - assuming ADCIOP\n");
return (1);
}
puts (str);
putc ('\n');
return 0;
}
/* ------------------------------------------------------------------------- */
long int initdram (int board_type)
{
return (16 * 1024 * 1024);
}
/* ------------------------------------------------------------------------- */
int testdram (void)
{
/* TODO: XXX XXX XXX */
printf ("test: 16 MB - ok\n");
return (0);
}
/* ------------------------------------------------------------------------- */