Commit 187af954 authored by Matthias Ludwig's avatar Matthias Ludwig Committed by Wolfgang Denk
Browse files

omap3: embedd gpmc_cs into gpmc config struct

Embedd chip select configuration into struct for gpmc config
instead of having it completely separated as suggested by
Wolfgang Denk on
http://lists.denx.de/pipermail/u-boot/2009-May/052247.html

Signed-off-by: default avatarMatthias Ludwig <mludwig@ultratronik.de>
parent cb32ed1f
......@@ -93,17 +93,17 @@ void set_muxconf_regs(void)
static void setup_net_chip(void)
{
gpio_t *gpio3_base = (gpio_t *)OMAP34XX_GPIO3_BASE;
gpmc_csx_t *gpmc_cs5_base = (gpmc_csx_t *)GPMC_CONFIG_CS5_BASE;
gpmc_t *gpmc = (gpmc_t *)GPMC_BASE;
ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
/* Configure GPMC registers */
writel(NET_GPMC_CONFIG1, &gpmc_cs5_base->config1);
writel(NET_GPMC_CONFIG2, &gpmc_cs5_base->config2);
writel(NET_GPMC_CONFIG3, &gpmc_cs5_base->config3);
writel(NET_GPMC_CONFIG4, &gpmc_cs5_base->config4);
writel(NET_GPMC_CONFIG5, &gpmc_cs5_base->config5);
writel(NET_GPMC_CONFIG6, &gpmc_cs5_base->config6);
writel(NET_GPMC_CONFIG7, &gpmc_cs5_base->config7);
writel(NET_GPMC_CONFIG1, &gpmc->cs[5].config1);
writel(NET_GPMC_CONFIG2, &gpmc->cs[5].config2);
writel(NET_GPMC_CONFIG3, &gpmc->cs[5].config3);
writel(NET_GPMC_CONFIG4, &gpmc->cs[5].config4);
writel(NET_GPMC_CONFIG5, &gpmc->cs[5].config5);
writel(NET_GPMC_CONFIG6, &gpmc->cs[5].config6);
writel(NET_GPMC_CONFIG7, &gpmc->cs[5].config7);
/* Enable off mode for NWE in PADCONF_GPMC_NWE register */
writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
......
......@@ -50,8 +50,8 @@
* The details of the setting of the serial gpmc setup are not available.
* The values were provided by another party.
*/
extern void enable_gpmc_config(u32 *gpmc_config, gpmc_csx_t *gpmc_cs_base,
u32 base, u32 size);
void enable_gpmc_cs_config(u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
u32 size);
static u32 gpmc_serial_TL16CP754C[GPMC_MAX_REG] = {
0x00011000,
......@@ -123,19 +123,15 @@ void zoom2_identify(void)
int board_init (void)
{
DECLARE_GLOBAL_DATA_PTR;
gpmc_csx_t *serial_cs_base;
gpmc_t *gpmc = (gpmc_t *)GPMC_BASE;
u32 *gpmc_config;
gpmc_init (); /* in SRAM or SDRAM, finish GPMC */
/* Configure console support on zoom2 */
gpmc_config = gpmc_serial_TL16CP754C;
serial_cs_base = (gpmc_csx_t *) (GPMC_CONFIG_CS0_BASE +
(3 * GPMC_CONFIG_WIDTH));
enable_gpmc_config(gpmc_config,
serial_cs_base,
SERIAL_TL16CP754C_BASE,
GPMC_SIZE_16M);
enable_gpmc_cs_config(gpmc_config, &gpmc->cs[4],
SERIAL_TL16CP754C_BASE, GPMC_SIZE_16M);
/* board id for Linux */
gd->bd->bi_arch_number = MACH_TYPE_OMAP_ZOOM2;
......
......@@ -51,7 +51,6 @@ static u32 gpmc_m_nand[GPMC_MAX_REG] = {
M_NAND_GPMC_CONFIG6, 0
};
gpmc_csx_t *nand_cs_base;
gpmc_t *gpmc_cfg_base;
#if defined(CONFIG_ENV_IS_IN_NAND)
......@@ -72,8 +71,6 @@ static u32 gpmc_onenand[GPMC_MAX_REG] = {
ONENAND_GPMC_CONFIG6, 0
};
gpmc_csx_t *onenand_cs_base;
#if defined(CONFIG_ENV_IS_IN_ONENAND)
#define GPMC_CS 0
#else
......@@ -195,21 +192,21 @@ void do_sdrc_init(u32 cs, u32 early)
writel(0, &sdrc_base->cs[cs].mcfg);
}
void enable_gpmc_config(u32 *gpmc_config, gpmc_csx_t *gpmc_cs_base, u32 base,
void enable_gpmc_cs_config(u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
u32 size)
{
writel(0, &gpmc_cs_base->config7);
writel(0, &cs->config7);
sdelay(1000);
/* Delay for settling */
writel(gpmc_config[0], &gpmc_cs_base->config1);
writel(gpmc_config[1], &gpmc_cs_base->config2);
writel(gpmc_config[2], &gpmc_cs_base->config3);
writel(gpmc_config[3], &gpmc_cs_base->config4);
writel(gpmc_config[4], &gpmc_cs_base->config5);
writel(gpmc_config[5], &gpmc_cs_base->config6);
writel(gpmc_config[0], &cs->config1);
writel(gpmc_config[1], &cs->config2);
writel(gpmc_config[2], &cs->config3);
writel(gpmc_config[3], &cs->config4);
writel(gpmc_config[4], &cs->config5);
writel(gpmc_config[5], &cs->config6);
/* Enable the config */
writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
(1 << 6)), &gpmc_cs_base->config7);
(1 << 6)), &cs->config7);
sdelay(2000);
}
......@@ -223,7 +220,6 @@ void gpmc_init(void)
/* putting a blanket check on GPMC based on ZeBu for now */
u32 *gpmc_config = NULL;
gpmc_t *gpmc_base = (gpmc_t *)GPMC_BASE;
gpmc_csx_t *gpmc_cs_base = (gpmc_csx_t *)GPMC_CONFIG_CS0_BASE;
u32 base = 0;
u32 size = 0;
u32 f_off = CONFIG_SYS_MONITOR_LEN;
......@@ -242,17 +238,16 @@ void gpmc_init(void)
* Disable the GPMC0 config set by ROM code
* It conflicts with our MPDB (both at 0x08000000)
*/
writel(0, &gpmc_cs_base->config7);
writel(0, &gpmc_base->cs[0].config7);
sdelay(1000);
#if defined(CONFIG_CMD_NAND) /* CS 0 */
gpmc_config = gpmc_m_nand;
gpmc_cfg_base = gpmc_base;
nand_cs_base = (gpmc_csx_t *)(GPMC_CONFIG_CS0_BASE +
(GPMC_CS * GPMC_CONFIG_WIDTH));
base = PISMO1_NAND_BASE;
size = PISMO1_NAND_SIZE;
enable_gpmc_config(gpmc_config, nand_cs_base, base, size);
enable_gpmc_cs_config(gpmc_config, &gpmc_base->cs[0], base, size);
#if defined(CONFIG_ENV_IS_IN_NAND)
f_off = SMNAND_ENV_OFFSET;
f_sec = SZ_128K;
......@@ -266,11 +261,9 @@ void gpmc_init(void)
#if defined(CONFIG_CMD_ONENAND)
gpmc_config = gpmc_onenand;
onenand_cs_base = (gpmc_csx_t *)(GPMC_CONFIG_CS0_BASE +
(GPMC_CS * GPMC_CONFIG_WIDTH));
base = PISMO1_ONEN_BASE;
size = PISMO1_ONEN_SIZE;
enable_gpmc_config(gpmc_config, onenand_cs_base, base, size);
enable_gpmc_cs_config(gpmc_config, &gpmc_base->cs[0], base, size);
#if defined(CONFIG_ENV_IS_IN_ONENAND)
f_off = ONENAND_ENV_OFFSET;
f_sec = SZ_128K;
......
......@@ -32,7 +32,7 @@
#include <i2c.h>
extern omap3_sysinfo sysinfo;
static gpmc_csx_t *gpmc_cs_base = (gpmc_csx_t *)GPMC_CONFIG_CS0_BASE;
static gpmc_t *gpmc_base = (gpmc_t *)GPMC_BASE;
static sdrc_t *sdrc_base = (sdrc_t *)OMAP34XX_SDRC_BASE;
static ctrl_t *ctrl_base = (ctrl_t *)OMAP34XX_CTRL_BASE;
static char *rev_s[CPU_3XX_MAX_REV] = {
......@@ -160,7 +160,7 @@ u32 get_gpmc0_base(void)
{
u32 b;
b = readl(&gpmc_cs_base->config7);
b = readl(&gpmc_base->cs[0].config7);
b &= 0x1F; /* keep base [5:0] */
b = b << 24; /* ret 0x0b000000 */
return b;
......
......@@ -31,7 +31,6 @@
static uint8_t cs;
static gpmc_t *gpmc_base = (gpmc_t *)GPMC_BASE;
static gpmc_csx_t *gpmc_cs_base;
static struct nand_ecclayout hw_nand_oob = GPMC_NAND_HW_ECC_LAYOUT;
/*
......@@ -49,13 +48,13 @@ static void omap_nand_hwcontrol(struct mtd_info *mtd, int32_t cmd,
*/
switch (ctrl) {
case NAND_CTRL_CHANGE | NAND_CTRL_CLE:
this->IO_ADDR_W = (void __iomem *)&gpmc_cs_base->nand_cmd;
this->IO_ADDR_W = (void __iomem *)&gpmc_base->cs[cs].nand_cmd;
break;
case NAND_CTRL_CHANGE | NAND_CTRL_ALE:
this->IO_ADDR_W = (void __iomem *)&gpmc_cs_base->nand_adr;
this->IO_ADDR_W = (void __iomem *)&gpmc_base->cs[cs].nand_adr;
break;
case NAND_CTRL_CHANGE | NAND_NCE:
this->IO_ADDR_W = (void __iomem *)&gpmc_cs_base->nand_dat;
this->IO_ADDR_W = (void __iomem *)&gpmc_base->cs[cs].nand_dat;
break;
}
......@@ -311,15 +310,8 @@ int board_nand_init(struct nand_chip *nand)
* devices.
*/
while (cs < GPMC_MAX_CS) {
/*
* Each GPMC set for a single CS is at offset 0x30
* - already remapped for us
*/
gpmc_cs_base = (gpmc_csx_t *)(GPMC_CONFIG_CS0_BASE +
(cs * GPMC_CONFIG_WIDTH));
/* Check if NAND type is set */
if ((readl(&gpmc_cs_base->config1) & 0xC00) ==
0x800) {
if ((readl(&gpmc_base->cs[cs].config1) & 0xC00) == 0x800) {
/* Found it!! */
break;
}
......@@ -336,13 +328,13 @@ int board_nand_init(struct nand_chip *nand)
gpmc_config |= 0x10;
writel(gpmc_config, &gpmc_base->config);
nand->IO_ADDR_R = (void __iomem *)&gpmc_cs_base->nand_dat;
nand->IO_ADDR_W = (void __iomem *)&gpmc_cs_base->nand_cmd;
nand->IO_ADDR_R = (void __iomem *)&gpmc_base->cs[cs].nand_dat;
nand->IO_ADDR_W = (void __iomem *)&gpmc_base->cs[cs].nand_cmd;
nand->cmd_ctrl = omap_nand_hwcontrol;
nand->options = NAND_NO_PADDING | NAND_CACHEPRG | NAND_NO_AUTOINCR;
/* If we are 16 bit dev, our gpmc config tells us that */
if ((readl(gpmc_cs_base) & 0x3000) == 0x1000)
if ((readl(&gpmc_base->cs[cs].config1) & 0x3000) == 0x1000)
nand->options |= NAND_BUSWIDTH_16;
nand->chip_delay = 100;
......
......@@ -81,30 +81,38 @@ typedef struct ctrl_id {
#define HS_DEVICE 0x2
#define GP_DEVICE 0x3
/* GPMC CS3/cs4/cs6 not avaliable */
#define GPMC_BASE (OMAP34XX_GPMC_BASE)
#define GPMC_CONFIG_CS0 0x60
#define GPMC_CONFIG_CS5 0x150
#define GPMC_CONFIG_CS0_BASE (GPMC_BASE + GPMC_CONFIG_CS0)
#define GPMC_CONFIG_CS5_BASE (GPMC_BASE + GPMC_CONFIG_CS5)
#define GPMC_CONFIG_WP 0x10
#define GPMC_CONFIG_WIDTH 0x30
#ifndef __ASSEMBLY__
struct gpmc_cs {
unsigned int config1; /* 0x00 */
unsigned int config2; /* 0x04 */
unsigned int config3; /* 0x08 */
unsigned int config4; /* 0x0C */
unsigned int config5; /* 0x10 */
unsigned int config6; /* 0x14 */
unsigned int config7; /* 0x18 */
unsigned int nand_cmd; /* 0x1C */
unsigned int nand_adr; /* 0x20 */
unsigned int nand_dat; /* 0x24 */
unsigned char res[8]; /* blow up to 0x30 byte */
};
typedef struct gpmc {
unsigned char res1[0x10];
unsigned int sysconfig; /* 0x10 */
unsigned char res2[0x4];
unsigned int irqstatus; /* 0x18 */
unsigned int irqenable; /* 0x1C */
unsigned int irqenable; /* 0x1C */
unsigned char res3[0x20];
unsigned int timeout_control; /* 0x40 */
unsigned char res4[0xC];
unsigned int config; /* 0x50 */
unsigned int status; /* 0x54 */
unsigned char res5[0x19C];
unsigned char res5[0x8];
struct gpmc_cs cs[8]; /* 0x60, 0x90, .. */
unsigned char res6[0x18];
unsigned int ecc_config; /* 0x1F4 */
unsigned int ecc_control; /* 0x1F8 */
unsigned int ecc_size_config; /* 0x1FC */
......@@ -118,19 +126,6 @@ typedef struct gpmc {
unsigned int ecc8_result; /* 0x21C */
unsigned int ecc9_result; /* 0x220 */
} gpmc_t;
typedef struct gpmc_csx {
unsigned int config1; /* 0x00 */
unsigned int config2; /* 0x04 */
unsigned int config3; /* 0x08 */
unsigned int config4; /* 0x0C */
unsigned int config5; /* 0x10 */
unsigned int config6; /* 0x14 */
unsigned int config7; /* 0x18 */
unsigned int nand_cmd; /* 0x1C */
unsigned int nand_adr; /* 0x20 */
unsigned int nand_dat; /* 0x24 */
} gpmc_csx_t;
#else /* __ASSEMBLY__ */
#define GPMC_CONFIG1 0x00
#define GPMC_CONFIG2 0x04
......
......@@ -300,7 +300,6 @@
#define CONFIG_SYS_JFFS2_NUM_BANKS 1
#ifndef __ASSEMBLY__
extern gpmc_csx_t *nand_cs_base;
extern gpmc_t *gpmc_cfg_base;
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
......
......@@ -292,7 +292,6 @@
#define CONFIG_SYS_JFFS2_NUM_BANKS 1
#ifndef __ASSEMBLY__
extern gpmc_csx_t *nand_cs_base;
extern gpmc_t *gpmc_cfg_base;
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
......
......@@ -285,7 +285,6 @@
#define CONFIG_SYS_JFFS2_NUM_BANKS 1
#ifndef __ASSEMBLY__
extern gpmc_csx_t *nand_cs_base;
extern gpmc_t *gpmc_cfg_base;
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
......
......@@ -289,7 +289,6 @@
#define CONFIG_SYS_JFFS2_NUM_BANKS 1
#ifndef __ASSEMBLY__
extern gpmc_csx_t *nand_cs_base;
extern gpmc_t *gpmc_cfg_base;
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
......
......@@ -297,7 +297,6 @@
#define CONFIG_SYS_JFFS2_NUM_BANKS 1
#ifndef __ASSEMBLY__
extern gpmc_csx_t *nand_cs_base;
extern gpmc_t *gpmc_cfg_base;
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
......
......@@ -252,7 +252,6 @@
#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
#ifndef __ASSEMBLY__
extern gpmc_csx_t *nand_cs_base;
extern gpmc_t *gpmc_cfg_base;
extern unsigned int boot_flash_base;
extern volatile unsigned int boot_flash_env_addr;
......
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