Commit 1aeed8d7 authored by Wolfgang Denk's avatar Wolfgang Denk
Browse files

Coding Style cleanup; update CHANGELOG



Signed-off-by: default avatarWolfgang Denk <wd@denx.de>
parent 8c8428a5
This diff is collapsed.
......@@ -29,4 +29,3 @@
#
TEXT_BASE = 0x8FFC0000
......@@ -42,7 +42,6 @@
.align 2
lowlevel_init:
mov.l CCR_A, r1 ! Address of Cache Control Register
mov.l CCR_D, r0 ! Instruction Cache Invalidate
mov.l r0, @r1
......@@ -100,7 +99,6 @@ lowlevel_init:
mov.l r0, @r1
bsc_init:
mov.l CMNCR_A, r1 ! CMNCR address -> R1
mov.l CMNCR_D, r0 ! CMNCR data -> R0
mov.l r0, @r1 ! CMNCR set
......@@ -188,8 +186,6 @@ bsc_init:
rts
mov #0, r0
.align 4
CCR_A: .long CCR
......@@ -266,4 +262,3 @@ PSCR_D: .word 0x0000
RWTCSR_D_1: .word 0xA507
RWTCSR_D_2: .word 0xA504 ! 20080115
RWTCNT_D: .word 0x5A00
......@@ -51,4 +51,3 @@ int dram_init (void)
void led_set_state (unsigned short value)
{
}
......@@ -103,4 +103,3 @@ SECTIONS
PROVIDE (_end = .);
}
......@@ -50,11 +50,11 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
}
} else {
if (info->iobase == CFG_FEC0_IOBASE) {
gpio->par_feci2c &= ~0x0F00;
gpio->par_fec0hl &= ~0xC0;
gpio->par_feci2c &= ~0x0F00;
gpio->par_fec0hl &= ~0xC0;
} else {
gpio->par_feci2c &= ~0x00A0;
gpio->par_fec1hl &= ~0xC0;
gpio->par_feci2c &= ~0x00A0;
gpio->par_fec1hl &= ~0xC0;
}
}
......
......@@ -67,7 +67,7 @@ int board_init(void)
/* set Pin Select Register D: Reserved, SIOF1_TxD, Reserved, SIOF1_MCLK, Reserved, SIOF1_SYNC, Reserved, SCIF1_SCK, Reserved */
__raw_writew(0x0000, PSELD); /* 0 00 00 00 00 00 00 00 0 */
/* OTH: (00) Other fuction
* GPO: (01) General Purpose Output
* GPI: (11) General Purpose Input
......@@ -159,4 +159,3 @@ int dram_init(void)
printf("SDRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
return 0;
}
......@@ -7,7 +7,7 @@
*
* Copyright (C) 2008
* Mark Jonas <mark.jonas@de.bosch.com>
*
*
* See file CREDITS for list of people who contributed to this
* project.
*
......
......@@ -33,11 +33,11 @@ DECLARE_GLOBAL_DATA_PTR;
/* We put these variables into .data section so that they are zero
* when entering the AMBA Plug & Play routines (in cpu/cpu/ambapp.c)
* the first time. BSS is not garantueed to be zero since BSS
* the first time. BSS is not garantueed to be zero since BSS
* hasn't been cleared the first times entering the CPU AMBA functions.
*
* The AMBA PnP routines call these functions if ambapp_???_print is set.
*
*
*/
int ambapp_apb_print __attribute__ ((section(".data"))) = 0;
int ambapp_ahb_print __attribute__ ((section(".data"))) = 0;
......
......@@ -199,7 +199,7 @@ int usb_stor_info(void)
}
return 0;
}
printf("No storage devices, perhaps not 'usb start'ed..?\n");
return 1;
}
......
......@@ -118,7 +118,7 @@ _trap_table:
TRAPI(13); ! 1d IRQ level 13
TRAPI(14); ! 1e IRQ level 14
TRAP(_nmi_trap); ! 1f IRQ level 15 /
! NMI (non maskable interrupt)
! NMI (non maskable interrupt)
BAD_TRAP; ! 20 r_register_access_error
BAD_TRAP; ! 21 instruction access error
BAD_TRAP; ! 22
......@@ -213,9 +213,9 @@ _hardreset:
nop
/* Init Cache */
set (LEON2_PREGS+LEON_REG_CACHECTRL_OFFSET), %g1
set 0x0081000f, %g2
st %g2, [%g1]
set (LEON2_PREGS+LEON_REG_CACHECTRL_OFFSET), %g1
set 0x0081000f, %g2
st %g2, [%g1]
mov %g0, %y
clr %g1
......@@ -584,7 +584,7 @@ trap_setup:
or %t_wim, %g2, %g2
and %g2, 0xff, %g2
save %g0, %g0, %g0 ! get in window to be saved
save %g0, %g0, %g0 ! get in window to be saved
/* Set new %wim value */
wr %g2, 0x0, %wim
......
......@@ -359,8 +359,8 @@ prom_relocate_loop:
nop
nop
nop
/* If CACHE snooping is available in hardware the
/* If CACHE snooping is available in hardware the
* variable leon3_snooping_avail will be set to
* 0x800000 else 0.
*/
......
......@@ -67,11 +67,13 @@ int get_clocks (void)
#if defined(CONFIG_M5275)
volatile pll_t *pll = (volatile pll_t *)(MMAP_PLL);
/* Setup PLL */
pll->syncr = 0x01080000;
while (!(pll->synsr & FMPLL_SYNSR_LOCK));
pll->syncr = 0x01000000;
while (!(pll->synsr & FMPLL_SYNSR_LOCK));
/* Setup PLL */
pll->syncr = 0x01080000;
while (!(pll->synsr & FMPLL_SYNSR_LOCK)
;
pll->syncr = 0x01000000;
while (!(pll->synsr & FMPLL_SYNSR_LOCK))
;
#endif
gd->cpu_clk = CFG_CLK;
......
......@@ -21,7 +21,7 @@ tested on both gig copper and gig fiber boards
You should have received a copy of the GNU General Public License along with
this program; if not, write to the Free Software Foundation, Inc., 59
Temple Place - Suite 330, Boston, MA 02111-1307, USA.
Temple Place - Suite 330, Boston, MA 02111-1307, USA.
The full GNU General Public License is included in this distribution in the
file called LICENSE.
......@@ -52,7 +52,7 @@ tested on both gig copper and gig fiber boards
#undef virt_to_bus
#define virt_to_bus(x) ((unsigned long)x)
#define bus_to_phys(devno, a) pci_mem_to_phys(devno, a)
#define mdelay(n) udelay((n)*1000)
#define mdelay(n) udelay((n)*1000)
#define E1000_DEFAULT_PBA 0x00000030
......@@ -646,8 +646,8 @@ e1000_set_mac_type(struct e1000_hw *hw)
hw->mac_type = e1000_82546;
break;
case E1000_DEV_ID_82541ER:
hw->mac_type = e1000_82541_rev_2;
break;
hw->mac_type = e1000_82541_rev_2;
break;
default:
/* Should never have loaded on this device */
return -E1000_ERR_MAC_TYPE;
......@@ -1061,12 +1061,12 @@ e1000_setup_fiber_link(struct eth_device *nic)
* configure the two flow control enable bits in the CTRL register.
*
* The possible values of the "fc" parameter are:
* 0: Flow control is completely disabled
* 1: Rx flow control is enabled (we can receive pause frames, but
* not send pause frames).
* 2: Tx flow control is enabled (we can send pause frames but we do
* not support receiving pause frames).
* 3: Both Rx and TX flow control (symmetric) are enabled.
* 0: Flow control is completely disabled
* 1: Rx flow control is enabled (we can receive pause frames, but
* not send pause frames).
* 2: Tx flow control is enabled (we can send pause frames but we do
* not support receiving pause frames).
* 3: Both Rx and TX flow control (symmetric) are enabled.
*/
switch (hw->fc) {
case e1000_fc_none:
......@@ -1229,7 +1229,7 @@ e1000_setup_copper_link(struct eth_device *nic)
#if 0
/* Options:
* disable_polarity_correction = 0 (default)
* Automatic Correction for Reversed Cable Polarity
* Automatic Correction for Reversed Cable Polarity
* 0 - Disabled
* 1 - Enabled
*/
......@@ -1271,14 +1271,14 @@ e1000_setup_copper_link(struct eth_device *nic)
/* Options:
* autoneg = 1 (default)
* PHY will advertise value(s) parsed from
* autoneg_advertised and fc
* PHY will advertise value(s) parsed from
* autoneg_advertised and fc
* autoneg = 0
* PHY will be set to 10H, 10F, 100H, or 100F
* depending on value parsed from forced_speed_duplex.
* PHY will be set to 10H, 10F, 100H, or 100F
* depending on value parsed from forced_speed_duplex.
*/
/* Is autoneg enabled? This is enabled by default or by software override.
/* Is autoneg enabled? This is enabled by default or by software override.
* If so, call e1000_phy_setup_autoneg routine to parse the
* autoneg_advertised and fc options. If autoneg is NOT enabled, then the
* user should have provided a speed/duplex override. If so, then call
......@@ -1353,11 +1353,11 @@ e1000_setup_copper_link(struct eth_device *nic)
if (phy_data & MII_SR_LINK_STATUS) {
/* We have link, so we need to finish the config process:
* 1) Set up the MAC to the current PHY speed/duplex
* if we are on 82543. If we
* are on newer silicon, we only need to configure
* collision distance in the Transmit Control Register.
* if we are on 82543. If we
* are on newer silicon, we only need to configure
* collision distance in the Transmit Control Register.
* 2) Set up flow control on the MAC to that established with
* the link partner.
* the link partner.
*/
if (hw->mac_type >= e1000_82544) {
e1000_config_collision_dist(hw);
......@@ -1418,7 +1418,7 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
/* First we clear all the 10/100 mb speed bits in the Auto-Neg
* Advertisement Register (Address 4) and the 1000 mb speed bits in
* the 1000Base-T Control Register (Address 9).
* the 1000Base-T Control Register (Address 9).
*/
mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
......@@ -1468,14 +1468,14 @@ e1000_phy_setup_autoneg(struct e1000_hw *hw)
* Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
*
* The possible values of the "fc" parameter are:
* 0: Flow control is completely disabled
* 1: Rx flow control is enabled (we can receive pause frames
* but not send pause frames).
* 2: Tx flow control is enabled (we can send pause frames
* but we do not support receiving pause frames).
* 3: Both Rx and TX flow control (symmetric) are enabled.
* 0: Flow control is completely disabled
* 1: Rx flow control is enabled (we can receive pause frames
* but not send pause frames).
* 2: Tx flow control is enabled (we can send pause frames
* but we do not support receiving pause frames).
* 3: Both Rx and TX flow control (symmetric) are enabled.
* other: No software override. The flow control configuration
* in the EEPROM is used.
* in the EEPROM is used.
*/
switch (hw->fc) {
case e1000_fc_none: /* 0 */
......@@ -1630,12 +1630,12 @@ e1000_force_mac_fc(struct e1000_hw *hw)
* according to the "hw->fc" parameter.
*
* The possible values of the "fc" parameter are:
* 0: Flow control is completely disabled
* 1: Rx flow control is enabled (we can receive pause
* frames but not send pause frames).
* 2: Tx flow control is enabled (we can send pause frames
* frames but we do not receive pause frames).
* 3: Both Rx and TX flow control (symmetric) is enabled.
* 0: Flow control is completely disabled
* 1: Rx flow control is enabled (we can receive pause
* frames but not send pause frames).
* 2: Tx flow control is enabled (we can send pause frames
* frames but we do not receive pause frames).
* 3: Both Rx and TX flow control (symmetric) is enabled.
* other: No other values should be possible at this point.
*/
......@@ -1752,14 +1752,14 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
* LOCAL DEVICE | LINK PARTNER
* PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
*-------|---------|-------|---------|--------------------
* 0 | 0 | DC | DC | e1000_fc_none
* 0 | 1 | 0 | DC | e1000_fc_none
* 0 | 1 | 1 | 0 | e1000_fc_none
* 0 | 1 | 1 | 1 | e1000_fc_tx_pause
* 1 | 0 | 0 | DC | e1000_fc_none
* 1 | DC | 1 | DC | e1000_fc_full
* 1 | 1 | 0 | 0 | e1000_fc_none
* 1 | 1 | 0 | 1 | e1000_fc_rx_pause
* 0 | 0 | DC | DC | e1000_fc_none
* 0 | 1 | 0 | DC | e1000_fc_none
* 0 | 1 | 1 | 0 | e1000_fc_none
* 0 | 1 | 1 | 1 | e1000_fc_tx_pause
* 1 | 0 | 0 | DC | e1000_fc_none
* 1 | DC | 1 | DC | e1000_fc_full
* 1 | 1 | 0 | 0 | e1000_fc_none
* 1 | 1 | 0 | 1 | e1000_fc_rx_pause
*
*/
/* Are both PAUSE bits set to 1? If so, this implies
......@@ -1771,7 +1771,7 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
* LOCAL DEVICE | LINK PARTNER
* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
*-------|---------|-------|---------|--------------------
* 1 | DC | 1 | DC | e1000_fc_full
* 1 | DC | 1 | DC | e1000_fc_full
*
*/
if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
......@@ -1796,7 +1796,7 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
* LOCAL DEVICE | LINK PARTNER
* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
*-------|---------|-------|---------|--------------------
* 0 | 1 | 1 | 1 | e1000_fc_tx_pause
* 0 | 1 | 1 | 1 | e1000_fc_tx_pause
*
*/
else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
......@@ -1813,7 +1813,7 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
* LOCAL DEVICE | LINK PARTNER
* PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
*-------|---------|-------|---------|--------------------
* 1 | 1 | 0 | 1 | e1000_fc_rx_pause
* 1 | 1 | 0 | 1 | e1000_fc_rx_pause
*
*/
else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
......@@ -1855,7 +1855,7 @@ e1000_config_fc_after_link_up(struct e1000_hw *hw)
("Flow Control = RX PAUSE frames only.\r\n");
}
/* Now we need to do one last check... If we auto-
/* Now we need to do one last check... If we auto-
* negotiated to HALF DUPLEX, flow control should not be
* enabled per IEEE 802.3 spec.
*/
......@@ -1919,7 +1919,7 @@ e1000_check_for_link(struct eth_device *nic)
/* If we have a copper PHY then we only want to go out to the PHY
* registers to see if Auto-Neg has completed and/or if our link
* status has changed. The get_link_status flag will be set if we
* status has changed. The get_link_status flag will be set if we
* receive a Link Status Change interrupt or we have Rx Sequence
* Errors.
*/
......@@ -1976,7 +1976,7 @@ e1000_check_for_link(struct eth_device *nic)
/* At this point we know that we are on copper and we have
* auto-negotiated link. These are conditions for checking the link
* parter capability register. We use the link partner capability to
* parter capability register. We use the link partner capability to
* determine if TBI Compatibility needs to be turned on or off. If
* the link partner advertises any speed in addition to Gigabit, then
* we assume that they are GMII-based, and TBI compatibility is not
......@@ -2494,34 +2494,33 @@ e1000_phy_reset(struct e1000_hw *hw)
return 0;
}
static int
e1000_set_phy_type(struct e1000_hw *hw)
static int e1000_set_phy_type (struct e1000_hw *hw)
{
DEBUGFUNC();
if(hw->mac_type == e1000_undefined)
return -E1000_ERR_PHY_TYPE;
switch(hw->phy_id) {
case M88E1000_E_PHY_ID:
case M88E1000_I_PHY_ID:
case M88E1011_I_PHY_ID:
hw->phy_type = e1000_phy_m88;
break;
case IGP01E1000_I_PHY_ID:
if(hw->mac_type == e1000_82541 ||
hw->mac_type == e1000_82541_rev_2) {
hw->phy_type = e1000_phy_igp;
break;
}
/* Fall Through */
default:
/* Should never have loaded on this device */
hw->phy_type = e1000_phy_undefined;
return -E1000_ERR_PHY_TYPE;
}
return E1000_SUCCESS;
DEBUGFUNC ();
if (hw->mac_type == e1000_undefined)
return -E1000_ERR_PHY_TYPE;
switch (hw->phy_id) {
case M88E1000_E_PHY_ID:
case M88E1000_I_PHY_ID:
case M88E1011_I_PHY_ID:
hw->phy_type = e1000_phy_m88;
break;
case IGP01E1000_I_PHY_ID:
if (hw->mac_type == e1000_82541 ||
hw->mac_type == e1000_82541_rev_2) {
hw->phy_type = e1000_phy_igp;
break;
}
/* Fall Through */
default:
/* Should never have loaded on this device */
hw->phy_type = e1000_phy_undefined;
return -E1000_ERR_PHY_TYPE;
}
return E1000_SUCCESS;
}
/******************************************************************************
......@@ -2825,8 +2824,8 @@ e1000_configure_rx(struct e1000_hw *hw)
#endif
/* Set the interrupt throttling rate. Value is calculated
* as DEFAULT_ITR = 1/(MAX_INTS_PER_SEC * 256ns) */
#define MAX_INTS_PER_SEC 8000
#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
#define MAX_INTS_PER_SEC 8000
#define DEFAULT_ITR 1000000000/(MAX_INTS_PER_SEC * 256)
E1000_WRITE_REG(hw, ITR, DEFAULT_ITR);
}
......
......@@ -41,7 +41,7 @@
/* Max devices this software will support */
#define LEON3_AHB_MASTERS 16
#define LEON3_AHB_SLAVES 16
/*#define LEON3_APB_MASTERS 1*//* Number of APB buses that has Plug&Play */
/*#define LEON3_APB_MASTERS 1*/ /* Number of APB buses that has Plug&Play */
#define LEON3_APB_SLAVES 16 /* Total number of APB slaves per APB bus */
/* Vendor codes */
......
......@@ -57,7 +57,7 @@ typedef struct ccsr_local_ecm {
uint lawbar7; /* 0xce8 - Local Access Window 7 Base Address Register */
char res19[4];
uint lawar7; /* 0xcf0 - Local Access Window 7 Attributes Register */
char res20[780]; // XXX: LAW 8, LAW9 for 8572
char res20[780]; /* XXX: LAW 8, LAW9 for 8572 */
uint eebacr; /* 0x1000 - ECM CCB Address Configuration Register */
char res21[12];
uint eebpcr; /* 0x1010 - ECM CCB Port Configuration Register */
......
This diff is collapsed.
......@@ -7,28 +7,26 @@
struct __large_struct { unsigned long buf[100]; };
#define __m(x) (*(struct __large_struct *)(x))
void dcache_wback_range(u32 start, u32 end)
void dcache_wback_range (u32 start, u32 end)
{
u32 v;
u32 v;
start &= ~(L1_CACHE_BYTES-1);
for (v = start; v < end; v+=L1_CACHE_BYTES) {
asm volatile("ocbwb %0"
: /* no output */
: "m" (__m(v)));
}
start &= ~(L1_CACHE_BYTES - 1);
for (v = start; v < end; v += L1_CACHE_BYTES) {
asm volatile ("ocbwb %0": /* no output */
:"m" (__m (v)));
}
}
void dcache_invalid_range(u32 start, u32 end)
void dcache_invalid_range (u32 start, u32 end)
{
u32 v;
u32 v;
start &= ~(L1_CACHE_BYTES-1);
for (v = start; v < end; v+=L1_CACHE_BYTES) {
asm volatile("ocbi %0"
: /* no output */
: "m" (__m(v)));
}
start &= ~(L1_CACHE_BYTES - 1);
for (v = start; v < end; v += L1_CACHE_BYTES) {
asm volatile ("ocbi %0": /* no output */
:"m" (__m (v)));
}
}
#endif /* CONFIG_SH4 || CONFIG_SH4A */
......
......@@ -28,10 +28,9 @@
#error Include LEON3 header file only if LEON3 processor
#endif
/* Not much to define, most is Plug and Play and GRLIB dependent
* not LEON3 dependent. See <ambapp.h> for GRLIB timers, interrupt
/* Not much to define, most is Plug and Play and GRLIB dependent
* not LEON3 dependent. See <ambapp.h> for GRLIB timers, interrupt
* ctrl, memory controllers etc.
*/
#endif
......@@ -313,8 +313,8 @@
/*** LEON2 UART 1 ***/
#define CFG_LEON2_UART1_SCALER \
((((CONFIG_SYS_CLK_FREQ*10)/(CONFIG_BAUDRATE*8))-5)/10)
((((CONFIG_SYS_CLK_FREQ*10)/(CONFIG_BAUDRATE*8))-5)/10)
/* UART1 Define to 1 or 0 */
#define LEON2_UART1_LOOPBACK_ENABLE 0
#define LEON2_UART1_FLOWCTRL_ENABLE 0
......@@ -324,7 +324,7 @@
/*** LEON2 UART 2 ***/
#define CFG_LEON2_UART2_SCALER \
((((CONFIG_SYS_CLK_FREQ*10)/(CONFIG_BAUDRATE*8))-5)/10)
((((CONFIG_SYS_CLK_FREQ*10)/(CONFIG_BAUDRATE*8))-5)/10)
/* UART2 Define to 1 or 0 */
#define LEON2_UART2_LOOPBACK_ENABLE 0
......
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