Commit 1ba62f10 authored by York Sun's avatar York Sun Committed by Andy Fleming
Browse files

powerpc/mpc8xxx: Fix CONFIG_DDR_RAW_TIMING for two boards



P1010RDB and p1_pc_rdb_pc has incorrect configuration for
CONFIG_DDR_RAW_TIMING. It should be CONFIG_SYS_DDR_RAW_TIMING.
Incorrect setting causes DDR failure in case of SPD absent.
Signed-off-by: default avatarYork Sun <yorksun@freescale.com>
Signed-off-by: default avatarAndy Fleming <afleming@freescale.com>
parent 119a55f9
......@@ -31,7 +31,7 @@
DECLARE_GLOBAL_DATA_PTR;
#ifndef CONFIG_DDR_RAW_TIMING
#ifndef CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_SYS_DRAM_SIZE 1024
fsl_ddr_cfg_regs_t ddr_cfg_regs_800 = {
......@@ -165,7 +165,7 @@ phys_size_t fixed_sdram(void)
return ddr_size;
}
#else /* CONFIG_DDR_RAW_TIMING */
#else /* CONFIG_SYS_DDR_RAW_TIMING */
/*
* Samsung K4B2G0846C-HCF8
* The following timing are for "downshift"
......@@ -247,4 +247,4 @@ void fsl_ddr_board_options(memctl_options_t *popts,
}
}
#endif /* CONFIG_DDR_RAW_TIMING */
#endif /* CONFIG_SYS_DDR_RAW_TIMING */
......@@ -15,7 +15,7 @@
#include <asm/io.h>
#include <asm/fsl_law.h>
#ifdef CONFIG_DDR_RAW_TIMING
#ifdef CONFIG_SYS_DDR_RAW_TIMING
#if defined(CONFIG_P1020RDB_PROTO) || \
defined(CONFIG_P1021RDB) || \
defined(CONFIG_P1020UTM)
......@@ -204,7 +204,7 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
return 0;
}
#endif /* CONFIG_DDR_RAW_TIMING */
#endif /* CONFIG_SYS_DDR_RAW_TIMING */
/* Fixed sdram init -- doesn't use serial presence detect. */
phys_size_t fixed_sdram(void)
......
......@@ -181,7 +181,7 @@
/* DDR Setup */
#define CONFIG_FSL_DDR3
#define CONFIG_DDR_RAW_TIMING
#define CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 1
#define SPD_EEPROM_ADDRESS 0x52
......
......@@ -227,7 +227,7 @@
/* DDR Setup */
#define CONFIG_FSL_DDR3
#define CONFIG_DDR_RAW_TIMING
#define CONFIG_SYS_DDR_RAW_TIMING
#define CONFIG_DDR_SPD
#define CONFIG_SYS_SPD_BUS_NUM 1
#define SPD_EEPROM_ADDRESS 0x52
......
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