Commit 1d56f63d authored by Wolfgang Denk's avatar Wolfgang Denk
Browse files

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx

* 'master' of git://git.denx.de/u-boot-mpc85xx

:
  powerpc/85xx: use CONFIG_SYS_FSL_PCIE_COMPAT macro when setting the PCI LIODNs
  powerpc/mpc85xx: Ignore E bit for BSC9130/1
  powerpc/sgmii: To support PHY link state auto detect in SGMII mode
  powerpc/85xx: improve definition of BR_PHYS_ADDR macro
  powerpc/p2041: configure the CPLD lane_mux according to RCW
  powerpc/ddr: fix fsl_ddr_get_dimm_params compile error
  powerpc/corenet: fix compile error when CONFIG_SYS_NO_FLASH is defined
  powerpc/mpc8xxx: fix workaround for errata DDR111 and DDR134 for DDR over 4GB
  powerpc/p1022ds: fix DIU/LBC switching with NAND enabled
  powerpc/p1022ds: add support for SPI and SD boot
Signed-off-by: default avatarWolfgang Denk <wd@denx.de>
parents d764c504 5c5befda
......@@ -50,7 +50,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
csn = i;
csn_bnds_backup = regs->cs[i].bnds;
csn_bnds_t = (unsigned int *) &regs->cs[i].bnds;
*csn_bnds_t = regs->cs[i].bnds ^ 0x0F000F00;
if (cs_ea > 0xeff)
*csn_bnds_t = regs->cs[i].bnds + 0x01000000;
else
*csn_bnds_t = regs->cs[i].bnds + 0x01000100;
debug("Found cs%d_bns (0x%08x) covering 0xff000000, "
"change it to 0x%x\n",
csn, csn_bnds_backup, regs->cs[i].bnds);
......@@ -310,9 +313,15 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
/* 7. Wait for 400ms/GB */
total_gb_size_per_controller = 0;
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
total_gb_size_per_controller +=
if (i == csn) {
total_gb_size_per_controller +=
((csn_bnds_backup & 0xFFFF) >> 6)
- (csn_bnds_backup >> 22) + 1;
} else {
total_gb_size_per_controller +=
((regs->cs[i].bnds & 0xFFFF) >> 6)
- (regs->cs[i].bnds >> 22) + 1;
}
}
if (in_be32(&ddr->sdram_cfg) & 0x80000)
total_gb_size_per_controller <<= 1;
......
......@@ -62,9 +62,9 @@ struct liodn_id_table liodn_tbl[] = {
SET_SATA_LIODN(1, 127),
SET_SATA_LIODN(2, 128),
SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193),
SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194),
SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 3, 195),
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 193),
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194),
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195),
SET_DMA_LIODN(1, 197),
SET_DMA_LIODN(2, 198),
......
......@@ -62,10 +62,10 @@ struct liodn_id_table liodn_tbl[] = {
SET_SATA_LIODN(1, 127),
SET_SATA_LIODN(2, 128),
SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193),
SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194),
SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 3, 195),
SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 4, 196),
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 193),
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194),
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195),
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 196),
SET_DMA_LIODN(1, 197),
SET_DMA_LIODN(2, 198),
......
......@@ -52,9 +52,9 @@ struct liodn_id_table liodn_tbl[] = {
SET_SDHC_LIODN(1, 156),
SET_PCI_LIODN("fsl,p4080-pcie", 1, 193),
SET_PCI_LIODN("fsl,p4080-pcie", 2, 194),
SET_PCI_LIODN("fsl,p4080-pcie", 3, 195),
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 193),
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194),
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195),
SET_DMA_LIODN(1, 196),
SET_DMA_LIODN(2, 197),
......
......@@ -62,10 +62,10 @@ struct liodn_id_table liodn_tbl[] = {
SET_SATA_LIODN(1, 127),
SET_SATA_LIODN(2, 128),
SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 1, 193),
SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 2, 194),
SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 3, 195),
SET_PCI_LIODN("fsl,qoriq-pcie-v2.2", 4, 196),
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 1, 193),
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 2, 194),
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 3, 195),
SET_PCI_LIODN(CONFIG_SYS_FSL_PCIE_COMPAT, 4, 196),
SET_DMA_LIODN(1, 197),
SET_DMA_LIODN(2, 198),
......
......@@ -366,7 +366,7 @@ fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
}
}
#else
#elif defined(CONFIG_SYS_DDR_RAW_TIMING)
case STEP_COMPUTE_DIMM_PARMS:
for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
......
......@@ -82,10 +82,10 @@ void lbc_sdram_init(void);
/* Convert an address into the right format for the BR registers */
#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_FSL_ELBC)
#define BR_PHYS_ADDR(x) ((unsigned long)((x & 0x0ffff8000ULL) | \
((x & 0x300000000ULL) >> 19)))
#define BR_PHYS_ADDR(x) \
((u32)(((x) & 0x0ffff8000ULL) | (((x) & 0x300000000ULL) >> 19)))
#else
#define BR_PHYS_ADDR(x) (x & 0xffff8000)
#define BR_PHYS_ADDR(x) ((u32)(x) & 0xffff8000)
#endif
/* OR - Option Registers
......
......@@ -1100,9 +1100,7 @@
#define SVR_8641D 0x809001
#define SVR_9130 0x860001
#define SVR_9130_E 0x860801
#define SVR_9131 0x860000
#define SVR_9131_E 0x860800
#define SVR_Unknown 0xFFFFFF
......
......@@ -17,6 +17,7 @@
#include <net.h>
#include <libfdt.h>
#include <tsec.h>
#include <fdt_support.h>
void fsl_sgmii_riser_init(struct tsec_info_struct *tsec_info, int num)
{
......@@ -31,6 +32,7 @@ void fsl_sgmii_riser_fdt_fixup(void *fdt)
{
struct eth_device *dev;
int node;
int mdio_node;
int i = -1;
int etsec_num = 0;
......@@ -40,16 +42,38 @@ void fsl_sgmii_riser_fdt_fixup(void *fdt)
while ((dev = eth_get_dev_by_index(++i)) != NULL) {
struct tsec_private *priv;
int phy_node;
int enet_node;
uint32_t ph;
char sgmii_phy[16];
char enet[16];
const u32 *phyh;
int phynode;
const char *model;
const char *path;
if (!strstr(dev->name, "eTSEC"))
continue;
priv = dev->priv;
if (!(priv->flags & TSEC_SGMII)) {
etsec_num++;
continue;
}
mdio_node = fdt_node_offset_by_compatible(fdt, -1,
"fsl,gianfar-mdio");
if (mdio_node < 0)
return;
sprintf(sgmii_phy, "sgmii-phy@%d", etsec_num);
phy_node = fdt_subnode_offset(fdt, mdio_node, sgmii_phy);
if (phy_node > 0) {
fdt_increase_size(fdt, 32);
ph = fdt_create_phandle(fdt, phy_node);
if (!ph)
continue;
}
sprintf(enet, "ethernet%d", etsec_num++);
path = fdt_getprop(fdt, node, enet, NULL);
if (!path) {
......@@ -74,15 +98,32 @@ void fsl_sgmii_riser_fdt_fixup(void *fdt)
if (!strstr(model, "TSEC"))
continue;
phyh = fdt_getprop(fdt, enet_node, "phy-handle", NULL);
if (!phyh)
continue;
if (phy_node < 0) {
/*
* This part is only for old device tree without
* sgmii_phy nodes. It's kept just for compatible
* reason. Soon to be deprecated if all device tree
* get updated.
*/
phyh = fdt_getprop(fdt, enet_node, "phy-handle", NULL);
if (!phyh)
continue;
phynode = fdt_node_offset_by_phandle(fdt, fdt32_to_cpu(*phyh));
phy_node = fdt_node_offset_by_phandle(fdt,
fdt32_to_cpu(*phyh));
priv = dev->priv;
priv = dev->priv;
if (priv->flags & TSEC_SGMII)
fdt_setprop_cell(fdt, phynode, "reg", priv->phyaddr);
if (priv->flags & TSEC_SGMII)
fdt_setprop_cell(fdt, phy_node, "reg",
priv->phyaddr);
} else {
fdt_setprop(fdt, enet_node, "phy-handle", &ph,
sizeof(ph));
fdt_setprop_string(fdt, enet_node,
"phy-connection-type",
phy_string_for_interface(
PHY_INTERFACE_MODE_SGMII));
}
}
}
......@@ -63,6 +63,8 @@ static u8 px_brdcfg0;
static u32 pmuxcr;
static void *lbc_lcs0_ba;
static void *lbc_lcs1_ba;
static u32 old_br0, old_or0, old_br1, old_or1;
static u32 new_br0, new_or0, new_br1, new_or1;
void diu_set_pixel_clock(unsigned int pixclock)
{
......@@ -88,10 +90,63 @@ int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
const char *name;
u32 pixel_format;
u8 temp;
phys_addr_t phys0, phys1; /* BR0/BR1 physical addresses */
/* Save the LBC LCS0 and LCS1 addresses for the DIU mux functions */
lbc_lcs0_ba = (void *)(get_lbc_br(0) & get_lbc_or(0) & 0xFFFF8000);
lbc_lcs1_ba = (void *)(get_lbc_br(1) & get_lbc_or(1) & 0xFFFF8000);
/*
* Indirect mode requires both BR0 and BR1 to be set to "GPCM",
* otherwise writes to these addresses won't actually appear on the
* local bus, and so the PIXIS won't see them.
*
* In FCM mode, writes go to the NAND controller, which does not pass
* them to the localbus directly. So we force BR0 and BR1 into GPCM
* mode, since we don't care about what's behind the localbus any
* more. However, we save those registers first, so that we can
* restore them when necessary.
*/
new_br0 = old_br0 = get_lbc_br(0);
new_br1 = old_br1 = get_lbc_br(1);
new_or0 = old_or0 = get_lbc_or(0);
new_or1 = old_or1 = get_lbc_or(1);
/*
* Use the existing BRx/ORx values if it's already GPCM. Otherwise,
* force the values to simple 32KB GPCM windows with the most
* conservative timing.
*/
if ((old_br0 & BR_MSEL) != BR_MS_GPCM) {
new_br0 = (get_lbc_br(0) & BR_BA) | BR_V;
new_or0 = OR_AM_32KB | 0xFF7;
set_lbc_br(0, new_br0);
set_lbc_or(0, new_or0);
}
if ((old_br1 & BR_MSEL) != BR_MS_GPCM) {
new_br1 = (get_lbc_br(1) & BR_BA) | BR_V;
new_or1 = OR_AM_32KB | 0xFF7;
set_lbc_br(1, new_br1);
set_lbc_or(1, new_or1);
}
/*
* Determine the physical addresses for Chip Selects 0 and 1. The
* BR0/BR1 registers contain the truncated physical addresses for the
* chip selects, mapped via the localbus LAW. Since the BRx registers
* only contain the lower 32 bits of the address, we have to determine
* the upper 4 bits some other way. The proper way is to scan the LAW
* table looking for a matching localbus address. Instead, we cheat.
* We know that the upper bits are 0 for 32-bit addressing, or 0xF for
* 36-bit addressing.
*/
#ifdef CONFIG_PHYS_64BIT
phys0 = 0xf00000000ULL | (old_br0 & old_or0 & BR_BA);
phys1 = 0xf00000000ULL | (old_br1 & old_or1 & BR_BA);
#else
phys0 = old_br0 & old_or0 & BR_BA;
phys1 = old_br1 & old_or1 & BR_BA;
#endif
/* Save the LBC LCS0 and LCS1 addresses for the DIU mux functions */
lbc_lcs0_ba = map_physmem(phys0, 1, 0);
lbc_lcs1_ba = map_physmem(phys1, 1, 0);
pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
(0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
......@@ -134,6 +189,7 @@ int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
px_brdcfg0 = in_8(lbc_lcs1_ba);
out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU);
in_8(lbc_lcs1_ba);
/* Set PMUXCR to switch the muxed pins from the LBC to the DIU */
clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU);
......@@ -168,12 +224,10 @@ static int set_mux_to_lbc(void)
* In DIU mode, the PIXIS can only be accessed indirectly
* since we can't read/write the LBC directly.
*/
/* Set the board mux to LBC. This will disable the display. */
out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
px_brdcfg0 = in_8(lbc_lcs1_ba);
out_8(lbc_lcs1_ba, (px_brdcfg0 & ~(PX_BRDCFG0_ELBC_SPI_MASK
| PX_BRDCFG0_ELBC_DIU)) | PX_BRDCFG0_ELBC_SPI_ELBC);
out_8(lbc_lcs1_ba, px_brdcfg0);
in_8(lbc_lcs1_ba);
/* Disable indirect PIXIS mode */
out_8(lbc_lcs0_ba, offsetof(ngpixis_t, csr));
......@@ -184,6 +238,12 @@ static int set_mux_to_lbc(void)
PMUXCR_ELBCDIU_NOR16);
in_be32(&gur->pmuxcr);
/* Restore the BR0 and BR1 settings */
set_lbc_br(0, old_br0);
set_lbc_or(0, old_or0);
set_lbc_br(1, old_br1);
set_lbc_or(1, old_or1);
return 1;
}
......@@ -199,12 +259,18 @@ static void set_mux_to_diu(void)
{
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
/* Set BR0 and BR1 to GPCM mode */
set_lbc_br(0, new_br0);
set_lbc_or(0, new_or0);
set_lbc_br(1, new_br1);
set_lbc_or(1, new_or1);
/* Enable indirect PIXIS mode */
setbits_8(&pixis->csr, PX_CTL_ALTACC);
/* Set the board mux to DIU. This will enable the display. */
out_8(lbc_lcs0_ba, offsetof(ngpixis_t, brdcfg0));
out_8(lbc_lcs1_ba, px_brdcfg0);
out_8(lbc_lcs1_ba, px_brdcfg0 | PX_BRDCFG0_ELBC_DIU);
in_8(lbc_lcs1_ba);
/* Set the chip mux to DIU mode. */
......
......@@ -39,6 +39,10 @@ int board_early_init_f(void)
/* Set pmuxcr to allow both i2c1 and i2c2 */
setbits_be32(&gur->pmuxcr, 0x1000);
#ifdef CONFIG_SYS_RAMBOOT
setbits_be32(&gur->pmuxcr,
in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
#endif
/* Read back the register to synchronize the write. */
in_be32(&gur->pmuxcr);
......
......@@ -71,6 +71,20 @@ struct fsl_e_tlb_entry tlb_table[] = {
SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 7, BOOKE_PAGESZ_4K, 1),
#ifdef CONFIG_SYS_RAMBOOT
/* *I*G - eSDHC/eSPI/NAND boot */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
MAS3_SX|MAS3_SW|MAS3_SR, 0,
0, 8, BOOKE_PAGESZ_1G, 1),
/* map the second 1G */
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 9, BOOKE_PAGESZ_1G, 1),
#endif
#
};
int num_tlb_entries = ARRAY_SIZE(tlb_table);
......@@ -136,6 +136,11 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
}
#endif /* #ifdef CONFIG_FMAN_ENET */
#define CPLD_LANE_A_SEL 0x1
#define CPLD_LANE_G_SEL 0x2
#define CPLD_LANE_C_SEL 0x4
#define CPLD_LANE_D_SEL 0x8
int board_eth_init(bd_t *bis)
{
#ifdef CONFIG_FMAN_ENET
......@@ -143,6 +148,10 @@ int board_eth_init(bd_t *bis)
struct tgec_mdio_info tgec_mdio_info;
unsigned int i, slot;
int lane;
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
int srds_prtcl = (in_be32(&gur->rcwsr[4]) &
FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
u8 mux = CPLD_READ(serdes_mux);
printf("Initializing Fman\n");
......@@ -172,6 +181,36 @@ int board_eth_init(bd_t *bis)
fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
fm_info_set_phy_address(FM1_DTSEC3, CONFIG_SYS_FM1_DTSEC3_PHY_ADDR);
mux &= ~(CPLD_LANE_A_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL);
switch (srds_prtcl) {
case 0x2:
case 0xf:
mux &= ~CPLD_LANE_G_SEL;
break;
case 0x5:
case 0x9:
case 0xa:
case 0x17:
mux |= CPLD_LANE_G_SEL;
break;
case 0x14:
mux = (mux & (~CPLD_LANE_G_SEL)) | CPLD_LANE_A_SEL;
break;
case 0x8:
case 0x16:
case 0x19:
case 0x1a:
mux |= CPLD_LANE_G_SEL | CPLD_LANE_C_SEL | CPLD_LANE_D_SEL;
break;
case 0x1c:
mux |= CPLD_LANE_G_SEL | CPLD_LANE_A_SEL;
break;
default:
printf("Fman:Unsupported SerDes Protocol 0x%02x\n", srds_prtcl);
break;
}
CPLD_WRITE(serdes_mux, mux);
for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
int idx = i - FM1_DTSEC1;
......
......@@ -731,6 +731,10 @@ P1021RDB-PC_NAND powerpc mpc85xx p1_p2_rdb_pc freesca
P1021RDB-PC_SDCARD powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,SDCARD
P1021RDB-PC_SPIFLASH powerpc mpc85xx p1_p2_rdb_pc freescale - p1_p2_rdb_pc:P1021RDB,SPIFLASH
P1022DS powerpc mpc85xx p1022ds freescale
P1022DS_SPIFLASH powerpc mpc85xx p1022ds freescale - P1022DS:SPIFLASH
P1022DS_36BIT_SPIFLASH powerpc mpc85xx p1022ds freescale - P1022DS:36BIT,SPIFLASH
P1022DS_SDCARD powerpc mpc85xx p1022ds freescale - P1022DS:SDCARD
P1022DS_36BIT_SDCARD powerpc mpc85xx p1022ds freescale - P1022DS:36BIT,SDCARD
P1022DS_36BIT powerpc mpc85xx p1022ds freescale - P1022DS:36BIT
P1023RDS powerpc mpc85xx p1023rds freescale - P1023RDS
P1023RDS_NAND powerpc mpc85xx p1023rds freescale - P1023RDS:NAND
......
......@@ -217,8 +217,7 @@
#endif
#define CONFIG_FLASH_BR_PRELIM \
(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
| BR_PS_16 | BR_V)
(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
#define CONFIG_SYS_BR1_PRELIM \
......@@ -380,14 +379,14 @@
#endif
#define CONFIG_SYS_BR4_PRELIM \
(BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)) \
(BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR5_PRELIM \
(BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)) \
(BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
......@@ -395,7 +394,7 @@
#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR6_PRELIM \
(BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)) \
(BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
......
......@@ -189,8 +189,7 @@ extern unsigned long get_clock_freq(void);
#endif
#define CONFIG_SYS_BR0_PRELIM \
(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x800000)) \
| BR_PS_16 | BR_V)
(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V)
#define CONFIG_SYS_BR1_PRELIM \
(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
......
......@@ -205,8 +205,7 @@
#define CONFIG_FLASH_BR_PRELIM \
(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \
| BR_PS_16 | BR_V)
(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
#define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
......@@ -376,20 +375,20 @@
#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#endif
#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000))\
#define CONFIG_SYS_BR4_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000))\
#define CONFIG_SYS_BR5_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000))\
#define CONFIG_SYS_BR6_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)\
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
......
......@@ -18,6 +18,22 @@
#define CONFIG_PHYS_64BIT
#endif
#ifdef CONFIG_SDCARD
#define CONFIG_RAMBOOT_SDCARD
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_SYS_TEXT_BASE 0x11000000
#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
#endif
#ifdef CONFIG_SPIFLASH
#define CONFIG_RAMBOOT_SPIFLASH
#define CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_SYS_TEXT_BASE 0x11000000
#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
#endif
/* High Level Configuration Options */
#define CONFIG_BOOKE /* BOOKE */
#define CONFIG_E500 /* BOOKE e500 family */
......@@ -118,7 +134,7 @@
#endif
#define CONFIG_FLASH_BR_PRELIM \
(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
#define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
......@@ -402,11 +418,40 @@
/*
* Environment
*/
#ifdef CONFIG_SYS_RAMBOOT
#ifdef CONFIG_RAMBOOT_SPIFLASH
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 10000000
#define CONFIG_ENV_SPI_MODE 0
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
#define CONFIG_ENV_SECT_SIZE 0x10000
#elif defined(CONFIG_RAMBOOT_SDCARD)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_SYS_MMC_ENV_DEV 0
#elif defined(CONFIG_NAND_U_BOOT)
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
#define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
#else
#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
#define CONFIG_ENV_SIZE 0x2000
#endif
#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#if CONFIG_SYS_MONITOR_BASE > 0xfff80000
#define CONFIG_ENV_ADDR 0xfff80000
#else
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#endif
#define CONFIG_ENV_SIZE 0x2000
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
#endif
#define CONFIG_LOADS_ECHO
#define CONFIG_SYS_LOADS_BAUD_CHANGE
......
......@@ -236,7 +236,8 @@
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
#endif