Commit 1ed3b710 authored by Wolfgang Denk's avatar Wolfgang Denk
Browse files

Merge branch 'at91' of git://git.denx.de/u-boot-atmel

parents 6d8d4ef9 5dca710a
......@@ -573,6 +573,10 @@ Rishi Bhattacharya <rishi@ti.com>
omap5912osk ARM926EJS
Andreas Biemann <andreas.devel@gmail.com>
at91rm9200ek at91rm9200
Cliff Brake <cliff.brake@gmail.com>
pxa255_idp xscale
......
......@@ -11,47 +11,46 @@
* (at your option) any later version.
*/
#include <config.h>
#include <common.h>
#include <asm/arch/hardware.h>
#include <asm/arch/io.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/clk.h>
static unsigned long cpu_clk_rate_hz;
static unsigned long main_clk_rate_hz;
static unsigned long mck_rate_hz;
static unsigned long plla_rate_hz;
static unsigned long pllb_rate_hz;
static u32 at91_pllb_usb_init;
#if !defined(CONFIG_AT91FAMILY)
# error You need to define CONFIG_AT91FAMILY in your board config!
#endif
DECLARE_GLOBAL_DATA_PTR;
unsigned long get_cpu_clk_rate(void)
{
return cpu_clk_rate_hz;
return gd->cpu_clk_rate_hz;
}
unsigned long get_main_clk_rate(void)
{
return main_clk_rate_hz;
return gd->main_clk_rate_hz;
}
unsigned long get_mck_clk_rate(void)
{
return mck_rate_hz;
return gd->mck_rate_hz;
}
unsigned long get_plla_clk_rate(void)
{
return plla_rate_hz;
return gd->plla_rate_hz;
}
unsigned long get_pllb_clk_rate(void)
{
return pllb_rate_hz;
return gd->pllb_rate_hz;
}
u32 get_pllb_init(void)
{
return at91_pllb_usb_init;
return gd->at91_pllb_usb_init;
}
static unsigned long at91_css_to_rate(unsigned long css)
......@@ -60,11 +59,11 @@ static unsigned long at91_css_to_rate(unsigned long css)
case AT91_PMC_MCKR_CSS_SLOW:
return AT91_SLOW_CLOCK;
case AT91_PMC_MCKR_CSS_MAIN:
return main_clk_rate_hz;
return gd->main_clk_rate_hz;
case AT91_PMC_MCKR_CSS_PLLA:
return plla_rate_hz;
return gd->plla_rate_hz;
case AT91_PMC_MCKR_CSS_PLLB:
return pllb_rate_hz;
return gd->pllb_rate_hz;
}
return 0;
......@@ -163,10 +162,10 @@ int at91_clock_init(unsigned long main_clock)
main_clock = tmp * (AT91_SLOW_CLOCK / 16);
}
#endif
main_clk_rate_hz = main_clock;
gd->main_clk_rate_hz = main_clock;
/* report if PLLA is more than mildly overclocked */
plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
gd->plla_rate_hz = at91_pll_rate(main_clock, readl(&pmc->pllar));
#ifdef CONFIG_USB_ATMEL
/*
......@@ -175,9 +174,9 @@ int at91_clock_init(unsigned long main_clock)
*
* REVISIT: assumes MCK doesn't derive from PLLB!
*/
at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
gd->at91_pllb_usb_init = at91_pll_calc(main_clock, 48000000 * 2) |
AT91_PMC_PLLBR_USBDIV_2;
pllb_rate_hz = at91_pll_rate(main_clock, at91_pllb_usb_init);
gd->pllb_rate_hz = at91_pll_rate(main_clock, gd->at91_pllb_usb_init);
#endif
/*
......@@ -187,30 +186,30 @@ int at91_clock_init(unsigned long main_clock)
mckr = readl(&pmc->mckr);
#if defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
/* plla divisor by 2 */
plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
gd->plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
#endif
mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
freq = mck_rate_hz;
gd->mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
freq = gd->mck_rate_hz;
freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
#if defined(CONFIG_AT91RM9200)
/* mdiv */
mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
gd->mck_rate_hz = freq / (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
#elif defined(CONFIG_AT91SAM9G20)
/* mdiv ; (x >> 7) = ((x >> 8) * 2) */
mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
if (mckr & AT91_PMC_MCKR_MDIV_MASK)
freq /= 2; /* processor clock division */
#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45)
mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
gd->mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ==
(AT91_PMC_MCKR_MDIV_2 | AT91_PMC_MCKR_MDIV_4)
? freq / 3
: freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
#else
mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
gd->mck_rate_hz = freq / (1 << ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
#endif
cpu_clk_rate_hz = freq;
gd->cpu_clk_rate_hz = freq;
return 0;
}
......@@ -30,55 +30,63 @@
#include <asm/arch/io.h>
#include <div64.h>
#if !defined(CONFIG_AT91FAMILY)
# error You need to define CONFIG_AT91FAMILY in your board config!
#endif
DECLARE_GLOBAL_DATA_PTR;
/*
* We're using the AT91CAP9/SAM9 PITC in 32 bit mode, by
* setting the 20 bit counter period to its maximum (0xfffff).
* (See the relevant data sheets to understand that this really works)
*
* We do also mimic the typical powerpc way of incrementing
* two 32 bit registers called tbl and tbu.
*
* Those registers increment at 1/16 the main clock rate.
*/
#define TIMER_LOAD_VAL 0xfffff
static ulong timestamp;
static ulong lastinc;
static ulong timer_freq;
#define TIMER_LOAD_VAL 0xfffff
static inline unsigned long long tick_to_time(unsigned long long tick)
{
tick *= CONFIG_SYS_HZ;
do_div(tick, timer_freq);
do_div(tick, gd->timer_rate_hz);
return tick;
}
static inline unsigned long long usec_to_tick(unsigned long long usec)
{
usec *= timer_freq;
usec *= gd->timer_rate_hz;
do_div(usec, 1000000);
return usec;
}
/* nothing really to do with interrupts, just starts up a counter. */
/*
* Use the PITC in full 32 bit incrementing mode
*/
int timer_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) AT91_PMC_BASE;
at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE;
/*
* Enable PITC Clock
* The clock is already enabled for system controller in boot
*/
/* Enable PITC Clock */
writel(1 << AT91_ID_SYS, &pmc->pcer);
/* Enable PITC */
writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
reset_timer_masked();
timer_freq = get_mck_clk_rate() >> 4;
gd->timer_rate_hz = gd->mck_rate_hz / 16;
gd->tbu = gd->tbl = 0;
return 0;
}
/*
* timer without interrupts
* Get the current 64 bit timer tick count
*/
unsigned long long get_ticks(void)
{
......@@ -86,28 +94,11 @@ unsigned long long get_ticks(void)
ulong now = readl(&pit->piir);
if (now >= lastinc) /* normal mode (non roll) */
/* move stamp forward with absolut diff ticks */
timestamp += (now - lastinc);
else /* we have rollover of incrementer */
timestamp += (0xFFFFFFFF - lastinc) + now;
lastinc = now;
return timestamp;
}
void reset_timer_masked(void)
{
/* reset time */
at91_pit_t *pit = (at91_pit_t *) AT91_PIT_BASE;
/* capture current incrementer value time */
lastinc = readl(&pit->piir);
timestamp = 0; /* start "advancing" time stamp from 0 */
}
ulong get_timer_masked(void)
{
return tick_to_time(get_ticks());
/* increment tbu if tbl has rolled over */
if (now < gd->tbl)
gd->tbu++;
gd->tbl = now;
return (((unsigned long long)gd->tbu) << 32) | gd->tbl;
}
void __udelay(unsigned long usec)
......@@ -119,24 +110,32 @@ void __udelay(unsigned long usec)
tmp = get_ticks() + tmo; /* get current timestamp */
while (get_ticks() < tmp) /* loop till event */
/*NOP*/;
;
}
/*
* reset_timer() and get_timer(base) are a pair of functions that are used by
* some timeout/sleep mechanisms in u-boot.
*
* reset_timer() marks the current time as epoch and
* get_timer(base) works relative to that epoch.
*
* The time is used in CONFIG_SYS_HZ units!
*/
void reset_timer(void)
{
reset_timer_masked();
gd->timer_reset_value = get_ticks();
}
ulong get_timer(ulong base)
{
return get_timer_masked () - base;
return tick_to_time(get_ticks() - gd->timer_reset_value) - base;
}
/*
* This function is derived from PowerPC code (timebase clock frequency).
* On ARM it returns the number of timer ticks per second.
* Return the number of timer ticks per second.
*/
ulong get_tbclk(void)
{
return timer_freq;
return gd->timer_rate_hz;
}
......@@ -18,6 +18,7 @@
#if defined(CONFIG_AT91RM9200)
#include <asm/arch-at91/at91rm9200.h>
#define AT91_PMC_UHP AT91RM9200_PMC_UHP
#elif defined(CONFIG_AT91SAM9260) || defined(CONFIG_AT91SAM9G20)
#include <asm/arch/at91sam9260.h>
#define AT91_BASE_MCI AT91SAM9260_BASE_MCI
......
......@@ -47,6 +47,20 @@ typedef struct global_data {
#ifdef CONFIG_FSL_ESDHC
unsigned long sdhc_clk;
#endif
#ifdef CONFIG_AT91FAMILY
/* "static data" needed by at91's clock.c */
unsigned long cpu_clk_rate_hz;
unsigned long main_clk_rate_hz;
unsigned long mck_rate_hz;
unsigned long plla_rate_hz;
unsigned long pllb_rate_hz;
unsigned long at91_pllb_usb_init;
/* "static data" needed by at91's timer.c */
unsigned long timer_rate_hz;
unsigned long tbl;
unsigned long tbu;
unsigned long long timer_reset_value;
#endif
#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC)
unsigned long relocaddr; /* Start address of U-Boot in RAM */
phys_size_t ram_size; /* RAM size */
......
......@@ -27,11 +27,6 @@ LIB = $(obj)lib$(BOARD).a
COBJS-y += $(BOARD).o
COBJS-y += led.o
COBJS-y += misc.o
ifdef CONFIG_HAS_DATAFLASH
COBJS-$(CONFIG_DATAFLASH_MMC_SELECT) += mux.o
COBJS-y += partition.o
endif
SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS-y))
......
/*
* (C) Copyright 2010 Andreas Bießmann <andreas.devel@gmail.com>
*
* derived from previous work
*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
......@@ -23,78 +27,44 @@
*/
#include <common.h>
#include <exports.h>
#include <netdev.h>
#include <asm/arch/AT91RM9200.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_pio.h>
#include <asm/arch/at91_pmc.h>
#include <asm/io.h>
#if defined(CONFIG_DRIVER_ETHER)
#include <at91rm9200_net.h>
#include <dm9161.h>
#endif
DECLARE_GLOBAL_DATA_PTR;
/* ------------------------------------------------------------------------- */
/*
* Miscelaneous platform dependent initialisations
*/
int board_init (void)
int board_init(void)
{
/* Enable Ctrlc */
console_init_f ();
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
/*
* Correct IRDA resistor problem
* Set PA23_TXD in Output
*/
writel(AT91C_PA23_TXD2, ((AT91PS_PIO) AT91C_BASE_PIOA)->PIO_OER);
/*
* memory and cpu-speed are setup before relocation
* so we do _nothing_ here
*/
writel(AT91_PMX_AA_TXD2, &pio->pioa.oer);
/* arch number of AT91RM9200EK-Board */
gd->bd->bi_arch_number = MACH_TYPE_AT91RM9200EK;
/* adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
return 0;
}
int dram_init (void)
{
gd->bd->bi_dram[0].start = PHYS_SDRAM;
gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE;
/* dram_init must store complete ramsize in gd->ram_size */
gd->ram_size = get_ram_size((volatile long *)CONFIG_SYS_SDRAM_BASE,
CONFIG_SYS_SDRAM_SIZE);
return 0;
}
#if defined(CONFIG_DRIVER_ETHER) && defined(CONFIG_CMD_NET)
/*
* Name:
* at91rm9200_GetPhyInterface
* Description:
* Initialise the interface functions to the PHY
* Arguments:
* None
* Return value:
* None
*/
void at91rm9200_GetPhyInterface(AT91PS_PhyOps p_phyops)
{
p_phyops->Init = dm9161_InitPhy;
p_phyops->IsPhyConnected = dm9161_IsPhyConnected;
p_phyops->GetLinkSpeed = dm9161_GetLinkSpeed;
p_phyops->AutoNegotiate = dm9161_AutoNegotiate;
}
#endif
#ifdef CONFIG_DRIVER_AT91EMAC
int board_eth_init(bd_t *bis)
{
int rc = 0;
rc = at91emac_register(bis, 0);
return rc;
return at91emac_register(bis, (u32) AT91_EMAC_BASE);
}
#endif
CONFIG_SYS_TEXT_BASE = 0x21f00000
# currently only NOR flash booting is supported
CONFIG_SYS_TEXT_BASE = 0x10000000
......@@ -3,6 +3,9 @@
* Atmel Nordic AB <www.atmel.com>
* Ulf Samuelsson <ulf@atmel.com>
*
* (C) Copyright 2010
* Andreas Bießmann <andreas.devel@gmail.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
......@@ -23,67 +26,62 @@
*/
#include <common.h>
#include <asm/arch/AT91RM9200.h>
#include <asm/io.h>
#include <asm/arch/gpio.h>
#include <asm/arch/at91_pmc.h>
#define GREEN_LED AT91C_PIO_PB0
#define YELLOW_LED AT91C_PIO_PB1
#define RED_LED AT91C_PIO_PB2
/* bit mask in PIO port B */
#define GREEN_LED (1<<0)
#define YELLOW_LED (1<<1)
#define RED_LED (1<<2)
void green_LED_on(void)
{
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
writel(GREEN_LED, PIOB->PIO_CODR);
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
writel(GREEN_LED, &pio->piob.codr);
}
void yellow_LED_on(void)
{
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
writel(YELLOW_LED, PIOB->PIO_CODR);
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
writel(YELLOW_LED, &pio->piob.codr);
}
void red_LED_on(void)
{
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
writel(RED_LED, PIOB->PIO_CODR);
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
writel(RED_LED, &pio->piob.codr);
}
void green_LED_off(void)
{
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
writel(GREEN_LED, PIOB->PIO_SODR);
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
writel(GREEN_LED, &pio->piob.sodr);
}
void yellow_LED_off(void)
{
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
writel(YELLOW_LED, PIOB->PIO_SODR);
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
writel(YELLOW_LED, &pio->piob.sodr);
}
void red_LED_off(void)
{
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
writel(RED_LED, PIOB->PIO_SODR);
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
writel(RED_LED, &pio->piob.sodr);
}
void coloured_LED_init (void)
{
AT91PS_PIO PIOB = AT91C_BASE_PIOB;
AT91PS_PMC PMC = AT91C_BASE_PMC;
at91_pmc_t *pmc = (at91_pmc_t *)AT91_PMC_BASE;
at91_pio_t *pio = (at91_pio_t *)AT91_PIO_BASE;
/* Enable PIOB clock */
writel((1 << AT91C_ID_PIOB), PMC->PMC_PCER);
writel(1 << AT91_ID_PIOB, &pmc->pcer);
/* Disable peripherals on LEDs */
writel(AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0, PIOB->PIO_PER);
writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.per);
/* Enable pins as outputs */
writel(AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0, PIOB->PIO_OER);
writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.oer);
/* Turn all LEDs OFF */
writel(AT91C_PIO_PB2 | AT91C_PIO_PB1 | AT91C_PIO_PB0, PIOB->PIO_SODR);
writel(GREEN_LED | YELLOW_LED | RED_LED, &pio->piob.sodr);
}
/*
* (C) Copyright 2002
* Sysgo Real-Time Solutions, GmbH <www.elinos.com>
* Marius Groeger <mgroeger@sysgo.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <asm/arch/AT91RM9200.h>
#include <at91rm9200_net.h>
#include <dm9161.h>
#include <net.h>
int board_late_init(void)
{
DECLARE_GLOBAL_DATA_PTR;
/* Fix Ethernet Initialization Bug when starting Linux from U-Boot */
eth_init(gd->bd);
return 0;
}
/* checks if addr is in RAM */
int addr2ram(ulong addr)
{
int result = 0;
if((addr >= PHYS_SDRAM) && (addr < (PHYS_SDRAM + PHYS_SDRAM_SIZE)))
result = 1;
return result;
}
#include <config.h>
#include <common.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <dataflash.h>
int AT91F_GetMuxStatus(void)
{
/* Set in PIO mode */
writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_PER);
/* Configure in output */
writel(CONFIG_SYS_DATAFLASH_MMC_PIO, AT91C_BASE_PIOB->PIO_OER);
if(readl(AT91C_BASE_PIOB->PIO_ODSR) & CONFIG_SYS_DATAFLASH_MMC_PIO)
return 1;
return 0;
}