Commit 20680b56 authored by Tom Rini's avatar Tom Rini

Merge branch 'master' of git://git.denx.de/u-boot-atmel

parents db6ce231 2a0b9ea3
......@@ -96,6 +96,11 @@ config TARGET_SAMA5D4EK
select CPU_V7
select SUPPORT_SPL
config TARGET_MA5D4EVK
bool "DENX MA5D4EVK Evaluation Kit"
select CPU_V7
select SUPPORT_SPL
config TARGET_MEESC
bool "Support meesc"
select CPU_ARM926EJS
......@@ -115,6 +120,11 @@ config TARGET_SMARTWEB
select CPU_ARM926EJS
select SUPPORT_SPL
config TARGET_VINCO
bool "Support VINCO"
select CPU_V7
select SUPPORT_SPL
endchoice
config SYS_SOC
......@@ -135,8 +145,10 @@ source "board/atmel/sama5d4_xplained/Kconfig"
source "board/atmel/sama5d4ek/Kconfig"
source "board/bluewater/snapper9260/Kconfig"
source "board/calao/usb_a9263/Kconfig"
source "board/denx/ma5d4evk/Kconfig"
source "board/egnite/ethernut5/Kconfig"
source "board/esd/meesc/Kconfig"
source "board/l+g/vinco/Kconfig"
source "board/mini-box/picosam9g45/Kconfig"
source "board/ronetix/pm9261/Kconfig"
source "board/ronetix/pm9263/Kconfig"
......
......@@ -15,6 +15,7 @@ obj-$(CONFIG_SAMA5D4) += mpddrc.o spl_atmel.o matrix.o atmel_sfr.o
obj-y += spl.o
endif
obj-y += clock.o
obj-$(CONFIG_CPU_ARM920T) += arm920t/
obj-$(CONFIG_CPU_ARM926EJS) += arm926ejs/
obj-$(CONFIG_CPU_V7) += armv7/
......@@ -14,7 +14,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
/*
......@@ -34,29 +34,23 @@
void at91_serial0_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 17, 1); /* TXD0 */
at91_set_a_periph(AT91_PIO_PORTA, 18, PUP); /* RXD0 */
writel(1 << ATMEL_ID_USART0, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_USART0);
}
void at91_serial1_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTB, 20, PUP); /* RXD1 */
at91_set_a_periph(AT91_PIO_PORTB, 21, 1); /* TXD1 */
writel(1 << ATMEL_ID_USART1, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_USART1);
}
void at91_serial2_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 22, PUP); /* RXD2 */
at91_set_a_periph(AT91_PIO_PORTA, 23, 1); /* TXD2 */
writel(1 << ATMEL_ID_USART2, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_USART2);
}
void at91_seriald_hw_init(void)
......
......@@ -18,6 +18,8 @@
# error You need to define CONFIG_AT91FAMILY in your board config!
#endif
#define EN_PLLB_TIMEOUT 500
DECLARE_GLOBAL_DATA_PTR;
static unsigned long at91_css_to_rate(unsigned long css)
......@@ -155,3 +157,39 @@ int at91_clock_init(unsigned long main_clock)
return 0;
}
int at91_pllb_clk_enable(u32 pllbr)
{
struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
ulong start_time, tmp_time;
start_time = get_timer(0);
writel(pllbr, &pmc->pllbr);
while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) {
tmp_time = get_timer(0);
if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) {
printf("ERROR: failed to enable PLLB\n");
return -1;
}
}
return 0;
}
int at91_pllb_clk_disable(void)
{
struct at91_pmc *pmc = (at91_pmc_t *)ATMEL_BASE_PMC;
ulong start_time, tmp_time;
start_time = get_timer(0);
writel(0, &pmc->pllbr);
while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0) {
tmp_time = get_timer(0);
if ((tmp_time - start_time) > EN_PLLB_TIMEOUT) {
printf("ERROR: failed to disable PLLB\n");
return -1;
}
}
return 0;
}
......@@ -19,7 +19,7 @@
#include <asm/io.h>
#include <asm/arch/hardware.h>
#include <asm/arch/at91_tc.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/clk.h>
DECLARE_GLOBAL_DATA_PTR;
......@@ -29,10 +29,8 @@ DECLARE_GLOBAL_DATA_PTR;
int timer_init(void)
{
at91_tc_t *tc = (at91_tc_t *) ATMEL_BASE_TC;
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
/* enables TC1.0 clock */
writel(1 << ATMEL_ID_TC0, &pmc->pcer); /* enable clock */
at91_periph_clk_enable(ATMEL_ID_TC0);
writel(0, &tc->bcr);
writel(AT91_TC_BMR_TC0XC0S_NONE | AT91_TC_BMR_TC1XC1S_NONE |
......
......@@ -11,8 +11,8 @@
#include <asm/io.h>
#include <asm/arch/at91sam9260_matrix.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91sam9_sdramc.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
/*
......@@ -32,51 +32,40 @@
void at91_serial0_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD0 */
at91_set_a_periph(AT91_PIO_PORTB, 5, PUP); /* RXD0 */
writel(1 << ATMEL_ID_USART0, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_USART0);
}
void at91_serial1_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTB, 6, 1); /* TXD1 */
at91_set_a_periph(AT91_PIO_PORTB, 7, PUP); /* RXD1 */
writel(1 << ATMEL_ID_USART1, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_USART1);
}
void at91_serial2_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTB, 8, 1); /* TXD2 */
at91_set_a_periph(AT91_PIO_PORTB, 9, PUP); /* RXD2 */
writel(1 << ATMEL_ID_USART2, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_USART2);
}
void at91_seriald_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* DRXD */
at91_set_a_periph(AT91_PIO_PORTB, 15, 1); /* DTXD */
writel(1 << ATMEL_ID_SYS, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_SYS);
}
#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
void at91_spi0_hw_init(unsigned long cs_mask)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */
at91_set_a_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */
at91_set_a_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */
/* Enable clock */
writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_SPI0);
if (cs_mask & (1 << 0)) {
at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
......@@ -106,14 +95,11 @@ void at91_spi0_hw_init(unsigned long cs_mask)
void at91_spi1_hw_init(unsigned long cs_mask)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTB, 0, PUP); /* SPI1_MISO */
at91_set_a_periph(AT91_PIO_PORTB, 1, PUP); /* SPI1_MOSI */
at91_set_a_periph(AT91_PIO_PORTB, 2, PUP); /* SPI1_SPCK */
/* Enable clock */
writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_SPI1);
if (cs_mask & (1 << 0)) {
at91_set_a_periph(AT91_PIO_PORTB, 3, 1);
......@@ -145,9 +131,7 @@ void at91_spi1_hw_init(unsigned long cs_mask)
#ifdef CONFIG_MACB
void at91_macb_hw_init(void)
{
/* Enable EMAC clock */
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_EMAC0);
at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* ETXCK_EREFCK */
at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* ERXDV */
......@@ -190,9 +174,7 @@ void at91_macb_hw_init(void)
#if defined(CONFIG_GENERIC_ATMEL_MCI)
void at91_mci_hw_init(void)
{
/* Enable mci clock */
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
writel(1 << ATMEL_ID_MCI, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_MCI);
at91_set_a_periph(AT91_PIO_PORTA, 8, 1); /* MCCK */
#if defined(CONFIG_ATMEL_MCI_PORTB)
......
......@@ -9,7 +9,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
/*
......@@ -29,51 +29,40 @@
void at91_serial0_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTC, 8, 1); /* TXD0 */
at91_set_a_periph(AT91_PIO_PORTC, 9, 0); /* RXD0 */
writel(1 << ATMEL_ID_USART0, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_USART0);
}
void at91_serial1_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTC, 12, 1); /* TXD1 */
at91_set_a_periph(AT91_PIO_PORTC, 13, 0); /* RXD1 */
writel(1 << ATMEL_ID_USART1, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_USART1);
}
void at91_serial2_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTC, 14, 1); /* TXD2 */
at91_set_a_periph(AT91_PIO_PORTC, 15, 0); /* RXD2 */
writel(1 << ATMEL_ID_USART2, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_USART2);
}
void at91_seriald_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
writel(1 << ATMEL_ID_SYS, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_SYS);
}
#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
void at91_spi0_hw_init(unsigned long cs_mask)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */
at91_set_a_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */
at91_set_a_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */
/* Enable clock */
writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_SPI0);
if (cs_mask & (1 << 0)) {
at91_set_a_periph(AT91_PIO_PORTA, 3, 1);
......@@ -103,14 +92,11 @@ void at91_spi0_hw_init(unsigned long cs_mask)
void at91_spi1_hw_init(unsigned long cs_mask)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTB, 30, PUP); /* SPI1_MISO */
at91_set_a_periph(AT91_PIO_PORTB, 31, PUP); /* SPI1_MOSI */
at91_set_a_periph(AT91_PIO_PORTB, 29, PUP); /* SPI1_SPCK */
/* Enable clock */
writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_SPI1);
if (cs_mask & (1 << 0)) {
at91_set_a_periph(AT91_PIO_PORTB, 28, 1);
......
......@@ -13,7 +13,7 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
/*
......@@ -33,51 +33,40 @@
void at91_serial0_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 26, 1); /* TXD0 */
at91_set_a_periph(AT91_PIO_PORTA, 27, PUP); /* RXD0 */
writel(1 << ATMEL_ID_USART0, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_USART0);
}
void at91_serial1_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTD, 0, 1); /* TXD1 */
at91_set_a_periph(AT91_PIO_PORTD, 1, PUP); /* RXD1 */
writel(1 << ATMEL_ID_USART1, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_USART1);
}
void at91_serial2_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTD, 2, 1); /* TXD2 */
at91_set_a_periph(AT91_PIO_PORTD, 3, PUP); /* RXD2 */
writel(1 << ATMEL_ID_USART2, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_USART2);
}
void at91_seriald_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTC, 30, PUP); /* DRXD */
at91_set_a_periph(AT91_PIO_PORTC, 31, 1); /* DTXD */
writel(1 << ATMEL_ID_SYS, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_SYS);
}
#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
void at91_spi0_hw_init(unsigned long cs_mask)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_b_periph(AT91_PIO_PORTA, 0, PUP); /* SPI0_MISO */
at91_set_b_periph(AT91_PIO_PORTA, 1, PUP); /* SPI0_MOSI */
at91_set_b_periph(AT91_PIO_PORTA, 2, PUP); /* SPI0_SPCK */
/* Enable clock */
writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_SPI0);
if (cs_mask & (1 << 0)) {
at91_set_b_periph(AT91_PIO_PORTA, 5, 1);
......@@ -107,14 +96,11 @@ void at91_spi0_hw_init(unsigned long cs_mask)
void at91_spi1_hw_init(unsigned long cs_mask)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTB, 12, PUP); /* SPI1_MISO */
at91_set_a_periph(AT91_PIO_PORTB, 13, PUP); /* SPI1_MOSI */
at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* SPI1_SPCK */
/* Enable clock */
writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_SPI1);
if (cs_mask & (1 << 0)) {
at91_set_a_periph(AT91_PIO_PORTB, 15, 1);
......@@ -146,9 +132,7 @@ void at91_spi1_hw_init(unsigned long cs_mask)
#if defined(CONFIG_GENERIC_ATMEL_MCI)
void at91_mci_hw_init(void)
{
/* Enable mci clock */
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
writel(1 << ATMEL_ID_MCI1, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_MCI1);
at91_set_a_periph(AT91_PIO_PORTA, 6, PUP); /* MCI1_CK */
......@@ -207,12 +191,9 @@ void at91_uhp_hw_init(void)
#ifdef CONFIG_AT91_CAN
void at91_can_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* CAN_TX */
at91_set_a_periph(AT91_PIO_PORTA, 14, 1); /* CAN_RX */
/* Enable clock */
writel(1 << ATMEL_ID_CAN, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_CAN);
}
#endif
......@@ -8,7 +8,7 @@
#include <common.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <asm/io.h>
......@@ -29,51 +29,40 @@
void at91_serial0_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTB, 19, 1); /* TXD0 */
at91_set_a_periph(AT91_PIO_PORTB, 18, PUP); /* RXD0 */
writel(1 << ATMEL_ID_USART0, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_USART0);
}
void at91_serial1_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTB, 4, 1); /* TXD1 */
at91_set_a_periph(AT91_PIO_PORTB, 5, PUP); /* RXD1 */
writel(1 << ATMEL_ID_USART1, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_USART1);
}
void at91_serial2_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTD, 6, 1); /* TXD2 */
at91_set_a_periph(AT91_PIO_PORTD, 7, PUP); /* RXD2 */
writel(1 << ATMEL_ID_USART2, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_USART2);
}
void at91_seriald_hw_init(void)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTB, 12, 0); /* DRXD */
at91_set_a_periph(AT91_PIO_PORTB, 13, 1); /* DTXD */
writel(1 << ATMEL_ID_SYS, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_SYS);
}
#if defined(CONFIG_HAS_DATAFLASH) || defined(CONFIG_ATMEL_SPI)
void at91_spi0_hw_init(unsigned long cs_mask)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTB, 0, PUP); /* SPI0_MISO */
at91_set_a_periph(AT91_PIO_PORTB, 1, PUP); /* SPI0_MOSI */
at91_set_a_periph(AT91_PIO_PORTB, 2, PUP); /* SPI0_SPCK */
/* Enable clock */
writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_SPI0);
if (cs_mask & (1 << 0)) {
at91_set_a_periph(AT91_PIO_PORTB, 3, 1);
......@@ -103,14 +92,11 @@ void at91_spi0_hw_init(unsigned long cs_mask)
void at91_spi1_hw_init(unsigned long cs_mask)
{
at91_pmc_t *pmc = (at91_pmc_t *) ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTB, 14, PUP); /* SPI1_MISO */
at91_set_a_periph(AT91_PIO_PORTB, 15, PUP); /* SPI1_MOSI */
at91_set_a_periph(AT91_PIO_PORTB, 16, PUP); /* SPI1_SPCK */
/* Enable clock */
writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_SPI1);
if (cs_mask & (1 << 0)) {
at91_set_a_periph(AT91_PIO_PORTB, 17, 1);
......@@ -169,8 +155,6 @@ void at91_macb_hw_init(void)
#ifdef CONFIG_GENERIC_ATMEL_MCI
void at91_mci_hw_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 0, 0); /* MCI0 CLK */
at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* MCI0 CDA */
at91_set_a_periph(AT91_PIO_PORTA, 2, 0); /* MCI0 DA0 */
......@@ -178,7 +162,6 @@ void at91_mci_hw_init(void)
at91_set_a_periph(AT91_PIO_PORTA, 4, 0); /* MCI0 DA2 */
at91_set_a_periph(AT91_PIO_PORTA, 5, 0); /* MCI0 DA3 */
/* Enable clock */
writel(1 << ATMEL_ID_MCI0, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_MCI0);
}
#endif
......@@ -8,8 +8,8 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_pmc.h>
#include <asm/arch/at91_pio.h>
#include <asm/arch/clk.h>
unsigned int has_lcdc()
{
......@@ -18,60 +18,47 @@ unsigned int has_lcdc()
void at91_serial0_hw_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 0, 1); /* TXD0 */
at91_set_a_periph(AT91_PIO_PORTA, 1, 0); /* RXD0 */
writel(1 << ATMEL_ID_USART0, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_USART0);
}
void at91_serial1_hw_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 5, 1); /* TXD1 */
at91_set_a_periph(AT91_PIO_PORTA, 6, 0); /* RXD1 */
writel(1 << ATMEL_ID_USART1, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_USART1);
}
void at91_serial2_hw_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 7, 1); /* TXD2 */
at91_set_a_periph(AT91_PIO_PORTA, 8, 0); /* RXD2 */
writel(1 << ATMEL_ID_USART2, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_USART2);
}
void at91_serial3_hw_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
at91_set_b_periph(AT91_PIO_PORTC, 22, 1); /* TXD3 */
at91_set_b_periph(AT91_PIO_PORTC, 23, 0); /* RXD3 */
writel(1 << ATMEL_ID_USART3, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_USART3);
}
void at91_seriald_hw_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 10, 1); /* DTXD */
at91_set_a_periph(AT91_PIO_PORTA, 9, 0); /* DRXD */
writel(1 << ATMEL_ID_SYS, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_SYS);
}
#ifdef CONFIG_ATMEL_SPI
void at91_spi0_hw_init(unsigned long cs_mask)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 11, 0); /* SPI0_MISO */
at91_set_a_periph(AT91_PIO_PORTA, 12, 0); /* SPI0_MOSI */
at91_set_a_periph(AT91_PIO_PORTA, 13, 0); /* SPI0_SPCK */
/* Enable clock */
writel(1 << ATMEL_ID_SPI0, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_SPI0);
if (cs_mask & (1 << 0))
at91_set_pio_output(AT91_PIO_PORTA, 14, 1);
......@@ -85,14 +72,11 @@ void at91_spi0_hw_init(unsigned long cs_mask)
void at91_spi1_hw_init(unsigned long cs_mask)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
at91_set_b_periph(AT91_PIO_PORTA, 21, 0); /* SPI1_MISO */
at91_set_b_periph(AT91_PIO_PORTA, 22, 0); /* SPI1_MOSI */
at91_set_b_periph(AT91_PIO_PORTA, 23, 0); /* SPI1_SPCK */
/* Enable clock */
writel(1 << ATMEL_ID_SPI1, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_SPI1);
if (cs_mask & (1 << 0))
at91_set_pio_output(AT91_PIO_PORTA, 8, 1);
......@@ -107,8 +91,6 @@ void at91_spi1_hw_init(unsigned long cs_mask)
void at91_mci_hw_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTA, 17, 0); /* MCCK */
at91_set_a_periph(AT91_PIO_PORTA, 16, 0); /* MCCDA */
at91_set_a_periph(AT91_PIO_PORTA, 15, 0); /* MCDA0 */
......@@ -116,14 +98,12 @@ void at91_mci_hw_init(void)
at91_set_a_periph(AT91_PIO_PORTA, 19, 0); /* MCDA2 */
at91_set_a_periph(AT91_PIO_PORTA, 20, 0); /* MCDA3 */
writel(1 << ATMEL_ID_HSMCI0, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_HSMCI0);
}
#ifdef CONFIG_LCD
void at91_lcd_hw_init(void)
{
struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
at91_set_a_periph(AT91_PIO_PORTC, 24, 0); /* LCDDPWR */
at91_set_a_periph(AT91_PIO_PORTC, 26, 0); /* LCDVSYNC */
at91_set_a_periph(AT91_PIO_PORTC, 27, 0); /* LCDHSYNC */
......@@ -156,6 +136,6 @@ void at91_lcd_hw_init(void)
at91_set_a_periph(AT91_PIO_PORTC, 22, 0); /* LCDD22 */
at91_set_a_periph(AT91_PIO_PORTC, 23, 0); /* LCDD23 */
writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
at91_periph_clk_enable(ATMEL_ID_LCDC);
}
#endif