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Librem5
uboot-imx
Commits
20913018
Commit
20913018
authored
Apr 16, 2015
by
Tom Rini
Browse files
Merge branch 'master' of
http://git.denx.de/u-boot-sunxi
parents
a32d2791
6c739c5d
Changes
39
Hide whitespace changes
Inline
Side-by-side
arch/arm/cpu/armv7/sunxi/board.c
View file @
20913018
...
...
@@ -46,28 +46,33 @@ static int gpio_init(void)
sunxi_gpio_set_cfgpin
(
SUNXI_GPB
(
22
),
SUNXI_GPIO_INPUT
);
sunxi_gpio_set_cfgpin
(
SUNXI_GPB
(
23
),
SUNXI_GPIO_INPUT
);
#endif
sunxi_gpio_set_cfgpin
(
SUNXI_GPF
(
2
),
SUNXI_GPF2_UART0_TX
);
sunxi_gpio_set_cfgpin
(
SUNXI_GPF
(
4
),
SUNXI_GPF4_UART0_RX
);
#if defined(CONFIG_MACH_SUN8I)
sunxi_gpio_set_cfgpin
(
SUNXI_GPF
(
2
),
SUN8I_GPF_UART0_TX
);
sunxi_gpio_set_cfgpin
(
SUNXI_GPF
(
4
),
SUN8I_GPF_UART0_RX
);
#else
sunxi_gpio_set_cfgpin
(
SUNXI_GPF
(
2
),
SUNXI_GPF_UART0_TX
);
sunxi_gpio_set_cfgpin
(
SUNXI_GPF
(
4
),
SUNXI_GPF_UART0_RX
);
#endif
sunxi_gpio_set_pull
(
SUNXI_GPF
(
4
),
1
);
#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I))
sunxi_gpio_set_cfgpin
(
SUNXI_GPB
(
22
),
SUN4I_GPB
22
_UART0
_TX
);
sunxi_gpio_set_cfgpin
(
SUNXI_GPB
(
23
),
SUN4I_GPB
23
_UART0
_RX
);
sunxi_gpio_set_cfgpin
(
SUNXI_GPB
(
22
),
SUN4I_GPB_UART0
);
sunxi_gpio_set_cfgpin
(
SUNXI_GPB
(
23
),
SUN4I_GPB_UART0
);
sunxi_gpio_set_pull
(
SUNXI_GPB
(
23
),
SUNXI_GPIO_PULL_UP
);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
sunxi_gpio_set_cfgpin
(
SUNXI_GPB
(
19
),
SUN5I_GPB
19
_UART0
_TX
);
sunxi_gpio_set_cfgpin
(
SUNXI_GPB
(
20
),
SUN5I_GPB
20
_UART0
_RX
);
sunxi_gpio_set_cfgpin
(
SUNXI_GPB
(
19
),
SUN5I_GPB_UART0
);
sunxi_gpio_set_cfgpin
(
SUNXI_GPB
(
20
),
SUN5I_GPB_UART0
);
sunxi_gpio_set_pull
(
SUNXI_GPB
(
20
),
SUNXI_GPIO_PULL_UP
);
#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
sunxi_gpio_set_cfgpin
(
SUNXI_GPH
(
20
),
SUN6I_GPH
20
_UART0
_TX
);
sunxi_gpio_set_cfgpin
(
SUNXI_GPH
(
21
),
SUN6I_GPH
21
_UART0
_RX
);
sunxi_gpio_set_cfgpin
(
SUNXI_GPH
(
20
),
SUN6I_GPH_UART0
);
sunxi_gpio_set_cfgpin
(
SUNXI_GPH
(
21
),
SUN6I_GPH_UART0
);
sunxi_gpio_set_pull
(
SUNXI_GPH
(
21
),
SUNXI_GPIO_PULL_UP
);
#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
sunxi_gpio_set_cfgpin
(
SUNXI_GPG
(
3
),
SUN5I_GPG
3
_UART1
_TX
);
sunxi_gpio_set_cfgpin
(
SUNXI_GPG
(
4
),
SUN5I_GPG
4
_UART1
_RX
);
sunxi_gpio_set_cfgpin
(
SUNXI_GPG
(
3
),
SUN5I_GPG_UART1
);
sunxi_gpio_set_cfgpin
(
SUNXI_GPG
(
4
),
SUN5I_GPG_UART1
);
sunxi_gpio_set_pull
(
SUNXI_GPG
(
4
),
SUNXI_GPIO_PULL_UP
);
#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
sunxi_gpio_set_cfgpin
(
SUNXI_GPL
(
2
),
SUN8I_GPL
2
_R_UART
_TX
);
sunxi_gpio_set_cfgpin
(
SUNXI_GPL
(
3
),
SUN8I_GPL
3
_R_UART
_RX
);
sunxi_gpio_set_cfgpin
(
SUNXI_GPL
(
2
),
SUN8I_GPL_R_UART
);
sunxi_gpio_set_cfgpin
(
SUNXI_GPL
(
3
),
SUN8I_GPL_R_UART
);
sunxi_gpio_set_pull
(
SUNXI_GPL
(
3
),
SUNXI_GPIO_PULL_UP
);
#else
#error Unsupported console port number. Please fix pin mux settings in board.c
...
...
arch/arm/cpu/armv7/sunxi/rsb.c
View file @
20913018
...
...
@@ -21,15 +21,15 @@ static int rsb_set_device_mode(void);
static
void
rsb_cfg_io
(
void
)
{
#ifdef CONFIG_MACH_SUN8I
sunxi_gpio_set_cfgpin
(
SUNXI_GPL
(
0
),
SUN8I_GPL
0
_R_RSB
_SCK
);
sunxi_gpio_set_cfgpin
(
SUNXI_GPL
(
1
),
SUN8I_GPL
1
_R_RSB
_SDA
);
sunxi_gpio_set_cfgpin
(
SUNXI_GPL
(
0
),
SUN8I_GPL_R_RSB
);
sunxi_gpio_set_cfgpin
(
SUNXI_GPL
(
1
),
SUN8I_GPL_R_RSB
);
sunxi_gpio_set_pull
(
SUNXI_GPL
(
0
),
1
);
sunxi_gpio_set_pull
(
SUNXI_GPL
(
1
),
1
);
sunxi_gpio_set_drv
(
SUNXI_GPL
(
0
),
2
);
sunxi_gpio_set_drv
(
SUNXI_GPL
(
1
),
2
);
#elif defined CONFIG_MACH_SUN9I
sunxi_gpio_set_cfgpin
(
SUNXI_GPN
(
0
),
SUN9I_GPN
0
_R_RSB
_SCK
);
sunxi_gpio_set_cfgpin
(
SUNXI_GPN
(
1
),
SUN9I_GPN
1
_R_RSB
_SDA
);
sunxi_gpio_set_cfgpin
(
SUNXI_GPN
(
0
),
SUN9I_GPN_R_RSB
);
sunxi_gpio_set_cfgpin
(
SUNXI_GPN
(
1
),
SUN9I_GPN_R_RSB
);
sunxi_gpio_set_pull
(
SUNXI_GPN
(
0
),
1
);
sunxi_gpio_set_pull
(
SUNXI_GPN
(
1
),
1
);
sunxi_gpio_set_drv
(
SUNXI_GPN
(
0
),
2
);
...
...
arch/arm/cpu/armv7/sunxi/usbc.c
View file @
20913018
...
...
@@ -41,6 +41,7 @@ static struct sunxi_usbc_hcd {
int
usb_rst_mask
;
int
ahb_clk_mask
;
int
gpio_vbus
;
int
gpio_vbus_det
;
int
irq
;
int
id
;
}
sunxi_usbc_hcd
[]
=
{
...
...
@@ -80,12 +81,6 @@ static struct sunxi_usbc_hcd {
static
int
enabled_hcd_count
;
static
bool
use_axp_drivebus
(
int
index
)
{
return
index
==
0
&&
strcmp
(
CONFIG_USB0_VBUS_PIN
,
"axp_drivebus"
)
==
0
;
}
void
*
sunxi_usbc_get_io_base
(
int
index
)
{
switch
(
index
)
{
...
...
@@ -102,9 +97,6 @@ void *sunxi_usbc_get_io_base(int index)
static
int
get_vbus_gpio
(
int
index
)
{
if
(
use_axp_drivebus
(
index
))
return
-
1
;
switch
(
index
)
{
case
0
:
return
sunxi_name_to_gpio
(
CONFIG_USB0_VBUS_PIN
);
case
1
:
return
sunxi_name_to_gpio
(
CONFIG_USB1_VBUS_PIN
);
...
...
@@ -113,6 +105,14 @@ static int get_vbus_gpio(int index)
return
-
1
;
}
static
int
get_vbus_detect_gpio
(
int
index
)
{
switch
(
index
)
{
case
0
:
return
sunxi_name_to_gpio
(
CONFIG_USB0_VBUS_DET
);
}
return
-
1
;
}
static
void
usb_phy_write
(
struct
sunxi_usbc_hcd
*
sunxi_usbc
,
int
addr
,
int
data
,
int
len
)
{
...
...
@@ -192,22 +192,35 @@ void sunxi_usbc_enable_squelch_detect(int index, int enable)
int
sunxi_usbc_request_resources
(
int
index
)
{
struct
sunxi_usbc_hcd
*
sunxi_usbc
=
&
sunxi_usbc_hcd
[
index
];
int
ret
=
0
;
sunxi_usbc
->
gpio_vbus
=
get_vbus_gpio
(
index
);
if
(
sunxi_usbc
->
gpio_vbus
!=
-
1
)
return
gpio_request
(
sunxi_usbc
->
gpio_vbus
,
"usbc_vbus"
);
if
(
sunxi_usbc
->
gpio_vbus
!=
-
1
)
{
ret
|=
gpio_request
(
sunxi_usbc
->
gpio_vbus
,
"usbc_vbus"
);
ret
|=
gpio_direction_output
(
sunxi_usbc
->
gpio_vbus
,
0
);
}
sunxi_usbc
->
gpio_vbus_det
=
get_vbus_detect_gpio
(
index
);
if
(
sunxi_usbc
->
gpio_vbus_det
!=
-
1
)
{
ret
|=
gpio_request
(
sunxi_usbc
->
gpio_vbus_det
,
"usbc_vbus_det"
);
ret
|=
gpio_direction_input
(
sunxi_usbc
->
gpio_vbus_det
);
}
return
0
;
return
ret
;
}
int
sunxi_usbc_free_resources
(
int
index
)
{
struct
sunxi_usbc_hcd
*
sunxi_usbc
=
&
sunxi_usbc_hcd
[
index
];
int
ret
=
0
;
if
(
sunxi_usbc
->
gpio_vbus
!=
-
1
)
ret
urn
gpio_free
(
sunxi_usbc
->
gpio_vbus
);
ret
|=
gpio_free
(
sunxi_usbc
->
gpio_vbus
);
return
0
;
if
(
sunxi_usbc
->
gpio_vbus_det
!=
-
1
)
ret
|=
gpio_free
(
sunxi_usbc
->
gpio_vbus_det
);
return
ret
;
}
void
sunxi_usbc_enable
(
int
index
)
...
...
@@ -258,22 +271,38 @@ void sunxi_usbc_vbus_enable(int index)
{
struct
sunxi_usbc_hcd
*
sunxi_usbc
=
&
sunxi_usbc_hcd
[
index
];
#ifdef AXP_DRIVEBUS
if
(
use_axp_drivebus
(
index
))
axp_drivebus_enable
();
#endif
if
(
sunxi_usbc
->
gpio_vbus
!=
-
1
)
gpio_
direction_output
(
sunxi_usbc
->
gpio_vbus
,
1
);
gpio_
set_value
(
sunxi_usbc
->
gpio_vbus
,
1
);
}
void
sunxi_usbc_vbus_disable
(
int
index
)
{
struct
sunxi_usbc_hcd
*
sunxi_usbc
=
&
sunxi_usbc_hcd
[
index
];
#ifdef AXP_DRIVEBUS
if
(
use_axp_drivebus
(
index
))
axp_drivebus_disable
();
#endif
if
(
sunxi_usbc
->
gpio_vbus
!=
-
1
)
gpio_direction_output
(
sunxi_usbc
->
gpio_vbus
,
0
);
gpio_set_value
(
sunxi_usbc
->
gpio_vbus
,
0
);
}
int
sunxi_usbc_vbus_detect
(
int
index
)
{
struct
sunxi_usbc_hcd
*
sunxi_usbc
=
&
sunxi_usbc_hcd
[
index
];
int
err
,
retries
=
3
;
if
(
sunxi_usbc
->
gpio_vbus_det
==
-
1
)
{
eprintf
(
"Error: invalid vbus detection pin
\n
"
);
return
-
1
;
}
err
=
gpio_get_value
(
sunxi_usbc
->
gpio_vbus_det
);
/*
* Vbus may have been provided by the board and just been turned of
* some milliseconds ago on reset, what we're measuring then is a
* residual charge on Vbus, sleep a bit and try again.
*/
while
(
err
>
0
&&
retries
--
)
{
mdelay
(
100
);
err
=
gpio_get_value
(
sunxi_usbc
->
gpio_vbus_det
);
}
return
err
;
}
arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
View file @
20913018
...
...
@@ -94,6 +94,13 @@
#define SUNXI_TWI0_BASE 0x01c2ac00
#define SUNXI_TWI1_BASE 0x01c2b000
#define SUNXI_TWI2_BASE 0x01c2b400
#ifdef CONFIG_MACH_SUN6I
#define SUNXI_TWI3_BASE 0x01c0b800
#endif
#ifdef CONFIG_MACH_SUN7I
#define SUNXI_TWI3_BASE 0x01c2b800
#define SUNXI_TWI4_BASE 0x01c2c000
#endif
#define SUNXI_CAN_BASE 0x01c2bc00
...
...
arch/arm/include/asm/arch-sunxi/gpio.h
View file @
20913018
...
...
@@ -84,7 +84,7 @@ struct sunxi_gpio_reg {
#define GPIO_CFG_INDEX(pin) (((pin) & 0x1f) >> 3)
#define GPIO_CFG_OFFSET(pin) ((((pin) & 0x1f) & 0x7) << 2)
#define GPIO_DRV_INDEX(pin)
(((pin) & 0x1f) >> 4)
#define GPIO_DRV_INDEX(pin)
(((pin) & 0x1f) >> 4)
#define GPIO_DRV_OFFSET(pin) ((((pin) & 0x1f) & 0xf) << 1)
#define GPIO_PULL_INDEX(pin) (((pin) & 0x1f) >> 4)
...
...
@@ -142,71 +142,77 @@ enum sunxi_gpio_number {
#define SUNXI_GPIO_INPUT 0
#define SUNXI_GPIO_OUTPUT 1
#define SUNXI_GPA0_EMAC 2
#define SUN6I_GPA0_GMAC 2
#define SUN7I_GPA0_GMAC 5
#define SUNXI_GPB0_TWI0 2
#define SUN4I_GPB22_UART0_TX 2
#define SUN4I_GPB23_UART0_RX 2
#define SUN5I_GPB19_UART0_TX 2
#define SUN5I_GPB20_UART0_RX 2
#define SUNXI_GPC6_SDC2 3
#define SUNXI_GPD0_LCD0 2
#define SUNXI_GPD0_LVDS0 3
#define SUNXI_GPF0_SDC0 2
#define SUNXI_GPF2_SDC0 2
#ifdef CONFIG_MACH_SUN8I
#define SUNXI_GPF2_UART0_TX 3
#define SUNXI_GPF4_UART0_RX 3
#else
#define SUNXI_GPF2_UART0_TX 4
#define SUNXI_GPF4_UART0_RX 4
#endif
#define SUN4I_GPG0_SDC1 4
#define SUN5I_GPG3_SDC1 2
#define SUN5I_GPG3_UART1_TX 4
#define SUN5I_GPG4_UART1_RX 4
#define SUN4I_GPH22_SDC1 5
#define SUN6I_GPH20_UART0_TX 2
#define SUN6I_GPH21_UART0_RX 2
#define SUN4I_GPI4_SDC3 2
#define SUNXI_GPA_EMAC 2
#define SUN6I_GPA_GMAC 2
#define SUN7I_GPA_GMAC 5
#define SUN6I_GPA_SDC2 5
#define SUN6I_GPA_SDC3 4
#define SUN4I_GPB_TWI0 2
#define SUN4I_GPB_TWI1 2
#define SUN5I_GPB_TWI1 2
#define SUN4I_GPB_TWI2 2
#define SUN5I_GPB_TWI2 2
#define SUN4I_GPB_UART0 2
#define SUN5I_GPB_UART0 2
#define SUNXI_GPC_SDC2 3
#define SUN6I_GPC_SDC3 4
#define SUN8I_GPD_SDC1 3
#define SUNXI_GPD_LCD0 2
#define SUNXI_GPD_LVDS0 3
#define SUN5I_GPE_SDC2 3
#define SUN8I_GPE_TWI2 3
#define SUNXI_GPF_SDC0 2
#define SUNXI_GPF_UART0 4
#define SUN8I_GPF_UART0 3
#define SUN4I_GPG_SDC1 4
#define SUN5I_GPG_SDC1 2
#define SUN6I_GPG_SDC1 2
#define SUN8I_GPG_SDC1 2
#define SUN6I_GPG_TWI3 2
#define SUN5I_GPG_UART1 4
#define SUN4I_GPH_SDC1 5
#define SUN6I_GPH_TWI0 2
#define SUN8I_GPH_TWI0 2
#define SUN6I_GPH_TWI1 2
#define SUN8I_GPH_TWI1 2
#define SUN6I_GPH_TWI2 2
#define SUN6I_GPH_UART0 2
#define SUNXI_GPI_SDC3 2
#define SUN7I_GPI_TWI3 3
#define SUN7I_GPI_TWI4 3
#define SUN6I_GPL0_R_P2WI_SCK 3
#define SUN6I_GPL1_R_P2WI_SDA 3
#define SUN8I_GPL0_R_RSB_SCK 2
#define SUN8I_GPL1_R_RSB_SDA 2
#define SUN8I_GPL2_R_UART_TX 2
#define SUN8I_GPL3_R_UART_RX 2
#define SUN8I_GPL_R_RSB 2
#define SUN8I_GPL_R_UART 2
#define SUN9I_GPN0_R_RSB_SCK 3
#define SUN9I_GPN1_R_RSB_SDA 3
#define SUN9I_GPN_R_RSB 3
/* GPIO pin pull-up/down config */
#define SUNXI_GPIO_PULL_DISABLE 0
#define SUNXI_GPIO_PULL_UP 1
#define SUNXI_GPIO_PULL_DOWN 2
/* Virtual AXP0 GPIOs */
#define SUNXI_GPIO_AXP0_VBUS_DETECT 8
#define SUNXI_GPIO_AXP0_VBUS_ENABLE 9
void
sunxi_gpio_set_cfgbank
(
struct
sunxi_gpio
*
pio
,
int
bank_offset
,
u32
val
);
void
sunxi_gpio_set_cfgpin
(
u32
pin
,
u32
val
);
int
sunxi_gpio_get_cfgbank
(
struct
sunxi_gpio
*
pio
,
int
bank_offset
);
int
sunxi_gpio_get_cfgpin
(
u32
pin
);
int
sunxi_gpio_set_drv
(
u32
pin
,
u32
val
);
int
sunxi_gpio_set_pull
(
u32
pin
,
u32
val
);
int
sunxi_name_to_gpio_bank
(
const
char
*
name
);
int
sunxi_name_to_gpio
(
const
char
*
name
);
#define name_to_gpio(name) sunxi_name_to_gpio(name)
...
...
arch/arm/include/asm/arch-sunxi/i2c.h
View file @
20913018
...
...
@@ -8,7 +8,22 @@
#include
<asm/arch/cpu.h>
#define CONFIG_I2C_MVTWSI_BASE SUNXI_TWI0_BASE
#ifdef CONFIG_I2C0_ENABLE
#define CONFIG_I2C_MVTWSI_BASE0 SUNXI_TWI0_BASE
#endif
#ifdef CONFIG_I2C1_ENABLE
#define CONFIG_I2C_MVTWSI_BASE1 SUNXI_TWI1_BASE
#endif
#ifdef CONFIG_I2C2_ENABLE
#define CONFIG_I2C_MVTWSI_BASE2 SUNXI_TWI2_BASE
#endif
#ifdef CONFIG_I2C3_ENABLE
#define CONFIG_I2C_MVTWSI_BASE3 SUNXI_TWI3_BASE
#endif
#ifdef CONFIG_I2C4_ENABLE
#define CONFIG_I2C_MVTWSI_BASE4 SUNXI_TWI4_BASE
#endif
/* This is abp0-clk on sun4i/5i/7i / abp1-clk on sun6i/sun8i which is 24MHz */
#define CONFIG_SYS_TCLK 24000000
...
...
arch/arm/include/asm/arch-sunxi/usbc.h
View file @
20913018
...
...
@@ -20,4 +20,5 @@ void sunxi_usbc_enable(int index);
void
sunxi_usbc_disable
(
int
index
);
void
sunxi_usbc_vbus_enable
(
int
index
);
void
sunxi_usbc_vbus_disable
(
int
index
);
int
sunxi_usbc_vbus_detect
(
int
index
);
void
sunxi_usbc_enable_squelch_detect
(
int
index
,
int
enable
);
arch/arm/mach-kirkwood/include/mach/config.h
View file @
20913018
...
...
@@ -44,7 +44,7 @@
#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000
#define CONFIG_NR_DRAM_BANKS_MAX 2
#define CONFIG_I2C_MVTWSI_BASE KW_TWSI_BASE
#define CONFIG_I2C_MVTWSI_BASE
0
KW_TWSI_BASE
#define MV_UART_CONSOLE_BASE KW_UART0_BASE
#define MV_SATA_BASE KW_SATA_BASE
#define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET
...
...
board/sunxi/Kconfig
View file @
20913018
...
...
@@ -212,6 +212,25 @@ config MMC3_CD_PIN
---help---
See MMC0_CD_PIN help text.
config MMC1_PINS
string "Pins for mmc1"
default ""
---help---
Set the pins used for mmc1, when applicable. This takes a string in the
format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
config MMC2_PINS
string "Pins for mmc2"
default ""
---help---
See MMC1_PINS help text.
config MMC3_PINS
string "Pins for mmc3"
default ""
---help---
See MMC1_PINS help text.
config MMC_SUNXI_SLOT_EXTRA
int "mmc extra slot number"
default -1
...
...
@@ -229,7 +248,6 @@ config USB0_VBUS_PIN
config USB0_VBUS_DET
string "Vbus detect pin for usb0 (otg)"
depends on USB_MUSB_SUNXI
default ""
---help---
Set the Vbus detect pin for usb0 (otg). This takes a string in the
...
...
@@ -251,6 +269,44 @@ config USB2_VBUS_PIN
---help---
See USB1_VBUS_PIN help text.
config I2C0_ENABLE
bool "Enable I2C/TWI controller 0"
default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
default n if MACH_SUN6I || MACH_SUN8I
---help---
This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
its clock and setting up the bus. This is especially useful on devices
with slaves connected to the bus or with pins exposed through e.g. an
expansion port/header.
config I2C1_ENABLE
bool "Enable I2C/TWI controller 1"
default n
---help---
See I2C0_ENABLE help text.
config I2C2_ENABLE
bool "Enable I2C/TWI controller 2"
default n
---help---
See I2C0_ENABLE help text.
if MACH_SUN6I || MACH_SUN7I
config I2C3_ENABLE
bool "Enable I2C/TWI controller 3"
default n
---help---
See I2C0_ENABLE help text.
endif
if MACH_SUN7I
config I2C4_ENABLE
bool "Enable I2C/TWI controller 4"
default n
---help---
See I2C0_ENABLE help text.
endif
config VIDEO
boolean "Enable graphical uboot console on HDMI, LCD or VGA"
default y
...
...
board/sunxi/MAINTAINERS
View file @
20913018
...
...
@@ -42,15 +42,18 @@ F: configs/Ippo_q8h_v1_2_defconfig
A20-OLINUXINO-LIME BOARD
M: FUKAUMI Naoki <naobsd@gmail.com>
S: Maintained
F: board/sunxi/dram_a20_olinuxino_l.c
F: configs/A20-OLinuXino-Lime_defconfig
A20-OLINUXINO-LIME2 BOARD
M: Iain Paton <ipaton0@gmail.com>
S: Maintained
F: board/sunxi/dram_a20_olinuxino_l2.c
F: configs/A20-OLinuXino-Lime2_defconfig
AINOL AW1 BOARD
M: Paul Kocialkowski <contact@paulk.fr>
S: Maintained
F: configs/Ainol_AW1_defconfig
AMPE A76 BOARD
M: Paul Kocialkowski <contact@paulk.fr>
S: Maintained
...
...
@@ -84,11 +87,20 @@ M: Chen-Yu Tsai <wens@csie.org>
S: Maintained
F: configs/Hummingbird_A31_defconfig
INET-86VS BOARD
INET 3F BOARD
M: Paul Kocialkowski <contact@paulk.fr>
S: Maintained
F: configs/iNet_3F_defconfig
INET 3W BOARD
M: Paul Kocialkowski <contact@paulk.fr>
S: Maintained
F: configs/iNet_3W_defconfig
INET 86VS BOARD
M: Michal Suchanek <hramrach@gmail.com>
S: Maintained
F: board/sunxi/dram_inet_86vs.c
F: configs/Inet_86VS_defconfig
F: configs/iNet_86VS_defconfig
IPPO-Q8H-V5 BOARD
M: Chen-Yu Tsai <wens@csie.org>
...
...
@@ -120,6 +132,11 @@ M: Ian Campbell <ijc@hellion.org.uk>
S: Maintained
F: configs/Mele_M5_defconfig
MIXTILE-LOFTQ BOARD
M: Phil Han <pengphei@sina.com>
S: Maintained
F: configs/mixtile_loftq_defconfig
MK808C BOARD
M: Marcus Cooper <codekipper@gmail.com>
S: Maintained
...
...
@@ -144,3 +161,8 @@ WEXLER-TAB7200 BOARD
M: Aleksei Mamlin <mamlinav@gmail.com>
S: Maintained
F: configs/Wexler_TAB7200_defconfig
YONES TOPTECH BD1078 BOARD
M: Paul Kocialkowski <contact@paulk.fr>
S: Maintained
F: configs/Yones_Toptech_BD1078_defconfig
board/sunxi/board.c
View file @
20913018
...
...
@@ -71,42 +71,163 @@ int dram_init(void)
static
void
mmc_pinmux_setup
(
int
sdc
)
{
unsigned
int
pin
;
__maybe_unused
int
pins
;
switch
(
sdc
)
{
case
0
:
/*
D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4
-PF5 */
/*
SDC0: PF0
-PF5 */
for
(
pin
=
SUNXI_GPF
(
0
);
pin
<=
SUNXI_GPF
(
5
);
pin
++
)
{
sunxi_gpio_set_cfgpin
(
pin
,
SUNXI_GPF
0
_SDC0
);
sunxi_gpio_set_cfgpin
(
pin
,
SUNXI_GPF_SDC0
);
sunxi_gpio_set_pull
(
pin
,
SUNXI_GPIO_PULL_UP
);
sunxi_gpio_set_drv
(
pin
,
2
);
}
break
;
case
1
:
/* CMD-PG3, CLK-PG4, D0~D3-PG5-8 */
pins
=
sunxi_name_to_gpio_bank
(
CONFIG_MMC1_PINS
);
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
if
(
pins
==
SUNXI_GPIO_H
)
{
/* SDC1: PH22-PH-27 */
for
(
pin
=
SUNXI_GPH
(
22
);
pin
<=
SUNXI_GPH
(
27
);
pin
++
)
{
sunxi_gpio_set_cfgpin
(
pin
,
SUN4I_GPH_SDC1
);
sunxi_gpio_set_pull
(
pin
,
SUNXI_GPIO_PULL_UP
);
sunxi_gpio_set_drv
(
pin
,
2
);
}
}
else
{
/* SDC1: PG0-PG5 */
for
(
pin
=
SUNXI_GPG
(
0
);
pin
<=
SUNXI_GPG
(
5
);
pin
++
)
{
sunxi_gpio_set_cfgpin
(
pin
,
SUN4I_GPG_SDC1
);
sunxi_gpio_set_pull
(
pin
,
SUNXI_GPIO_PULL_UP
);
sunxi_gpio_set_drv
(
pin
,
2
);
}
}
#elif defined(CONFIG_MACH_SUN5I)
/* SDC1: PG3-PG8 */
for
(
pin
=
SUNXI_GPG
(
3
);
pin
<=
SUNXI_GPG
(
8
);
pin
++
)
{
sunxi_gpio_set_cfgpin
(
pin
,
SUN5I_GPG3_SDC1
);
sunxi_gpio_set_cfgpin
(
pin
,
SUN5I_GPG_SDC1
);
sunxi_gpio_set_pull
(
pin
,
SUNXI_GPIO_PULL_UP
);
sunxi_gpio_set_drv
(
pin
,
2
);
}
#elif defined(CONFIG_MACH_SUN6I)
/* SDC1: PG0-PG5 */
for
(
pin
=
SUNXI_GPG
(
0
);
pin
<=
SUNXI_GPG
(
5
);
pin
++
)
{
sunxi_gpio_set_cfgpin
(
pin
,
SUN6I_GPG_SDC1
);
sunxi_gpio_set_pull
(
pin
,
SUNXI_GPIO_PULL_UP
);
sunxi_gpio_set_drv
(
pin
,
2
);
}
#elif defined(CONFIG_MACH_SUN8I)
if
(
pins
==
SUNXI_GPIO_D
)
{
/* SDC1: PD2-PD7 */
for
(
pin
=
SUNXI_GPD
(
2
);
pin
<=
SUNXI_GPD
(
7
);
pin
++
)
{
sunxi_gpio_set_cfgpin
(
pin
,
SUN8I_GPD_SDC1
);
sunxi_gpio_set_pull
(
pin
,
SUNXI_GPIO_PULL_UP
);
sunxi_gpio_set_drv
(
pin
,
2
);
}
}
else
{
/* SDC1: PG0-PG5 */
for
(
pin
=
SUNXI_GPG
(
0
);
pin
<=
SUNXI_GPG
(
5
);
pin
++
)
{
sunxi_gpio_set_cfgpin
(
pin
,
SUN8I_GPG_SDC1
);
sunxi_gpio_set_pull
(
pin
,
SUNXI_GPIO_PULL_UP
);
sunxi_gpio_set_drv
(
pin
,
2
);
}
}
#endif
break
;
case
2
:
/* CMD-PC6, CLK-PC7, D0-PC8, D1-PC9, D2-PC10, D3-PC11 */
pins
=
sunxi_name_to_gpio_bank
(
CONFIG_MMC2_PINS
);
#if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
/* SDC2: PC6-PC11 */
for
(
pin
=
SUNXI_GPC
(
6
);
pin
<=
SUNXI_GPC
(
11
);
pin
++
)
{
sunxi_gpio_set_cfgpin
(
pin
,
SUNXI_GPC6_SDC2
);
sunxi_gpio_set_cfgpin
(
pin
,
SUNXI_GPC_SDC2
);
sunxi_gpio_set_pull
(
pin
,
SUNXI_GPIO_PULL_UP
);
sunxi_gpio_set_drv
(
pin
,
2
);
}
#elif defined(CONFIG_MACH_SUN5I)
if
(
pins
==
SUNXI_GPIO_E
)
{
/* SDC2: PE4-PE9 */
for
(
pin
=
SUNXI_GPE
(
4
);
pin
<=
SUNXI_GPD
(
9
);
pin
++
)
{
sunxi_gpio_set_cfgpin
(
pin
,
SUN5I_GPE_SDC2
);
sunxi_gpio_set_pull
(
pin
,
SUNXI_GPIO_PULL_UP
);