Commit 21008ad6 authored by Tom Rini's avatar Tom Rini
Browse files

Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx



Conflicts:
	drivers/mmc/fsl_esdhc.c
Signed-off-by: default avatarTom Rini <trini@ti.com>
parents d3e488ea 3b4b9a33
......@@ -71,6 +71,22 @@ enum srds_prtcl {
INTERLAKEN,
QSGMII_SW1_A, /* Indicates ports on L2 Switch */
QSGMII_SW1_B,
SGMII_2500_FM1_DTSEC1,
SGMII_2500_FM1_DTSEC2,
SGMII_2500_FM1_DTSEC3,
SGMII_2500_FM1_DTSEC4,
SGMII_2500_FM1_DTSEC5,
SGMII_2500_FM1_DTSEC6,
SGMII_2500_FM1_DTSEC9,
SGMII_2500_FM1_DTSEC10,
SGMII_2500_FM2_DTSEC1,
SGMII_2500_FM2_DTSEC2,
SGMII_2500_FM2_DTSEC3,
SGMII_2500_FM2_DTSEC4,
SGMII_2500_FM2_DTSEC5,
SGMII_2500_FM2_DTSEC6,
SGMII_2500_FM2_DTSEC9,
SGMII_2500_FM2_DTSEC10,
};
enum srds {
......
The T2080QDS is a high-performance computing evaluation, development and
test platform supporting the T2080 QorIQ Power Architecture processor.
T2080 SoC Overview
------------------
The T2080 QorIQ multicore processor combines four dual-threaded e6500 Power
Architecture processor cores with high-performance datapath acceleration
logic and network and peripheral bus interfaces required for networking,
telecom/datacom, wireless infrastructure, and mil/aerospace applications.
T2080 includes the following functions and features:
- Four dual-threads 64-bit Power architecture e6500 cores, up to 1.8GHz
- 2MB L2 cache and 512KB CoreNet platform cache (CPC)
- Hierarchical interconnect fabric
- One 32-/64-bit DDR3/3L SDRAM memory controllers with ECC and interleaving
- Data Path Acceleration Architecture (DPAA) incorporating acceleration
- 16 SerDes lanes up to 10.3125 GHz
- 8 Ethernet interfaces, supporting combinations of the following:
- Up to four 10 Gbps Ethernet MACs
- Up to eight 1 Gbps Ethernet MACs
- Up to four 2.5 Gbps Ethernet MACs
- High-speed peripheral interfaces
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
- Two Serial RapidIO 2.0 controllers/ports running at up to 5 GHz
- Additional peripheral interfaces
- Two serial ATA (SATA 2.0) controllers
- Two high-speed USB 2.0 controllers with integrated PHY
- Enhanced secure digital host controller (SD/SDHC/SDXC/eMMC)
- Enhanced serial peripheral interface (eSPI)
- Four I2C controllers
- Four 2-pin UARTs or two 4-pin UARTs
- Integrated Flash Controller supporting NAND and NOR flash
- Three eight-channel DMA engines
- Support for hardware virtualization and partitioning enforcement
- QorIQ Platform's Trust Architecture 2.0
Differences between T2080 and T2081
-----------------------------------
Feature T2080 T2081
1G Ethernet numbers: 8 6
10G Ethernet numbers: 4 2
SerDes lanes: 16 8
Serial RapidIO,RMan: 2 no
SATA Controller: 2 no
Aurora: yes no
SoC Package: 896-pins 780-pins
T2080QDS feature overview
-------------------------
Processor:
- T2080 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
Memory:
- Single memory controller capable of supporting DDR3 and DDR3-LV devices
- Two DDR3 DIMMs up to 4GB, Dual rank @ 2133MT/s and ECC support
Ethernet interfaces:
- Two 1Gbps RGMII on-board ports
- Four 10Gbps XFI on-board cages
- 1Gbps/2.5Gbps SGMII Riser card
- 10Gbps XAUI Riser card
Accelerator:
- DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
SerDes:
- 16 lanes up to 10.3125GHz
- Supports Aurora debug, PEX, SATA, SGMII, sRIO, HiGig, XFI and XAUI
IFC:
- 128MB NOR Flash, 512MB NAND Flash, PromJet debug port and FPGA
eSPI:
- Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
USB:
- Two USB2.0 ports with internal PHY (one Type-A + one micro Type-AB)
PCIE:
- Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
SATA:
- Two SATA 2.0 ports on-board
SRIO:
- Two Serial RapidIO 2.0 ports up to 5 GHz
eSDHC:
- Supports SD/SDHC/SDXC/eMMC Card
I2C:
- Four I2C controllers.
UART:
- Dual 4-pins UART serial ports
System Logic:
- QIXIS-II FPGA system controll
Debug Features:
- Support Legacy, COP/JTAG, Aurora, Event and EVT
XFI:
- XFI is supported on T2080QDS through Lane A/B/C/D on Serdes 1 routed to
a on-board SFP+ cages, which to house optical module (fiber cable) or
direct attach cable(copper), the copper cable is used to emulate
10GBASE-KR scenario.
So, for XFI usage, there are two scenarios, one will use fiber cable,
another will use copper cable. An hwconfig env "fsl_10gkr_copper" is
introduced to indicate a XFI port will use copper cable, and U-boot
will fixup the dtb accordingly.
It's used as: fsl_10gkr_copper:<10g_mac_name>
The <10g_mac_name> can be fm1_10g1, fm1_10g2, fm1_10g3, fm1_10g4, they
do not have to be coexist in hwconfig. If a MAC is listed in the env
"fsl_10gkr_copper", it will use copper cable, otherwise, fiber cable
will be used by default.
for ex. set "fsl_10gkr_copper:fm1_10g1,fm1_10g2,fm1_10g3,fm1_10g4" in
hwconfig, then both four XFI ports will use copper cable.
set "fsl_10gkr_copper:fm1_10g1,fm1_10g2" in hwconfig, then first two
XFI ports will use copper cable, the other two XFI ports will use fiber
cable.
1000BASE-KX(1G-KX):
- T2080QDS can support 1G-KX by using SGMII protocol, but serdes lane
runs in 1G-KX mode. By default, the lane runs in SGMII mode, to set a lane
in 1G-KX mode, need to set corresponding bit in SerDes Protocol Configuration
Register 1 (PCCR1), and U-boot fixup the dtb for kernel to do proper
initialization.
Hwconfig "fsl_1gkx" is used to indicate a lane runs in 1G-KX mode, MAC
1/2/5/6/9/10 are available for 1G-KX, MAC 3/4 run in RGMII mode. To set a
MAC to use 1G-KX mode, set its' corresponding env in "fsl_1gkx", 'fm1_1g1'
stands for MAC 1, 'fm1_1g2' stands for MAC 2, etc.
For ex. set "fsl_1gkx:fm1_1g1,fm1_1g2,fm1_1g5,fm1_1g6,fm1_1g9,fm1_1g10" in
hwconfig, MAC 1/2/5/6/9/10 will use 1G-KX mode.
System Memory map
----------------
Start Address End Address Description Size
0xF_FFDF_0000 0xF_FFDF_0FFF IFC - CPLD 4KB
0xF_FF80_0000 0xF_FF80_FFFF IFC - NAND Flash 64KB
0xF_FE00_0000 0xF_FEFF_FFFF CCSRBAR 16MB
0xF_F803_0000 0xF_F803_FFFF PCI Express 4 I/O Space 64KB
0xF_F802_0000 0xF_F802_FFFF PCI Express 3 I/O Space 64KB
0xF_F801_0000 0xF_F801_FFFF PCI Express 2 I/O Space 64KB
0xF_F800_0000 0xF_F800_FFFF PCI Express 1 I/O Space 64KB
0xF_F600_0000 0xF_F7FF_FFFF Queue manager software portal 32MB
0xF_F400_0000 0xF_F5FF_FFFF Buffer manager software portal 32MB
0xF_E800_0000 0xF_EFFF_FFFF IFC - NOR Flash 128MB
0xF_0000_0000 0xF_003F_FFFF DCSR 4MB
0xC_4000_0000 0xC_4FFF_FFFF PCI Express 4 Mem Space 256MB
0xC_3000_0000 0xC_3FFF_FFFF PCI Express 3 Mem Space 256MB
0xC_2000_0000 0xC_2FFF_FFFF PCI Express 2 Mem Space 256MB
0xC_0000_0000 0xC_1FFF_FFFF PCI Express 1 Mem Space 512MB
0x0_0000_0000 0x0_ffff_ffff DDR 4GB
128M NOR Flash memory Map
-------------------------
Start Address End Address Definition Max size
0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB
0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB
0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB
0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB
0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
0xE8000000 0xE801FFFF RCW (current bank) 128KB
Software configurations and board settings
------------------------------------------
1. NOR boot:
a. build NOR boot image
$ make T2080QDS_config
$ make
b. program u-boot.bin image to NOR flash
=> tftp 1000000 u-boot.bin
=> pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
set SW1[1:8] = '00010011', SW2[1] = '1', SW6[1:4] = '0000' for NOR boot
Switching between default bank0 and alternate bank4 on NOR flash
To change boot source to vbank4:
by software: run command 'qixis_reset altbank' in u-boot.
by DIP-switch: set SW6[1:4] = '0100'
To change boot source to vbank0:
by software: run command 'qixis_reset' in u-boot.
by DIP-Switch: set SW6[1:4] = '0000'
2. NAND Boot:
a. build PBL image for NAND boot
$ make T2080QDS_NAND_config
$ make
b. program u-boot-with-spl-pbl.bin to NAND flash
=> tftp 1000000 u-boot-with-spl-pbl.bin
=> nand erase 0 $filesize
=> nand write 1000000 0 $filesize
set SW1[1:8] = '10000010', SW2[1] = '0' and SW6[1:4] = '1001' for NAND boot
3. SPI Boot:
a. build PBL image for SPI boot
$ make T2080QDS_SPIFLASH_config
$ make
b. program u-boot-with-spl-pbl.bin to SPI flash
=> tftp 1000000 u-boot-with-spl-pbl.bin
=> sf probe 0
=> sf erase 0 f0000
=> sf write 1000000 0 $filesize
set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
4. SD Boot:
a. build PBL image for SD boot
$ make T2080QDS_SDCARD_config
$ make
b. program u-boot-with-spl-pbl.bin to SD/MMC card
=> tftp 1000000 u-boot-with-spl-pbl.bin
=> mmc write 1000000 8 0x800
=> tftp 1000000 fsl_fman_ucode_T2080_xx.bin
=> mmc write 1000000 0x820 80
set SW1[1:8] = '00100000', SW2[1] = '0' for SD boot
2-stage NAND/SPI/SD boot loader
-------------------------------
PBL initializes the internal CPC-SRAM and copy SPL(160K) to SRAM.
SPL further initializes DDR using SPD and environment variables
and copy u-boot(768 KB) from NAND/SPI/SD device to DDR.
Finally SPL transers control to u-boot for futher booting.
SPL has following features:
- Executes within 256K
- No relocation required
Run time view of SPL framework
-------------------------------------------------
|Area | Address |
-------------------------------------------------
|SecureBoot header | 0xFFFC0000 (32KB) |
-------------------------------------------------
|GD, BD | 0xFFFC8000 (4KB) |
-------------------------------------------------
|ENV | 0xFFFC9000 (8KB) |
-------------------------------------------------
|HEAP | 0xFFFCB000 (50KB) |
-------------------------------------------------
|STACK | 0xFFFD8000 (22KB) |
-------------------------------------------------
|U-boot SPL | 0xFFFD8000 (160KB) |
-------------------------------------------------
NAND Flash memory Map on T2080QDS
--------------------------------------------------------------
Start End Definition Size
0x000000 0x0FFFFF u-boot img 1MB (2 blocks)
0x100000 0x17FFFF u-boot env 512KB (1 block)
0x180000 0x1FFFFF FMAN ucode 512KB (1 block)
Micro SD Card memory Map on T2080QDS
----------------------------------------------------
Block #blocks Definition Size
0x008 2048 u-boot img 1MB
0x800 0016 u-boot env 8KB
0x820 0128 FMAN ucode 64KB
SPI Flash memory Map on T2080QDS
----------------------------------------------------
Start End Definition Size
0x000000 0x0FFFFF u-boot img 1MB
0x100000 0x101FFF u-boot env 8KB
0x110000 0x11FFFF FMAN ucode 64KB
How to update the ucode of Freescale FMAN
-----------------------------------------
=> tftp 1000000 fsl_fman_ucode_t2080_xx.bin
=> pro off all;erase 0xeff00000 0xeff1ffff;cp 1000000 0xeff00000 $filesize
For more details, please refer to T2080QDS User Guide and access
website www.freescale.com and Freescale QorIQ SDK Infocenter document.
......@@ -23,6 +23,7 @@
#include <phy.h>
#include <asm/fsl_dtsec.h>
#include <asm/fsl_serdes.h>
#include <hwconfig.h>
#include "../common/qixis.h"
#include "../common/fman.h"
#include "t208xqds_qixis.h"
......@@ -46,6 +47,15 @@
#define EMI2 8
#endif
#define PCCR1_SGMIIA_KX_MASK 0x00008000
#define PCCR1_SGMIIB_KX_MASK 0x00004000
#define PCCR1_SGMIIC_KX_MASK 0x00002000
#define PCCR1_SGMIID_KX_MASK 0x00001000
#define PCCR1_SGMIIE_KX_MASK 0x00000800
#define PCCR1_SGMIIF_KX_MASK 0x00000400
#define PCCR1_SGMIIG_KX_MASK 0x00000200
#define PCCR1_SGMIIH_KX_MASK 0x00000100
static int mdio_mux[NUM_FM_PORTS];
static const char * const mdio_names[] = {
......@@ -187,8 +197,18 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
{
int phy;
char alias[20];
char lane_mode[2][20] = {"1000BASE-KX", "10GBASE-KR"};
char buf[32] = "serdes-1,";
struct fixed_link f_link;
int media_type = 0;
int off;
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#ifdef CONFIG_T2080QDS
serdes_corenet_t *srds_regs =
(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1);
#endif
u32 srds_s1 = in_be32(&gur->rcwsr[4]) &
FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
......@@ -199,9 +219,54 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
switch (port) {
#if defined(CONFIG_T2080QDS)
case FM1_DTSEC1:
if (hwconfig_sub("fsl_1gkx", "fm1_1g1")) {
media_type = 1;
fdt_set_phy_handle(fdt, compat, addr,
"phy_1gkx1");
fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio1");
sprintf(buf, "%s%s%s", buf, "lane-c,",
(char *)lane_mode[0]);
out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
PCCR1_SGMIIH_KX_MASK);
break;
}
case FM1_DTSEC2:
if (hwconfig_sub("fsl_1gkx", "fm1_1g2")) {
media_type = 1;
fdt_set_phy_handle(fdt, compat, addr,
"phy_1gkx2");
fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio2");
sprintf(buf, "%s%s%s", buf, "lane-d,",
(char *)lane_mode[0]);
out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
PCCR1_SGMIIG_KX_MASK);
break;
}
case FM1_DTSEC9:
if (hwconfig_sub("fsl_1gkx", "fm1_1g9")) {
media_type = 1;
fdt_set_phy_handle(fdt, compat, addr,
"phy_1gkx9");
fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio9");
sprintf(buf, "%s%s%s", buf, "lane-a,",
(char *)lane_mode[0]);
out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
PCCR1_SGMIIE_KX_MASK);
break;
}
case FM1_DTSEC10:
if (hwconfig_sub("fsl_1gkx", "fm1_1g10")) {
media_type = 1;
fdt_set_phy_handle(fdt, compat, addr,
"phy_1gkx10");
fdt_status_okay_by_alias(fdt,
"1gkx_pcs_mdio10");
sprintf(buf, "%s%s%s", buf, "lane-b,",
(char *)lane_mode[0]);
out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
PCCR1_SGMIIF_KX_MASK);
break;
}
if (mdio_mux[port] == EMI1_SLOT2) {
sprintf(alias, "phy_sgmii_s2_%x", phy);
fdt_set_phy_handle(fdt, compat, addr, alias);
......@@ -213,7 +278,29 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
}
break;
case FM1_DTSEC5:
if (hwconfig_sub("fsl_1gkx", "fm1_1g5")) {
media_type = 1;
fdt_set_phy_handle(fdt, compat, addr,
"phy_1gkx5");
fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio5");
sprintf(buf, "%s%s%s", buf, "lane-g,",
(char *)lane_mode[0]);
out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
PCCR1_SGMIIC_KX_MASK);
break;
}
case FM1_DTSEC6:
if (hwconfig_sub("fsl_1gkx", "fm1_1g6")) {
media_type = 1;
fdt_set_phy_handle(fdt, compat, addr,
"phy_1gkx6");
fdt_status_okay_by_alias(fdt, "1gkx_pcs_mdio6");
sprintf(buf, "%s%s%s", buf, "lane-h,",
(char *)lane_mode[0]);
out_be32(&srds_regs->srdspccr1, srds1_pccr1 |
PCCR1_SGMIID_KX_MASK);
break;
}
if (mdio_mux[port] == EMI1_SLOT1) {
sprintf(alias, "phy_sgmii_s1_%x", phy);
fdt_set_phy_handle(fdt, compat, addr, alias);
......@@ -257,6 +344,12 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
default:
break;
}
if (media_type) {
/* set property for 1000BASE-KX in dtb */
off = fdt_node_offset_by_compat_reg(fdt,
"fsl,fman-memac-mdio", addr + 0x1000);
fdt_setprop_string(fdt, off, "lane-instance", buf);
}
} else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII) {
switch (srds_s1) {
......@@ -265,15 +358,77 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
case 0x6c:
case 0x6d:
case 0x71:
f_link.phy_id = port;
f_link.duplex = 1;
f_link.link_speed = 10000;
f_link.pause = 0;
f_link.asym_pause = 0;
/* no PHY for XFI */
fdt_delprop(fdt, offset, "phy-handle");
fdt_setprop(fdt, offset, "fixed-link", &f_link,
sizeof(f_link));
/*
* if the 10G is XFI, check hwconfig to see what is the
* media type, there are two types, fiber or copper,
* fix the dtb accordingly.
*/
switch (port) {
case FM1_10GEC1:
if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g1")) {
/* it's MAC9 */
media_type = 1;
fdt_set_phy_handle(fdt, compat, addr,
"phy_xfi9");
fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio9");
sprintf(buf, "%s%s%s", buf, "lane-a,",
(char *)lane_mode[1]);
}
break;
case FM1_10GEC2:
if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g2")) {
/* it's MAC10 */
media_type = 1;
fdt_set_phy_handle(fdt, compat, addr,
"phy_xfi10");
fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio10");
sprintf(buf, "%s%s%s", buf, "lane-b,",
(char *)lane_mode[1]);
}
break;
case FM1_10GEC3:
if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g3")) {
/* it's MAC1 */
media_type = 1;
fdt_set_phy_handle(fdt, compat, addr,
"phy_xfi1");
fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio1");
sprintf(buf, "%s%s%s", buf, "lane-c,",
(char *)lane_mode[1]);
}
break;
case FM1_10GEC4:
if (hwconfig_sub("fsl_10gkr_copper", "fm1_10g4")) {
/* it's MAC2 */
media_type = 1;
fdt_set_phy_handle(fdt, compat, addr,
"phy_xfi2");
fdt_status_okay_by_alias(fdt, "xfi_pcs_mdio2");
sprintf(buf, "%s%s%s", buf, "lane-d,",
(char *)lane_mode[1]);
}
break;
default:
return;
}
if (!media_type) {
/* fixed-link is used for XFI fiber cable */
f_link.phy_id = port;
f_link.duplex = 1;
f_link.link_speed = 10000;
f_link.pause = 0;
f_link.asym_pause = 0;
fdt_delprop(fdt, offset, "phy-handle");
fdt_setprop(fdt, offset, "fixed-link", &f_link,
sizeof(f_link));
} else {
/* set property for copper cable */
off = fdt_node_offset_by_compat_reg(fdt,
"fsl,fman-memac-mdio", addr + 0x1000);
fdt_setprop_string(fdt, off,
"lane-instance", buf);
}
break;
default:
break;
......
......@@ -618,7 +618,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
#endif
cfg->cfg.f_min = 400000;
cfg->cfg.f_max = min(gd->arch.sdhc_clk, (u32)52000000);
cfg->cfg.f_max = min(cfg->sdhc_clk, (u32)52000000);
cfg->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
......
......@@ -39,9 +39,14 @@ static void dtsec_configure_serdes(struct fm_eth *priv)
u32 value;
struct mii_dev bus;
bus.priv = priv->mac->phyregs;
bool sgmii_2500 = (priv->enet_if ==
PHY_INTERFACE_MODE_SGMII_2500) ? true : false;
/* SGMII IF mode + AN enable only for 1G SGMII, not for 2.5G */
value = PHY_SGMII_IF_MODE_SGMII;
if (!sgmii_2500)
value |= PHY_SGMII_IF_MODE_AN;
/* SGMII IF mode + AN enable */
value = PHY_SGMII_IF_MODE_AN | PHY_SGMII_IF_MODE_SGMII;
memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x14, value);
/* Dev ability according to SGMII specification */
......@@ -54,7 +59,9 @@ static void dtsec_configure_serdes(struct fm_eth *priv)
memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0x12, 0xd40);
/* Restart AN */
value = PHY_SGMII_CR_DEF_VAL | PHY_SGMII_CR_RESET_AN;
value = PHY_SGMII_CR_DEF_VAL;
if (!sgmii_2500)
value |= PHY_SGMII_CR_RESET_AN;
memac_mdio_write(&bus, 0, MDIO_DEVAD_NONE, 0, value);
#else
struct dtsec *regs = priv->mac->base;
......@@ -83,7 +90,8 @@ static void dtsec_init_phy(struct eth_device *dev)
out_be32(&regs->tbipa, CONFIG_SYS_TBIPA_VALUE);
#endif
if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII)
if (fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII ||
fm_eth->enet_if == PHY_INTERFACE_MODE_SGMII_2500)
dtsec_configure_serdes(fm_eth);
}
......
......@@ -387,6 +387,11 @@ extern int board_pci_host_broken(void);
#define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */
#define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_PCI_PNP /* do pci plug-and-play */
......
......@@ -685,6 +685,11 @@
#define CONFIG_ENV_OVERWRITE
#define CONFIG_HAS_FSL_DR_USB
#define CONFIG_CMD_USB
#define CONFIG_USB_STORAGE
#define CONFIG_USB_EHCI
#define CONFIG_USB_EHCI_FSL
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_NETDEV "eth1"
......
......@@ -374,6 +374,49 @@ extern unsigned long get_clock_freq(void);
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"netdev=eth0\0" \
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
"loadaddr=1000000\0" \
"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
"tftpflash=tftpboot $loadaddr $uboot; " \
"protect off $ubootaddr +$filesize; " \
"erase $ubootaddr +$filesize; " \
"cp.b $loadaddr $ubootaddr $filesize; " \
"protect on $ubootaddr +$filesize; " \
"cmp.b $loadaddr $ubootaddr $filesize\0" \
"consoledev=ttyS0\0" \
"ramdiskaddr=2000000\0" \
"ramdiskfile=rootfs.ext2.gz.uboot\0" \
"fdtaddr=c00000\0" \
"fdtfile=p1023rdb.dtb\0" \
"othbootargs=ramdisk_size=600000\0" \
"bdev=sda1\0" \
"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
#define CONFIG_HDBOOT \
"setenv bootargs root=/dev/$bdev rw " \
"console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \
"bootm $loadaddr - $fdtaddr"
#define CONFIG_NFSBOOTCOMMAND \