Commit 2218c54b authored by Tom Rini's avatar Tom Rini

Merge branch 'master' of git://git.denx.de/u-boot-imx

parents cc4228f9 ed3fb1fb
......@@ -18,6 +18,8 @@ enum pll_clocks {
PLL_BUS, /* System Bus PLL*/
PLL_USBOTG, /* OTG USB PLL */
PLL_ENET, /* ENET PLL */
PLL_AUDIO, /* AUDIO PLL */
PLL_VIDEO, /* AUDIO PLL */
};
struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
......@@ -204,7 +206,7 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num)
}
static u32 decode_pll(enum pll_clocks pll, u32 infreq)
{
u32 div;
u32 div, test_div, pll_num, pll_denom;
switch (pll) {
case PLL_SYS:
......@@ -227,6 +229,44 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq)
div &= BM_ANADIG_PLL_ENET_DIV_SELECT;
return 25000000 * (div + (div >> 1) + 1);
case PLL_AUDIO:
div = __raw_readl(&imx_ccm->analog_pll_audio);
if (!(div & BM_ANADIG_PLL_AUDIO_ENABLE))
return 0;
/* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
if (div & BM_ANADIG_PLL_AUDIO_BYPASS)
return MXC_HCLK;
pll_num = __raw_readl(&imx_ccm->analog_pll_audio_num);
pll_denom = __raw_readl(&imx_ccm->analog_pll_audio_denom);
test_div = (div & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) >>
BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT;
div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT;
if (test_div == 3) {
debug("Error test_div\n");
return 0;
}
test_div = 1 << (2 - test_div);
return infreq * (div + pll_num / pll_denom) / test_div;
case PLL_VIDEO:
div = __raw_readl(&imx_ccm->analog_pll_video);
if (!(div & BM_ANADIG_PLL_VIDEO_ENABLE))
return 0;
/* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */
if (div & BM_ANADIG_PLL_VIDEO_BYPASS)
return MXC_HCLK;
pll_num = __raw_readl(&imx_ccm->analog_pll_video_num);
pll_denom = __raw_readl(&imx_ccm->analog_pll_video_denom);
test_div = (div & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) >>
BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT;
if (test_div == 3) {
debug("Error test_div\n");
return 0;
}
test_div = 1 << (2 - test_div);
return infreq * (div + pll_num / pll_denom) / test_div;
default:
return 0;
}
......@@ -437,7 +477,7 @@ static u32 get_mmdc_ch0_clk(void)
u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);
u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);
u32 freq, podf, per2_clk2_podf;
u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div;
if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) ||
is_cpu_type(MXC_CPU_MX6SL)) {
......@@ -472,8 +512,21 @@ static u32 get_mmdc_ch0_clk(void)
freq = mxc_get_pll_pfd(PLL_BUS, 0);
break;
case 3:
/* static / 2 divider */
freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2;
pmu_misc2_audio_div = PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm->pmu_misc2));
switch (pmu_misc2_audio_div) {
case 0:
case 2:
pmu_misc2_audio_div = 1;
break;
case 1:
pmu_misc2_audio_div = 2;
break;
case 3:
pmu_misc2_audio_div = 4;
break;
}
freq = decode_pll(PLL_AUDIO, MXC_HCLK) /
pmu_misc2_audio_div;
break;
}
}
......
......@@ -130,6 +130,24 @@ static void init_csu(void)
writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4);
}
static void imx_enet_mdio_fixup(void)
{
struct iomuxc_gpr_base_regs *gpr_regs =
(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;
/*
* The management data input/output (MDIO) requires open-drain,
* i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports
* this feature. So to TO1.1, need to enable open drain by setting
* bits GPR0[8:7].
*/
if (soc_rev() >= CHIP_REV_1_1) {
setbits_le32(&gpr_regs->gpr[0],
IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK);
}
}
int arch_cpu_init(void)
{
init_aips();
......@@ -138,6 +156,8 @@ int arch_cpu_init(void)
/* Disable PDE bit of WMCR register */
imx_set_wdog_powerdown(false);
imx_enet_mdio_fixup();
#ifdef CONFIG_APBH_DMA
/* Start APBH DMA */
mxs_dma_init();
......
......@@ -103,6 +103,97 @@ struct mxc_ccm_reg {
u32 analog_pfd_528_set;
u32 analog_pfd_528_clr;
u32 analog_pfd_528_tog;
/* PMU Memory Map/Register Definition */
u32 pmu_reg_1p1;
u32 pmu_reg_1p1_set;
u32 pmu_reg_1p1_clr;
u32 pmu_reg_1p1_tog;
u32 pmu_reg_3p0;
u32 pmu_reg_3p0_set;
u32 pmu_reg_3p0_clr;
u32 pmu_reg_3p0_tog;
u32 pmu_reg_2p5;
u32 pmu_reg_2p5_set;
u32 pmu_reg_2p5_clr;
u32 pmu_reg_2p5_tog;
u32 pmu_reg_core;
u32 pmu_reg_core_set;
u32 pmu_reg_core_clr;
u32 pmu_reg_core_tog;
u32 pmu_misc0;
u32 pmu_misc0_set;
u32 pmu_misc0_clr;
u32 pmu_misc0_tog;
u32 pmu_misc1;
u32 pmu_misc1_set;
u32 pmu_misc1_clr;
u32 pmu_misc1_tog;
u32 pmu_misc2;
u32 pmu_misc2_set;
u32 pmu_misc2_clr;
u32 pmu_misc2_tog;
/* TEMPMON Memory Map/Register Definition */
u32 tempsense0;
u32 tempsense0_set;
u32 tempsense0_clr;
u32 tempsense0_tog;
u32 tempsense1;
u32 tempsense1_set;
u32 tempsense1_clr;
u32 tempsense1_tog;
/* USB Analog Memory Map/Register Definition */
u32 usb1_vbus_detect;
u32 usb1_vbus_detect_set;
u32 usb1_vbus_detect_clr;
u32 usb1_vbus_detect_tog;
u32 usb1_chrg_detect;
u32 usb1_chrg_detect_set;
u32 usb1_chrg_detect_clr;
u32 usb1_chrg_detect_tog;
u32 usb1_vbus_det_stat;
u32 usb1_vbus_det_stat_set;
u32 usb1_vbus_det_stat_clr;
u32 usb1_vbus_det_stat_tog;
u32 usb1_chrg_det_stat;
u32 usb1_chrg_det_stat_set;
u32 usb1_chrg_det_stat_clr;
u32 usb1_chrg_det_stat_tog;
u32 usb1_loopback;
u32 usb1_loopback_set;
u32 usb1_loopback_clr;
u32 usb1_loopback_tog;
u32 usb1_misc;
u32 usb1_misc_set;
u32 usb1_misc_clr;
u32 usb1_misc_tog;
u32 usb2_vbus_detect;
u32 usb2_vbus_detect_set;
u32 usb2_vbus_detect_clr;
u32 usb2_vbus_detect_tog;
u32 usb2_chrg_detect;
u32 usb2_chrg_detect_set;
u32 usb2_chrg_detect_clr;
u32 usb2_chrg_detect_tog;
u32 usb2_vbus_det_stat;
u32 usb2_vbus_det_stat_set;
u32 usb2_vbus_det_stat_clr;
u32 usb2_vbus_det_stat_tog;
u32 usb2_chrg_det_stat;
u32 usb2_chrg_det_stat_set;
u32 usb2_chrg_det_stat_clr;
u32 usb2_chrg_det_stat_tog;
u32 usb2_loopback;
u32 usb2_loopback_set;
u32 usb2_loopback_clr;
u32 usb2_loopback_tog;
u32 usb2_misc;
u32 usb2_misc_set;
u32 usb2_misc_clr;
u32 usb2_misc_tog;
u32 digprog;
u32 reserved1[7];
/* For i.MX 6SoloLite */
u32 digprog_sololite;
};
#endif
......@@ -1136,4 +1227,16 @@ struct mxc_ccm_reg {
#define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008
#define BM_PMU_MISC2_AUDIO_DIV_MSB (1 << 23)
#define BP_PMU_MISC2_AUDIO_DIV_MSB 23
#define BM_PMU_MISC2_AUDIO_DIV_LSB (1 << 15)
#define BP_PMU_MISC2_AUDIO_DIV_LSB 15
#define PMU_MISC2_AUDIO_DIV(v) \
(((v & BM_PMU_MISC2_AUDIO_DIV_MSB) >> \
(BP_PMU_MISC2_AUDIO_DIV_MSB - 1)) | \
((v & BM_PMU_MISC2_AUDIO_DIV_LSB) >> \
BP_PMU_MISC2_AUDIO_DIV_LSB))
#endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */
......@@ -272,6 +272,8 @@ struct src {
#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT 5
#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK 0x40u
#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT 6
#define IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK (3 << 7)
#define IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_SHIFT 7
/* GPR1 Bit Fields */
#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_MASK 0x1u
#define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_SHIFT 0
......
......@@ -59,7 +59,7 @@ enum {
MXS_DMA_CHANNEL_AHB_APBH_RESERVED1,
MXS_MAX_DMA_CHANNELS,
};
#elif defined(CONFIG_MX6)
#elif defined(CONFIG_MX6) || defined(CONFIG_MX7)
enum {
MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0,
MXS_DMA_CHANNEL_AHB_APBH_GPMI1,
......
......@@ -96,7 +96,7 @@ struct mxs_apbh_regs {
mxs_reg_32(hw_apbh_version)
};
#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6))
#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7))
struct mxs_apbh_regs {
mxs_reg_32(hw_apbh_ctrl0)
mxs_reg_32(hw_apbh_ctrl1)
......@@ -275,7 +275,7 @@ struct mxs_apbh_regs {
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800
#define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000
#define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000
#elif defined(CONFIG_MX6)
#elif (defined(CONFIG_MX6) || defined(CONFIG_MX7))
#define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0001
#define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0002
......@@ -391,7 +391,7 @@ struct mxs_apbh_regs {
#define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000
#endif
#if defined(CONFIG_MX6)
#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
#define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16
#endif
......
......@@ -123,7 +123,7 @@ struct mxs_bch_regs {
#define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24
#define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16)
#define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16
#if defined(CONFIG_MX6)
#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
#define BCH_FLASHLAYOUT0_ECC0_MASK (0x1f << 11)
#define BCH_FLASHLAYOUT0_ECC0_OFFSET 11
#else
......@@ -154,7 +154,7 @@ struct mxs_bch_regs {
#define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16)
#define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16
#if defined(CONFIG_MX6)
#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
#define BCH_FLASHLAYOUT1_ECCN_MASK (0x1f << 11)
#define BCH_FLASHLAYOUT1_ECCN_OFFSET 11
#else
......
......@@ -7,4 +7,3 @@
#
obj-y := mx25pdk.o
obj-y += lowlevel_init.o
/*
* Copyright (c) 2011 Freescale Semiconductor
*
* SPDX-License-Identifier: GPL-2.0+
*/
.globl lowlevel_init
lowlevel_init:
mov pc, lr
......@@ -186,3 +186,6 @@ int checkboard(void)
return 0;
}
/* Lowlevel init isn't used on mx25pdk, so just provide a dummy one here */
void lowlevel_init(void) {}
......@@ -47,6 +47,9 @@ DECLARE_GLOBAL_DATA_PTR;
#define QSPI_PAD_CTRL \
(PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)
#define NAND_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_SLOW | PAD_CTL_HYS)
#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
#ifdef CONFIG_SYS_I2C_MXC
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
/* I2C1 for PMIC */
......@@ -196,6 +199,38 @@ static void iox74lv_init(void)
gpio_direction_output(IOX_STCP, 1);
};
#ifdef CONFIG_NAND_MXS
static iomux_v3_cfg_t const gpmi_pads[] = {
MX7D_PAD_SD3_DATA0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX7D_PAD_SD3_DATA1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX7D_PAD_SD3_DATA2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX7D_PAD_SD3_DATA3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX7D_PAD_SD3_DATA4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX7D_PAD_SD3_DATA5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX7D_PAD_SD3_DATA6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX7D_PAD_SD3_DATA7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX7D_PAD_SD3_CLK__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX7D_PAD_SD3_CMD__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX7D_PAD_SD3_STROBE__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX7D_PAD_SD3_RESET_B__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX7D_PAD_SAI1_MCLK__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX7D_PAD_SAI1_RX_BCLK__NAND_CE3_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX7D_PAD_SAI1_RX_SYNC__NAND_CE2_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX7D_PAD_SAI1_RX_DATA__NAND_CE1_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX7D_PAD_SAI1_TX_BCLK__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX7D_PAD_SAI1_TX_SYNC__NAND_DQS | MUX_PAD_CTRL(NAND_PAD_CTRL),
MX7D_PAD_SAI1_TX_DATA__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_READY0_CTRL),
};
static void setup_gpmi_nand(void)
{
imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads));
/* NAND_USDHC_BUS_CLK is set in rom */
set_clk_nand();
}
#endif
#ifdef CONFIG_VIDEO_MXS
static iomux_v3_cfg_t const lcd_pads[] = {
MX7D_PAD_LCD_CLK__LCD_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
......@@ -503,6 +538,10 @@ int board_init(void)
setup_fec();
#endif
#ifdef CONFIG_NAND_MXS
setup_gpmi_nand();
#endif
#ifdef CONFIG_VIDEO_MXS
setup_lcd();
#endif
......
......@@ -215,7 +215,7 @@ static int mxs_dma_reset(int channel)
#if defined(CONFIG_MX23)
uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_ctrl0_set);
uint32_t offset = APBH_CTRL0_RESET_CHANNEL_OFFSET;
#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6))
#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7))
uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_channel_ctrl_set);
uint32_t offset = APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET;
#endif
......
......@@ -30,7 +30,7 @@
#define MXS_NAND_DMA_DESCRIPTOR_COUNT 4
#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE 512
#if defined(CONFIG_MX6)
#if (defined(CONFIG_MX6) || defined(CONFIG_MX7))
#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 2
#else
#define MXS_NAND_CHUNK_DATA_CHUNK_SIZE_SHIFT 0
......@@ -152,7 +152,7 @@ static inline uint32_t mxs_nand_get_ecc_strength(uint32_t page_data_size,
int max_ecc_strength_supported;
/* Refer to Chapter 17 for i.MX6DQ, Chapter 18 for i.MX6SX */
if (is_cpu_type(MXC_CPU_MX6SX))
if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7))
max_ecc_strength_supported = 62;
else
max_ecc_strength_supported = 40;
......
......@@ -34,6 +34,7 @@
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_WATCHDOG_SUPPORT
/* NAND support */
#if defined(CONFIG_SPL_NAND_SUPPORT)
......
......@@ -25,6 +25,8 @@
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_BOOTM_LEN 0x1000000
#include <linux/sizes.h>
#include <asm/arch/imx-regs.h>
#include <asm/imx-common/gpio.h>
......
......@@ -156,7 +156,7 @@
/* Miscellaneous configurable options */
#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000000)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x8000000)
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
#define CONFIG_SYS_HZ 1000
......@@ -203,6 +203,7 @@
#define CONFIG_SF_DEFAULT_CS 0
#define CONFIG_SF_DEFAULT_SPEED 40000000
#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
#define CONFIG_SPI_FLASH_STMICRO
#define FSL_QSPI_FLASH_NUM 1
#define FSL_QSPI_FLASH_SIZE SZ_32M
#endif
......
......@@ -23,6 +23,8 @@
#define CONFIG_SC_TIMER_CLK 8000000 /* 8Mhz */
#define CONFIG_SYS_FSL_CLK
#define CONFIG_SYS_BOOTM_LEN 0x1000000
/* Enable iomux-lpsr support */
#define CONFIG_IOMUX_LPSR
#define CONFIG_IMX_FIXED_IVT_OFFSET
......
......@@ -179,8 +179,33 @@
#define CONFIG_SYS_NO_FLASH
#define CONFIG_ENV_SIZE SZ_8K
#define CONFIG_ENV_IS_IN_MMC
/*
* If want to use nand, define CONFIG_NAND_MXS and rework board
* to support nand, since emmc has pin conflicts with nand
*/
#ifdef CONFIG_NAND_MXS
#define CONFIG_CMD_NAND
#define CONFIG_CMD_NAND_TRIMFFS
/* NAND stuff */
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
#define CONFIG_SYS_NAND_ONFI_DETECTION
/* DMA stuff, needed for GPMI/MXS NAND support */
#define CONFIG_APBH_DMA
#define CONFIG_APBH_DMA_BURST
#define CONFIG_APBH_DMA_BURST8
#endif
#define CONFIG_ENV_OFFSET (8 * SZ_64K)
#ifdef CONFIG_NAND_MXS
#define CONFIG_SYS_FSL_USDHC_NUM 1
#else
#define CONFIG_SYS_FSL_USDHC_NUM 2
#endif
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment