Commit 230187ce authored by Tom Rini's avatar Tom Rini
Browse files

Merge branch 'master' of git://git.denx.de/u-boot-mips



Conflict over SPDX changes means that one change was effectively dropped
as it was fixing typos in a removed hunk of text.

Conflicts:
	arch/mips/cpu/mips64/start.S
Signed-off-by: default avatarTom Rini <trini@ti.com>
parents 8dde4ca9 db2c86d7
......@@ -18,7 +18,7 @@
#define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
#endif
#define RA t8
#define RA t9
/*
* 16kB is the maximum size of instruction and data caches on MIPS 4K,
......@@ -128,8 +128,7 @@ NESTED(mips_cache_reset, 0, ra)
move RA, ra
li t2, CONFIG_SYS_ICACHE_SIZE
li t3, CONFIG_SYS_DCACHE_SIZE
li t4, CONFIG_SYS_CACHELINE_SIZE
move t5, t4
li t8, CONFIG_SYS_CACHELINE_SIZE
li v0, MIPS_MAX_CACHE_SIZE
......@@ -156,17 +155,17 @@ NESTED(mips_cache_reset, 0, ra)
* Initialize the I-cache first,
*/
move a1, t2
move a2, t4
PTR_LA t7, mips_init_icache
jalr t7
move a2, t8
PTR_LA v1, mips_init_icache
jalr v1
/*
* then initialize D-cache.
*/
move a1, t3
move a2, t5
PTR_LA t7, mips_init_dcache
jalr t7
move a2, t8
PTR_LA v1, mips_init_dcache
jalr v1
jr RA
END(mips_cache_reset)
......
......@@ -41,7 +41,7 @@ _start:
nop
.org 0x10
#ifdef CONFIG_SYS_XWAY_EBU_BOOTCFG
#if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
/*
* Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
* access external NOR flashes. If the board boots from NOR flash the
......@@ -51,6 +51,12 @@ _start:
*/
.word CONFIG_SYS_XWAY_EBU_BOOTCFG
.word 0x0
#elif defined(CONFIG_QEMU_MALTA)
/*
* Linux expects the Board ID here.
*/
.word 0x00000420 # 0x420 (Malta Board with CoreLV)
.word 0x00000000
#endif
.org 0x200
......@@ -199,19 +205,19 @@ in_ram:
* generated by GNU ld. Skip these reserved entries from relocation.
*/
lw t3, -4(t0) # t3 <-- num_got_entries
lw t4, -8(t0) # t4 <-- _GLOBAL_OFFSET_TABLE_
add t4, s1 # t4 now holds relocated _G_O_T_
addi t4, t4, 8 # skipping first two entries
lw t8, -8(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
add t8, s1 # t8 now holds relocated _G_O_T_
addi t8, t8, 8 # skipping first two entries
li t2, 2
1:
lw t1, 0(t4)
lw t1, 0(t8)
beqz t1, 2f
add t1, s1
sw t1, 0(t4)
sw t1, 0(t8)
2:
addi t2, 1
blt t2, t3, 1b
addi t4, 4
addi t8, 4
/* Update dynamic relocations */
lw t1, -16(t0) # t1 <-- __rel_dyn_start
......@@ -221,19 +227,19 @@ in_ram:
addi t1, 8
1:
lw t3, -4(t1) # t3 <-- relocation info
lw t8, -4(t1) # t8 <-- relocation info
sub t3, 3
bnez t3, 2f # skip non R_MIPS_REL32 entries
li t3, 3
bne t8, t3, 2f # skip non R_MIPS_REL32 entries
nop
lw t3, -8(t1) # t3 <-- location to fix up in FLASH
lw t4, 0(t3) # t4 <-- original pointer
add t4, s1 # t4 <-- adjusted pointer
lw t8, 0(t3) # t8 <-- original pointer
add t8, s1 # t8 <-- adjusted pointer
add t3, s1 # t3 <-- location to fix up in RAM
sw t4, 0(t3)
sw t8, 0(t3)
2:
blt t1, t2, 1b
......
......@@ -11,7 +11,8 @@
static unsigned long timestamp;
/* how many counter cycles in a jiffy */
#define CYCLES_PER_JIFFY (CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ
#define CYCLES_PER_JIFFY \
(CONFIG_SYS_MIPS_TIMER_FREQ + CONFIG_SYS_HZ / 2) / CONFIG_SYS_HZ
/*
* timer without interrupts
......@@ -38,7 +39,7 @@ ulong get_timer(ulong base)
}
write_c0_compare(expirelo);
return (timestamp - base);
return timestamp - base;
}
void __udelay(unsigned long usec)
......
......@@ -6,7 +6,6 @@
*/
#include <common.h>
#include <asm/mipsregs.h>
void enable_interrupts(void)
{
......
......@@ -3,7 +3,7 @@
*
* Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
*
* SPDX-License-Identifier: GPL-2.0+
* SPDX-License-Identifier: GPL-2.0+
*/
#include <asm-offsets.h>
......
......@@ -47,14 +47,17 @@ _start:
relocate_code:
move sp, a0 # set new stack pointer
move s0, a1 # save gd in s0
move s2, a2 # save destination address in s2
li t0, CONFIG_SYS_MONITOR_BASE
sub t6, a2, t0 # t6 <-- relocation offset
sub s1, s2, t0 # s1 <-- relocation offset
la t3, in_ram
lw t2, -12(t3) # t2 <-- __image_copy_end
move t1, a2
add gp, t6 # adjust gp
add gp, s1 # adjust gp
/*
* t0 = source address
......@@ -96,7 +99,7 @@ relocate_code:
nop
/* Jump to where we've relocated ourselves */
addi t0, a2, in_ram - _start
addi t0, s2, in_ram - _start
jr t0
nop
......@@ -114,19 +117,19 @@ in_ram:
* generated by GNU ld. Skip these reserved entries from relocation.
*/
lw t3, -4(t0) # t3 <-- num_got_entries
lw t4, -8(t0) # t4 <-- _GLOBAL_OFFSET_TABLE_
add t4, t6 # t4 now holds relocated _G_O_T_
addi t4, t4, 8 # skipping first two entries
lw t8, -8(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
add t8, s1 # t8 now holds relocated _G_O_T_
addi t8, t8, 8 # skipping first two entries
li t2, 2
1:
lw t1, 0(t4)
lw t1, 0(t8)
beqz t1, 2f
add t1, t6
sw t1, 0(t4)
add t1, s1
sw t1, 0(t8)
2:
addi t2, 1
blt t2, t3, 1b
addi t4, 4
addi t8, 4
/* Update dynamic relocations */
lw t1, -16(t0) # t1 <-- __rel_dyn_start
......@@ -136,19 +139,19 @@ in_ram:
addi t1, 8
1:
lw t3, -4(t1) # t3 <-- relocation info
lw t8, -4(t1) # t8 <-- relocation info
sub t3, 3
bnez t3, 2f # skip non R_MIPS_REL32 entries
li t3, 3
bne t8, t3, 2f # skip non R_MIPS_REL32 entries
nop
lw t3, -8(t1) # t3 <-- location to fix up in FLASH
lw t4, 0(t3) # t4 <-- original pointer
add t4, t6 # t4 <-- adjusted pointer
lw t8, 0(t3) # t8 <-- original pointer
add t8, s1 # t8 <-- adjusted pointer
add t3, t6 # t3 <-- location to fix up in RAM
sw t4, 0(t3)
add t3, s1 # t3 <-- location to fix up in RAM
sw t8, 0(t3)
2:
blt t1, t2, 1b
......@@ -168,9 +171,9 @@ in_ram:
blt t1, t2, 1b
addi t1, 4
move a0, a1 # a0 <-- gd
move a0, s0 # a0 <-- gd
la t9, board_init_r
jr t9
move a1, a2
move a1, s2
.end relocate_code
/*
* Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#ifndef _MIPS_ASM_MALTA_H
#define _MIPS_ASM_MALTA_H
#define MALTA_IO_PORT_BASE 0x18000000
#define MALTA_UART_BASE (MALTA_IO_PORT_BASE + 0x3f8)
#define MALTA_GT_BASE 0x1be00000
#define MALTA_RESET_BASE 0x1f000500
#define GORESET 0x42
#define MALTA_FLASH_BASE 0x1fc00000
#endif /* _MIPS_ASM_MALTA_H */
#
# (C) Copyright 2003-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).o
COBJS = $(BOARD).o
SOBJS = lowlevel_init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
$(call cmd_link_o_target, $(OBJS) $(SOBJS))
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################
/*
* Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <config.h>
#include <gt64120.h>
#include <asm/addrspace.h>
#include <asm/regdef.h>
#include <asm/malta.h>
#ifdef CONFIG_SYS_BIG_ENDIAN
#define CPU_TO_GT32(_x) ((_x))
#else
#define CPU_TO_GT32(_x) ( \
(((_x) & 0xff) << 24) | (((_x) & 0xff00) << 8) | \
(((_x) & 0xff0000) >> 8) | (((_x) & 0xff000000) >> 24))
#endif
.text
.set noreorder
.set mips32
.globl lowlevel_init
lowlevel_init:
/*
* Load BAR registers of GT64120 as done by YAMON
*
* based on a patch sent by Antony Pavlov <antonynpavlov@gmail.com>
* to the barebox mailing list.
* The subject of the original patch:
* 'MIPS: qemu-malta: add YAMON-style GT64120 memory map'
* URL:
* http://www.mail-archive.com/barebox@lists.infradead.org/msg06128.html
*
* based on write_bootloader() in qemu.git/hw/mips_malta.c
* see GT64120 manual and qemu.git/hw/gt64xxx.c for details
*/
/* move GT64120 registers from 0x14000000 to 0x1be00000 */
li t1, KSEG1ADDR(GT_DEF_BASE)
li t0, CPU_TO_GT32(0xdf000000)
sw t0, GT_ISD_OFS(t1)
/* setup MEM-to-PCI0 mapping */
li t1, KSEG1ADDR(MALTA_GT_BASE)
/* setup PCI0 io window to 0x18000000-0x181fffff */
li t0, CPU_TO_GT32(0xc0000000)
sw t0, GT_PCI0IOLD_OFS(t1)
li t0, CPU_TO_GT32(0x40000000)
sw t0, GT_PCI0IOHD_OFS(t1)
/* setup PCI0 mem windows */
li t0, CPU_TO_GT32(0x80000000)
sw t0, GT_PCI0M0LD_OFS(t1)
li t0, CPU_TO_GT32(0x3f000000)
sw t0, GT_PCI0M0HD_OFS(t1)
li t0, CPU_TO_GT32(0xc1000000)
sw t0, GT_PCI0M1LD_OFS(t1)
li t0, CPU_TO_GT32(0x5e000000)
sw t0, GT_PCI0M1HD_OFS(t1)
jr ra
nop
/*
* Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <common.h>
#include <netdev.h>
#include <asm/addrspace.h>
#include <asm/io.h>
#include <asm/malta.h>
#include <pci_gt64120.h>
phys_size_t initdram(int board_type)
{
return CONFIG_SYS_MEM_SIZE;
}
int checkboard(void)
{
puts("Board: MIPS Malta CoreLV (Qemu)\n");
return 0;
}
int board_eth_init(bd_t *bis)
{
return pci_eth_init(bis);
}
void _machine_restart(void)
{
void __iomem *reset_base;
reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE);
__raw_writel(GORESET, reset_base);
}
void pci_init_board(void)
{
set_io_port_base(CKSEG1ADDR(MALTA_IO_PORT_BASE));
gt64120_pci_init((void *)CKSEG1ADDR(MALTA_GT_BASE),
0x00000000, 0x00000000, CONFIG_SYS_MEM_SIZE,
0x10000000, 0x10000000, 128 * 1024 * 1024,
0x00000000, 0x00000000, 0x20000);
}
......@@ -470,6 +470,8 @@ qemu_mips mips mips32 qemu-mips -
qemu_mipsel mips mips32 qemu-mips - - qemu-mips:SYS_LITTLE_ENDIAN
qemu_mips64 mips mips64 qemu-mips - - qemu-mips64:SYS_BIG_ENDIAN
qemu_mips64el mips mips64 qemu-mips - - qemu-mips64:SYS_LITTLE_ENDIAN
qemu_malta mips mips32 qemu-malta - - qemu-malta:MIPS32,SYS_BIG_ENDIAN
qemu_maltael mips mips32 qemu-malta - - qemu-malta:MIPS32,SYS_LITTLE_ENDIAN
vct_platinum mips mips32 vct micronas - vct:VCT_PLATINUM
vct_platinumavc mips mips32 vct micronas - vct:VCT_PLATINUMAVC
vct_platinumavc_onenand mips mips32 vct micronas - vct:VCT_PLATINUMAVC,VCT_ONENAND
......
......@@ -39,8 +39,6 @@ TODOs
* Secondary cache support missing
* Centralize the link directive files
* Initialize TLB entries redardless of their use
* R2000/R3000 class parts are not supported
......@@ -51,8 +49,6 @@ TODOs
initialized in board specific assembler language before the cache init
code is run -- that is, initialize the DRAM in lowlevel_init().
* get rid of CONFIG_MANUAL_RELOC
* centralize/share more CPU code of MIPS32, MIPS64 and XBurst
* support Qemu Malta
......@@ -130,7 +130,7 @@ static int pcnet_recv (struct eth_device *dev);
static void pcnet_halt (struct eth_device *dev);
static int pcnet_probe (struct eth_device *dev, bd_t * bis, int dev_num);
#define PCI_TO_MEM(d,a) pci_phys_to_mem((pci_dev_t)d->priv, (u_long)(a))
#define PCI_TO_MEM(d, a) pci_virt_to_mem((pci_dev_t)d->priv, (a))
#define PCI_TO_MEM_LE(d,a) (u32)(cpu_to_le32(PCI_TO_MEM(d,a)))
static struct pci_device_id supported[] = {
......
......@@ -12,6 +12,7 @@ LIB := $(obj)libpci.o
COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_pci_init.o
COBJS-$(CONFIG_PCI) += pci.o pci_auto.o
COBJS-$(CONFIG_PCI_INDIRECT_BRIDGE) += pci_indirect.o
COBJS-$(CONFIG_PCI_GT64120) += pci_gt64120.o
COBJS-$(CONFIG_FTPCI100) += pci_ftpci100.o
COBJS-$(CONFIG_IXP_PCI) += pci_ixp.o
COBJS-$(CONFIG_SH4_PCI) += pci_sh4.o
......
/*
* Copyright (C) 2013 Gabor Juhos <juhosg@openwrt.org>
*
* Based on the Linux implementation.
* Copyright (C) 1999, 2000, 2004 MIPS Technologies, Inc.
* Authors: Carsten Langgaard <carstenl@mips.com>
* Maciej W. Rozycki <macro@mips.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation.
*/
#include <common.h>
#include <gt64120.h>
#include <pci.h>
#include <pci_gt64120.h>
#include <asm/io.h>
#define PCI_ACCESS_READ 0
#define PCI_ACCESS_WRITE 1
struct gt64120_regs {
u8 unused_000[0xc18];
u32 intrcause;
u8 unused_c1c[0x0dc];
u32 pci0_cfgaddr;
u32 pci0_cfgdata;
};
struct gt64120_pci_controller {
struct pci_controller hose;
struct gt64120_regs *regs;
};
static inline struct gt64120_pci_controller *
hose_to_gt64120(struct pci_controller *hose)
{
return container_of(hose, struct gt64120_pci_controller, hose);
}
#define GT_INTRCAUSE_ABORT_BITS \
(GT_INTRCAUSE_MASABORT0_BIT | GT_INTRCAUSE_TARABORT0_BIT)
static int gt_config_access(struct gt64120_pci_controller *gt,
unsigned char access_type, pci_dev_t bdf,
int where, u32 *data)
{
unsigned int bus = PCI_BUS(bdf);
unsigned int dev = PCI_DEV(bdf);
unsigned int devfn = PCI_DEV(bdf) << 3 | PCI_FUNC(bdf);
u32 intr;
u32 addr;
u32 val;
if (bus == 0 && dev >= 31) {
/* Because of a bug in the galileo (for slot 31). */
return -1;
}
if (access_type == PCI_ACCESS_WRITE)
debug("PCI WR %02x:%02x.%x reg:%02d data:%08x\n",
PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), where, *data);
/* Clear cause register bits */
writel(~GT_INTRCAUSE_ABORT_BITS, &gt->regs->intrcause);
addr = GT_PCI0_CFGADDR_CONFIGEN_BIT;
addr |= bus << GT_PCI0_CFGADDR_BUSNUM_SHF;
addr |= devfn << GT_PCI0_CFGADDR_FUNCTNUM_SHF;
addr |= (where / 4) << GT_PCI0_CFGADDR_REGNUM_SHF;
/* Setup address */
writel(addr, &gt->regs->pci0_cfgaddr);
if (access_type == PCI_ACCESS_WRITE) {
if (bus == 0 && dev == 0) {
/*
* The Galileo system controller is acting
* differently than other devices.
*/
val = *data;
} else {
val = cpu_to_le32(*data);
}
writel(val, &gt->regs->pci0_cfgdata);
} else {
val = readl(&gt->regs->pci0_cfgdata);
if (bus == 0 && dev == 0) {
/*
* The Galileo system controller is acting
* differently than other devices.
*/
*data = val;
} else {
*data = le32_to_cpu(val);
}
}
/* Check for master or target abort */
intr = readl(&gt->regs->intrcause);
if (intr & GT_INTRCAUSE_ABORT_BITS) {
/* Error occurred, clear abort bits */
writel(~GT_INTRCAUSE_ABORT_BITS, &gt->regs->intrcause);
return -1;
}
if (access_type == PCI_ACCESS_READ)
debug("PCI RD %02x:%02x.%x reg:%02d data:%08x\n",
PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf), where, *data);
return 0;
}
static int gt_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
int where, u32 *value)
{
struct gt64120_pci_controller *gt = hose_to_gt64120(hose);
*value = 0xffffffff;
return gt_config_access(gt, PCI_ACCESS_READ, dev, where, value);
}
static int gt_write_config_dword(struct pci_controller *hose, pci_dev_t dev,
int where, u32 value)
{