Commit 2482e3c8 authored by Anton Staaf's avatar Anton Staaf Committed by Wolfgang Denk
Browse files

sh: cache: define ARCH_DMA_MINALIGN for DMA buffer alignment


Signed-off-by: default avatarAnton Staaf <robotboy@chromium.org>
Cc: Mike Frysinger <vapier@gentoo.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
parent 0991701a
......@@ -6,6 +6,7 @@
int cache_control(unsigned int cmd);
#define L1_CACHE_BYTES 32
struct __large_struct { unsigned long buf[100]; };
#define __m(x) (*(struct __large_struct *)(x))
......@@ -30,6 +31,22 @@ void dcache_invalid_range(u32 start, u32 end)
: "m" (__m(v)));
}
}
#else
/*
* 32-bytes is the largest L1 data cache line size for SH the architecture. So
* it is a safe default for DMA alignment.
*/
#define ARCH_DMA_MINALIGN 32
#endif /* CONFIG_SH4 || CONFIG_SH4A */
/*
* Use the L1 data cache line size value for the minimum DMA buffer alignment
* on SH.
*/
#ifndef ARCH_DMA_MINALIGN
#define ARCH_DMA_MINALIGN L1_CACHE_BYTES
#endif
#endif /* __ASM_SH_CACHE_H */
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